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From: "Alex Bennée" <alex.bennee@linaro.org>
To: peter.maydell@linaro.org
Cc: Dave.Martin@arm.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: [Qemu-devel] [RISU PATCH 04/10] risu: move optional args to each architecture
Date: Tue,  7 Nov 2017 15:05:52 +0000	[thread overview]
Message-ID: <20171107150558.22131-5-alex.bennee@linaro.org> (raw)
In-Reply-To: <20171107150558.22131-1-alex.bennee@linaro.org>

The key variables here are: *arch_long_opts and *arch_extra_help. If
they are not NULL then we concatenate the extra options to appropriate
structure to enable the support. Adding architecture short options is
not supported.

This also includes moving the ARM specific test_fp_exc/test-fp-exc
into ARM specific code.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 risu.c                 | 31 ++++++++++++++++++++++++++-----
 risu.h                 |  6 ++++--
 risu_reginfo_aarch64.c |  3 +++
 risu_reginfo_arm.c     | 11 +++++++++++
 risu_reginfo_m68k.c    |  3 +++
 risu_reginfo_ppc64.c   |  3 +++
 6 files changed, 50 insertions(+), 7 deletions(-)

diff --git a/risu.c b/risu.c
index 616fc33..f063093 100644
--- a/risu.c
+++ b/risu.c
@@ -43,9 +43,6 @@ gzFile gz_trace_file;
 
 sigjmp_buf jmpbuf;
 
-/* Should we test for FP exception status bits? */
-int test_fp_exc;
-
 /* Master functions */
 
 int read_sock(void *ptr, size_t bytes)
@@ -280,6 +277,9 @@ void usage(void)
     fprintf(stderr,
             "  -p, --port=PORT   Specify the port to connect to/listen on "
             "(default 9191)\n");
+    if (arch_extra_help) {
+        fprintf(stderr, "%s", arch_extra_help);
+    }
 }
 
 struct option * setup_options(char **short_opts)
@@ -290,12 +290,33 @@ struct option * setup_options(char **short_opts)
         {"host", required_argument, 0, 'h'},
         {"port", required_argument, 0, 'p'},
         {"trace", required_argument, 0, 't'},
-        {"test-fp-exc", no_argument, &test_fp_exc, 1},
         {0, 0, 0, 0}
     };
+    struct option *lopts = &default_longopts[0];
 
     *short_opts = "h:p:t:";
-    return default_longopts;
+
+    if (arch_long_opts) {
+        struct option *dptr, *sptr;
+        size_t osize = sizeof(default_longopts);
+        lopts = malloc(osize);
+        /* Copy default opts */
+        memcpy(lopts, default_longopts, osize);
+        dptr = lopts;
+        while (dptr->name) {
+            dptr++;
+        }
+        /* Copy extra opts */
+        sptr = arch_long_opts;
+        while (sptr->name) {
+            osize += sizeof(struct option);
+            lopts = realloc(lopts, osize);
+            *dptr++ = *sptr++;
+        }
+        memset(dptr, 0, sizeof(struct option));
+    }
+
+    return lopts;
 }
 
 int main(int argc, char **argv)
diff --git a/risu.h b/risu.h
index 1c8ecee..89811f4 100644
--- a/risu.h
+++ b/risu.h
@@ -17,6 +17,10 @@
 #include <ucontext.h>
 #include <stdio.h>
 
+/* Extra option processing for architectures */
+extern void *arch_long_opts;
+extern char *arch_extra_help;
+
 /* GCC computed include to pull in the correct risu_reginfo_*.h for
  * the architecture.
  */
@@ -36,8 +40,6 @@ void send_response_byte(int sock, int resp);
 extern uintptr_t image_start_address;
 extern void *memblock;
 
-extern int test_fp_exc;
-
 /* Ops code under test can request from risu: */
 #define OP_COMPARE 0
 #define OP_TESTEND 1
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index e3fadde..38ad338 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -17,6 +17,9 @@
 #include "risu.h"
 #include "risu_reginfo_aarch64.h"
 
+void *arch_long_opts;
+char *arch_extra_help;
+
 /* reginfo_init: initialize with a ucontext */
 void reginfo_init(struct reginfo *ri, ucontext_t *uc)
 {
diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c
index 6b9ee7b..5acad02 100644
--- a/risu_reginfo_arm.c
+++ b/risu_reginfo_arm.c
@@ -13,12 +13,23 @@
 #include <stdio.h>
 #include <ucontext.h>
 #include <string.h>
+#include <getopt.h>
 
 #include "risu.h"
 #include "risu_reginfo_arm.h"
 
 extern int insnsize(ucontext_t *uc);
 
+/* Should we test for FP exception status bits? */
+static int test_fp_exc;
+static struct option extra_opts[] = {
+    {"test-fp-exc", no_argument, &test_fp_exc, 1},
+    {0, 0, 0, 0}
+};
+
+void *arch_long_opts = &extra_opts[0];
+char *arch_extra_help = "  --test-fp-exc     Check FP exception bits when comparing\n";
+
 static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc)
 {
     /* Read VFP registers. These live in uc->uc_regspace, which is
diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c
index 4ff0aa8..d429502 100644
--- a/risu_reginfo_m68k.c
+++ b/risu_reginfo_m68k.c
@@ -14,6 +14,9 @@
 #include "risu.h"
 #include "risu_reginfo_m68k.h"
 
+void *arch_long_opts;
+char *arch_extra_help;
+
 /* reginfo_init: initialize with a ucontext */
 void reginfo_init(struct reginfo *ri, ucontext_t *uc)
 {
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index eb9c12b..aa5d8c6 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -22,6 +22,9 @@
 #define XER 37
 #define CCR 38
 
+void *arch_long_opts;
+char *arch_extra_help;
+
 /* reginfo_init: initialize with a ucontext */
 void reginfo_init(struct reginfo *ri, ucontext_t *uc)
 {
-- 
2.14.2

  parent reply	other threads:[~2017-11-07 15:06 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-07 15:05 [Qemu-devel] [RISU PATCH 00/10] Initial support for SVE Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 01/10] build-all-arches: drop -t (for tty) from docker invocation Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 02/10] risu.c: split out setting up options Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 03/10] risu.c: add missing --trace longopt Alex Bennée
2017-11-07 15:05 ` Alex Bennée [this message]
2017-11-09  8:13   ` [Qemu-devel] [RISU PATCH 04/10] risu: move optional args to each architecture Richard Henderson
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 05/10] configure: allow repeated invocation of configure in build dir Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 06/10] configure: support CPPFLAGS Alex Bennée
2017-11-08 10:34   ` Dave Martin
2017-11-08 11:02     ` Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 07/10] risugen: add --sve support Alex Bennée
2017-11-09  8:18   ` Richard Henderson
2017-11-09 12:21   ` Dave Martin
2017-11-09 14:50     ` Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 08/10] aarch64.risu: initial SVE instruction Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 09/10] risu_reginfo_aarch64: add reginfo_copy_sve Alex Bennée
2017-11-08 10:46   ` Dave Martin
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 10/10] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch Alex Bennée
2017-11-08 10:58   ` Dave Martin
2017-11-08 11:41     ` Alex Bennée
2017-11-08 10:36 ` [Qemu-devel] [RISU PATCH 00/10] Initial support for SVE Dave Martin
2017-11-08 11:02   ` Alex Bennée
2017-11-08 11:12     ` Dave Martin
2017-11-21 16:51 ` Peter Maydell

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