From: "Alex Bennée" <alex.bennee@linaro.org>
To: peter.maydell@linaro.org
Cc: Dave.Martin@arm.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: [Qemu-devel] [RISU PATCH 08/10] aarch64.risu: initial SVE instruction
Date: Tue, 7 Nov 2017 15:05:56 +0000 [thread overview]
Message-ID: <20171107150558.22131-9-alex.bennee@linaro.org> (raw)
In-Reply-To: <20171107150558.22131-1-alex.bennee@linaro.org>
---
aarch64.risu | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/aarch64.risu b/aarch64.risu
index 838bded..bfa4ff8 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2937,3 +2937,27 @@ FCVTZUsi_RES A64_V sf:1 0011110 1 type:1 1 11 001 000000 rn:5 rd:5
# End of:
# Data processing - SIMD and floating point
# Data processing - Scalar Floating-Point and Advanced SIMD
+
+# SVE Instructions
+# Top-level Encodings
+#
+# 31 24 | 23 22 | 21 17 | 16 | 15 10 | 9 0
+# y y y y y y y m | - - | m m m m m | - | | - - - - - - - - - -
+#
+@SVE
+
+# SVE Integer Arithmetic - Binary Predicated Group
+# 31 24 | 23 22 | 21 | 20 19 | 18 16 | 15 13 | 12 0
+# 0 0 0 0 0 1 0 0 | size | 0 | op | --- | 0 0 0 | ------------- |
+
+SVE_INTA_PRED_UNALL A64_V 00000100 ig:2 010 001 000 ignore2:13
+
+# - SVE integer add/subtract vectors (predicated)
+# 31 24 | 23 22 | 21 19 | 18 16 | 15 13 | 12 10 | 9 5 | 4 0 |
+# 0 0 0 0 0 1 0 0 | size | 0 0 0 | opc | 0 0 0 | Pg | Zm | Zn |
+# opc 010/1xx are UNALLOCATED
+
+SVE_INT_ADDSUB_PRED A64_V 00000100 sz:2 000 opc:3 000 pg:3 zm:5 zn:5
+
+@
+# End of SVE instructions
--
2.14.2
next prev parent reply other threads:[~2017-11-07 15:06 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-07 15:05 [Qemu-devel] [RISU PATCH 00/10] Initial support for SVE Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 01/10] build-all-arches: drop -t (for tty) from docker invocation Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 02/10] risu.c: split out setting up options Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 03/10] risu.c: add missing --trace longopt Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 04/10] risu: move optional args to each architecture Alex Bennée
2017-11-09 8:13 ` Richard Henderson
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 05/10] configure: allow repeated invocation of configure in build dir Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 06/10] configure: support CPPFLAGS Alex Bennée
2017-11-08 10:34 ` Dave Martin
2017-11-08 11:02 ` Alex Bennée
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 07/10] risugen: add --sve support Alex Bennée
2017-11-09 8:18 ` Richard Henderson
2017-11-09 12:21 ` Dave Martin
2017-11-09 14:50 ` Alex Bennée
2017-11-07 15:05 ` Alex Bennée [this message]
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 09/10] risu_reginfo_aarch64: add reginfo_copy_sve Alex Bennée
2017-11-08 10:46 ` Dave Martin
2017-11-07 15:05 ` [Qemu-devel] [RISU PATCH 10/10] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch Alex Bennée
2017-11-08 10:58 ` Dave Martin
2017-11-08 11:41 ` Alex Bennée
2017-11-08 10:36 ` [Qemu-devel] [RISU PATCH 00/10] Initial support for SVE Dave Martin
2017-11-08 11:02 ` Alex Bennée
2017-11-08 11:12 ` Dave Martin
2017-11-21 16:51 ` Peter Maydell
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