Re: [Qemu-devel] [RISU PATCH 10/10] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch

[Dave Martin <Dave.Martin@arm.com>]

On Tue, Nov 07, 2017 at 03:05:58PM +0000, Alex Bennée wrote:
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>  risu_reginfo_aarch64.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
> index 7c97790..8aba192 100644
> --- a/risu_reginfo_aarch64.c
> +++ b/risu_reginfo_aarch64.c
> @@ -141,6 +141,18 @@ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
>      return memcmp(r1, r2, sizeof(*r1)) == 0;
>  }
>  
> +#ifdef SVE_MAGIC
> +static int sve_zreg_is_eq(struct reginfo *r1, struct reginfo *r2, int z)
> +{
> +    return memcmp(r1->zregs[z], r2->zregs[z], sizeof(*r1->zregs[z])) == 0;
> +}
> +
> +static int sve_preg_is_eq(struct reginfo *r1, struct reginfo *r2, int p)
> +{
> +    return memcmp(r1->pregs[p], r2->pregs[p], sizeof(*r1->pregs[p])) == 0;
> +}
> +#endif
> +
>  /* reginfo_dump: print state to a stream, returns nonzero on success */
>  int reginfo_dump(struct reginfo *ri, FILE * f)
>  {
> @@ -216,5 +228,42 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
>          }
>      }
>  
> +#ifdef SVE_MAGIC
> +    if (test_sve) {
> +        if (m->vl != a->vl) {
> +            fprintf(f, "  SVE VL  : %d vs %d\n", m->vl, a->vl);
> +        }
> +        for (i = 0; i < SVE_NUM_PREGS; i++) {
> +           if (!sve_preg_is_eq(m, a, i)) {
> +              int q;
> +              fprintf(f, "  P%2d   : ", i);
> +              for (q = 0; q < sve_vq_from_vl(m->vl); q++) {
> +                 fprintf(f, "%04x", m->pregs[i][q]);
> +              }
> +              fprintf(f, " vs ");
> +              for (q = 0; q < sve_vq_from_vl(m->vl); q++) {
> +                 fprintf(f, "%04x", a->pregs[i][q]);
> +              }
> +              fprintf(f, "\n");
> +            }
> +        }
> +        for (i = 0; i < SVE_NUM_ZREGS; i++) {
> +           if (!sve_zreg_is_eq(m, a, i)) {
> +              int q;
> +              char *pad="";
> +              fprintf(f, "  Z%2d   : ", i);
> +              for (q = 0; q < sve_vq_from_vl(m->vl); q++) {
> +                 if (m->zregs[i][q] != a->zregs[i][q]) {
> +                    fprintf(f, "%sq%02d: %016" PRIx64 "%016" PRIx64 " vs %016" PRIx64 "%016" PRIx64"\n", pad, q,
> +                            (uint64_t) (m->zregs[i][q] >> 64), (uint64_t) m->zregs[i][q],
> +                            (uint64_t) (a->zregs[i][q] >> 64), (uint64_t) a->zregs[i][q]);
> +                    pad = "          ";
> +                 }
> +              }
> +           }
> +        }

No FFR?

Perhaps I should have explicitly encoded FFR as "P16" -- that sort of
works and saves some open-coding of the extra special case, but it feels
less correct.

You could do

static int sve_preg_is_eq(uint16_t const (*p1)[SVE_VQ_MAX],
				uint16_t const (*p2)[SVE_VQ_MAX])
{
	return memcmp(p1, p2, sizeof *p1) == 0;
}

/* ... */

sve_preg_is_eq(&r1->pregs[p], &r2->pregs[p])

/* ... */

sve_preg_is_eq(&r1->ffr, &r2->ffr)

(or some variation on this theme).  ffr is a specialised predicate
register, so I think you can assume that it really does have the same
type as pregs[p].  Coding the above way will give a typcheck error if
not.

Cheers
---Dave