From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eILXs-0001am-T7 for qemu-devel@nongnu.org; Fri, 24 Nov 2017 16:30:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eILXs-0007co-4b for qemu-devel@nongnu.org; Fri, 24 Nov 2017 16:30:00 -0500 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:41366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eILXr-0007cb-TR for qemu-devel@nongnu.org; Fri, 24 Nov 2017 16:30:00 -0500 Received: by mail-lf0-x242.google.com with SMTP id f134so26674103lfg.8 for ; Fri, 24 Nov 2017 13:29:59 -0800 (PST) From: Francisco Iglesias Date: Fri, 24 Nov 2017 22:29:35 +0100 Message-Id: <20171124212938.7074-11-frasse.iglesias@gmail.com> In-Reply-To: <20171124212938.7074-1-frasse.iglesias@gmail.com> References: <20171124212938.7074-1-frasse.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v8 10/13] xilinx_spips: Add support for 4 byte addresses in the LQSPI List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com, peter.maydell@linaro.org Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis --- hw/ssi/xilinx_spips.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 878b17e..ab54da8 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -92,8 +92,9 @@ #define R_LQSPI_CFG_RESET 0x03A002EB #define LQSPI_CFG_LQ_MODE (1U << 31) #define LQSPI_CFG_TWO_MEM (1 << 30) -#define LQSPI_CFG_SEP_BUS (1 << 30) +#define LQSPI_CFG_SEP_BUS (1 << 29) #define LQSPI_CFG_U_PAGE (1 << 28) +#define LQSPI_CFG_ADDR4 (1 << 27) #define LQSPI_CFG_MODE_EN (1 << 25) #define LQSPI_CFG_MODE_WIDTH 8 #define LQSPI_CFG_MODE_SHIFT 16 @@ -702,6 +703,9 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); /* read address */ DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { + fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); + } fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); -- 2.9.3