[Qemu-devel] [PATCH v2 14/19] spapr: introduce a helper to map the XIVE memory regions

["Cédric Le Goater" <clg@kaod.org>]

When the XIVE exploitation interrupt mode is activated, the machine
needs to expose to the guest the MMIO regions used by the controller :

  - Event State Buffers
  - Thread Interrupt Management Area for the OS and User views

Migration will also need to reflect the current interrupt mode in use.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 Changes since v1:
 
 - moved the mapping of the XIVE memory region under the machine reset
   handler.

 hw/intc/spapr_xive.c        | 10 ++++++++++
 hw/ppc/spapr.c              | 10 ++++++++++
 include/hw/ppc/spapr_xive.h |  1 +
 3 files changed, 21 insertions(+)

diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index bf30edc87bee..fcdadf727f9d 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -970,3 +970,13 @@ XiveEQ *spapr_xive_get_eq(sPAPRXive *xive, uint32_t server, uint8_t priority)
     }
     return &nvt->eqt[priority];
 }
+
+void spapr_xive_mmio_map(sPAPRXive *xive)
+{
+    /* ESBs */
+    sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->esb_base);
+
+    /* Thread Management Interrupt Area: User and OS views */
+    sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->tm_base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base + (1 << TM_SHIFT));
+}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2e15ee8a9333..73df038a9e8b 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1537,6 +1537,11 @@ static void ppc_spapr_reset(void)
         ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
     }
 
+    /* Setup XIVE resources if required by CAS */
+    if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
+        spapr_xive_mmio_map(spapr->xive);
+    }
+
     fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
 
     spapr_load_rtas(spapr, fdt, rtas_addr);
@@ -1644,6 +1649,11 @@ static int spapr_post_load(void *opaque, int version_id)
         }
     }
 
+    /* Restore XIVE resources if required by CAS */
+    if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
+        spapr_xive_mmio_map(spapr->xive);
+    }
+
     return err;
 }
 
diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
index 8c3b9cb194a9..5d0c178a4984 100644
--- a/include/hw/ppc/spapr_xive.h
+++ b/include/hw/ppc/spapr_xive.h
@@ -59,6 +59,7 @@ bool spapr_xive_irq_enable(sPAPRXive *xive, uint32_t lisn, bool lsi);
 bool spapr_xive_irq_disable(sPAPRXive *xive, uint32_t lisn);
 void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon);
 void spapr_xive_nvt_pic_print_info(sPAPRXiveNVT *nvt, Monitor *mon);
+void spapr_xive_mmio_map(sPAPRXive *xive);
 
 typedef struct sPAPRMachineState sPAPRMachineState;
 
-- 
2.13.6