From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Alistair Francis <alistair.francis@xilinx.com>,
"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
Peter Maydell <peter.maydell@linaro.org>,
Michael Walle <michael@walle.cc>,
Andrzej Zaborowski <balrogg@gmail.com>,
Andrew Baumann <Andrew.Baumann@microsoft.com>,
Andrey Smirnov <andrew.smirnov@gmail.com>,
Andrey Yurovsky <yurovsky@gmail.com>
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Prasad J Pandit" <pjp@fedoraproject.org>,
"Peter Crosthwaite" <crosthwaite.peter@gmail.com>,
"Sai Pavan Boddu" <saipava@xilinx.com>
Subject: [Qemu-devel] [PATCH v2 11/20] sdhci: add a "dma-memory" property
Date: Fri, 15 Dec 2017 00:15:38 -0300 [thread overview]
Message-ID: <20171215031547.31006-12-f4bug@amsat.org> (raw)
In-Reply-To: <20171215031547.31006-1-f4bug@amsat.org>
Add a dma property allowing machine creation to provide the address-space
sdhci dma operates on.
[based on a patch from Alistair Francis <alistair.francis@xilinx.com>
from qemu/xilinx tag xilinx-v2016.1]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
include/hw/sd/sdhci.h | 2 ++
hw/sd/sdhci.c | 36 +++++++++++++++++++++++-------------
2 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 5391430c59..715048d77b 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -41,6 +41,8 @@ typedef struct SDHCIState {
/*< public >*/
SDBus sdbus;
MemoryRegion iomem;
+ MemoryRegion *dma_mr;
+ AddressSpace dma_as;
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
QEMUTimer *transfer_timer;
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 866be44db5..0f3ff657cf 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -505,7 +505,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
s->blkcnt--;
}
}
- dma_memory_write(&address_space_memory, s->sdmasysad,
+ dma_memory_write(&s->dma_as, s->sdmasysad,
&s->fifo_buffer[begin], s->data_count - begin);
s->sdmasysad += s->data_count - begin;
if (s->data_count == block_size) {
@@ -527,7 +527,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
s->data_count = block_size;
boundary_count -= block_size - begin;
}
- dma_memory_read(&address_space_memory, s->sdmasysad,
+ dma_memory_read(&s->dma_as, s->sdmasysad,
&s->fifo_buffer[begin], s->data_count - begin);
s->sdmasysad += s->data_count - begin;
if (s->data_count == block_size) {
@@ -565,11 +565,9 @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s)
for (n = 0; n < datacnt; n++) {
s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
}
- dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer,
- datacnt);
+ dma_memory_write(&s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
} else {
- dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer,
- datacnt);
+ dma_memory_read(&s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
for (n = 0; n < datacnt; n++) {
sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
}
@@ -593,7 +591,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
hwaddr entry_addr = (hwaddr)s->admasysaddr;
switch (SDHC_DMA_TYPE(s->hostctl)) {
case SDHC_CTRL_ADMA2_32:
- dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2,
+ dma_memory_read(&s->dma_as, entry_addr, (uint8_t *)&adma2,
sizeof(adma2));
adma2 = le64_to_cpu(adma2);
/* The spec does not specify endianness of descriptor table.
@@ -605,7 +603,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
dscr->incr = 8;
break;
case SDHC_CTRL_ADMA1_32:
- dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1,
+ dma_memory_read(&s->dma_as, entry_addr, (uint8_t *)&adma1,
sizeof(adma1));
adma1 = le32_to_cpu(adma1);
dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
@@ -618,12 +616,12 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
}
break;
case SDHC_CTRL_ADMA2_64:
- dma_memory_read(&address_space_memory, entry_addr,
+ dma_memory_read(&s->dma_as, entry_addr,
(uint8_t *)(&dscr->attr), 1);
- dma_memory_read(&address_space_memory, entry_addr + 2,
+ dma_memory_read(&s->dma_as, entry_addr + 2,
(uint8_t *)(&dscr->length), 2);
dscr->length = le16_to_cpu(dscr->length);
- dma_memory_read(&address_space_memory, entry_addr + 4,
+ dma_memory_read(&s->dma_as, entry_addr + 4,
(uint8_t *)(&dscr->addr), 8);
dscr->attr = le64_to_cpu(dscr->attr);
dscr->attr &= 0xfffffff8;
@@ -682,7 +680,7 @@ static void sdhci_do_adma(SDHCIState *s)
s->data_count = block_size;
length -= block_size - begin;
}
- dma_memory_write(&address_space_memory, dscr.addr,
+ dma_memory_write(&s->dma_as, dscr.addr,
&s->fifo_buffer[begin],
s->data_count - begin);
dscr.addr += s->data_count - begin;
@@ -706,7 +704,7 @@ static void sdhci_do_adma(SDHCIState *s)
s->data_count = block_size;
length -= block_size - begin;
}
- dma_memory_read(&address_space_memory, dscr.addr,
+ dma_memory_read(&s->dma_as, dscr.addr,
&s->fifo_buffer[begin],
s->data_count - begin);
dscr.addr += s->data_count - begin;
@@ -1183,10 +1181,20 @@ static void sdhci_realizefn(SDHCIState *s, Error **errp)
memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
SDHC_REGISTERS_MAP_SIZE);
+
+ /* use system_memory() if property "dma-memory" not set */
+ address_space_init(&s->dma_as,
+ s->dma_mr ? s->dma_mr : get_system_memory(),
+ "sdhci-dma");
}
static void sdhci_unrealizefn(SDHCIState *s, Error **errp)
{
+ if (s->dma_mr) {
+ address_space_destroy(&s->dma_as);
+ object_unparent(OBJECT(&s->dma_mr));
+ }
+
g_free(s->fifo_buffer);
}
@@ -1269,6 +1277,8 @@ static Property sdhci_properties[] = {
DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
false),
+ DEFINE_PROP_LINK("dma-memory", SDHCIState, dma_mr,
+ TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
--
2.15.1
next prev parent reply other threads:[~2017-12-15 3:16 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-15 3:15 [Qemu-devel] [PATCH v2 00/20] SDHCI: housekeeping, add a qtest and fix few issues Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 01/20] sdhci: clean up includes Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 02/20] sdhci: use deposit64() Philippe Mathieu-Daudé
2017-12-19 1:16 ` Alistair Francis
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 03/20] sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h" Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 04/20] sdhci: refactor same sysbus/pci properties into a common one Philippe Mathieu-Daudé
2017-12-19 1:13 ` Alistair Francis
2017-12-29 17:21 ` Philippe Mathieu-Daudé
2018-01-03 19:36 ` Alistair Francis
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 05/20] sdhci: refactor common sysbus/pci realize() into sdhci_realizefn() Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 06/20] sdhci: refactor common sysbus/pci class_init() into sdhci_class_init() Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 07/20] sdhci: refactor common sysbus/pci unrealize() into sdhci_unrealizefn() Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 08/20] sdhci: use qemu_log_mask(UNIMP) instead of fprintf() Philippe Mathieu-Daudé
2017-12-19 1:16 ` Alistair Francis
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 09/20] sdhci: convert the DPRINT() calls into trace events Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 10/20] sdhci: add a GPIO for the access control LED Philippe Mathieu-Daudé
2017-12-15 3:15 ` Philippe Mathieu-Daudé [this message]
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 12/20] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 13/20] sdhci: Implement write method of ACMD12ERRSTS register Philippe Mathieu-Daudé
2017-12-19 1:18 ` Alistair Francis
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 14/20] sdhci: add a "sd-spec-version" property Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 15/20] sdhci: some ARM boards do support SD_HOST_SPECv3_VERS Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 16/20] sdhci: add qtest to check the SD Spec version Philippe Mathieu-Daudé
2017-12-18 15:27 ` Stefan Hajnoczi
2017-12-18 23:10 ` Philippe Mathieu-Daudé
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 17/20] sdhci: add check_capab_readonly() qtest Philippe Mathieu-Daudé
2017-12-18 17:00 ` Stefan Hajnoczi
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 18/20] sdhci: add a check_capab_baseclock() qtest Philippe Mathieu-Daudé
2017-12-18 17:00 ` Stefan Hajnoczi
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 19/20] sdhci: add a check_capab_sdma() qtest Philippe Mathieu-Daudé
2017-12-18 17:01 ` Stefan Hajnoczi
2017-12-15 3:15 ` [Qemu-devel] [PATCH v2 20/20] sdhci: add a check_capab_v3() qtest Philippe Mathieu-Daudé
2017-12-18 17:01 ` Stefan Hajnoczi
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