From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v2 06/11] target/arm: Decode aa32 armv8.1 two reg and a scalar
Date: Mon, 18 Dec 2017 09:24:20 -0800 [thread overview]
Message-ID: <20171218172425.18200-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20171218172425.18200-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 38 +++++++++++++++++++++++++++++++++++---
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a9587ae242..1a0b0eaced 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6973,11 +6973,43 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
neon_store_reg64(cpu_V0, rd + pass);
}
+ break;
+ case 14: /* VQRDMLAH scalar */
+ case 15: /* VQRDMLSH scalar */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) {
+ return 1;
+ }
+ if (u && ((rd | rn) & 1)) {
+ return 1;
+ }
+ tmp2 = neon_get_scalar(size, rm);
+ for (pass = 0; pass < (u ? 4 : 2); pass++) {
+ void (*fn)(TCGv_i32, TCGv_env, TCGv_i32,
+ TCGv_i32, TCGv_i32);
-
+ tmp = neon_load_reg(rn, pass);
+ tmp3 = neon_load_reg(rd, pass);
+ if (op == 14) {
+ if (size == 1) {
+ fn = gen_helper_neon_qrdmlah_s16;
+ } else {
+ fn = gen_helper_neon_qrdmlah_s32;
+ }
+ } else {
+ if (size == 1) {
+ fn = gen_helper_neon_qrdmlsh_s16;
+ } else {
+ fn = gen_helper_neon_qrdmlsh_s32;
+ }
+ }
+ fn(tmp, cpu_env, tmp, tmp2, tmp3);
+ tcg_temp_free_i32(tmp3);
+ neon_store_reg(rd, pass, tmp);
+ }
+ tcg_temp_free_i32(tmp2);
break;
- default: /* 14 and 15 are RESERVED */
- return 1;
+ default:
+ g_assert_not_reached();
}
}
} else { /* size == 3 */
--
2.14.3
next prev parent reply other threads:[~2017-12-18 17:24 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-18 17:24 [Qemu-devel] [PATCH v2 00/11] ARM v8.1 simd + v8.3 complex insns Richard Henderson
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 01/11] target/arm: Add ARM_FEATURE_V8_1_SIMD Richard Henderson
2018-01-15 17:21 ` Peter Maydell
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 02/11] target/arm: Decode aa64 armv8.1 scalar three same extra Richard Henderson
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 03/11] target/arm: Decode aa64 armv8.1 " Richard Henderson
2018-01-15 17:21 ` Peter Maydell
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 04/11] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element Richard Henderson
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 05/11] target/arm: Decode aa32 armv8.1 three same Richard Henderson
2018-01-15 17:37 ` Peter Maydell
2017-12-18 17:24 ` Richard Henderson [this message]
2018-01-15 17:47 ` [Qemu-devel] [PATCH v2 06/11] target/arm: Decode aa32 armv8.1 two reg and a scalar Peter Maydell
2018-01-26 7:18 ` Richard Henderson
2018-01-26 10:05 ` Peter Maydell
2018-01-26 13:41 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 07/11] target/arm: Add ARM_FEATURE_V8_FCMA Richard Henderson
2018-01-15 17:53 ` Peter Maydell
2018-01-15 18:03 ` Richard Henderson
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 08/11] target/arm: Decode aa64 armv8.3 fcadd Richard Henderson
2018-01-15 18:11 ` Peter Maydell
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 09/11] target/arm: Decode aa64 armv8.3 fcmla Richard Henderson
2018-01-15 18:18 ` Peter Maydell
2018-01-26 7:29 ` Richard Henderson
2018-01-26 10:07 ` Peter Maydell
2018-01-26 19:03 ` Richard Henderson
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 10/11] target/arm: Decode aa32 armv8.3 3-same Richard Henderson
2018-01-15 18:46 ` Peter Maydell
2018-01-15 19:10 ` Richard Henderson
2018-01-15 18:49 ` Peter Maydell
2017-12-18 17:24 ` [Qemu-devel] [PATCH v2 11/11] target/arm: Decode aa32 armv8.3 2-reg-index Richard Henderson
2018-01-15 18:51 ` Peter Maydell
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