* [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219
@ 2017-12-19 4:29 David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 01/14] target-ppc: optimize cmp translation David Gibson
` (14 more replies)
0 siblings, 15 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-ppc, qemu-devel, mdroth, David Gibson
The following changes since commit eaefea537b476cb853e2edbdc68e969ec777e4bb:
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging (2017-12-18 14:17:42 +0000)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20171219
for you to fetch changes up to eec745d4366076dee068750ea80245e1a46e9c13:
hw/ide: Emulate SiI3112 SATA controller (2017-12-19 15:24:28 +1100)
----------------------------------------------------------------
ppc patch queue 2017-12-19
Here's a second batch of patches for qemu-2.12. Highlights are:
* Optional capabilities for the "pseries" machine. This removes
some places where we were changing guest visible properties based
on host capabilities, which makes life very bad for migration.
* SLOF update
* Significant TCG speedup from Paolo
* Several new devices for embedded platforms
* Some minor cleanups
----------------------------------------------------------------
Alexey Kardashevskiy (1):
pseries: Update SLOF firmware image to qemu-slof-20171214
BALATON Zoltan (4):
sm501: Add panel hardware cursor registers also to read function
sm501: Add some more unimplemented registers
ppc4xx_i2c: Implement basic I2C functions
hw/ide: Emulate SiI3112 SATA controller
Cédric Le Goater (1):
ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency
David Gibson (6):
spapr: Capabilities infrastructure
spapr: Treat Hardware Transactional Memory (HTM) as an optional capability
spapr: Validate capabilities on migration
target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM
spapr: Handle VMX/VSX presence as an spapr capability flag
spapr: Handle Decimal Floating Point (DFP) as an optional capability
Greg Kurz (1):
spapr_pci: use warn_report()
pbonzini@redhat.com (1):
target-ppc: optimize cmp translation
MAINTAINERS | 6 +
default-configs/ppcemb-softmmu.mak | 1 +
hw/display/sm501.c | 30 +++
hw/i2c/ppc4xx_i2c.c | 198 +++++++++++++++++---
hw/ide/Makefile.objs | 1 +
hw/ide/sii3112.c | 368 +++++++++++++++++++++++++++++++++++++
hw/ide/trace-events | 5 +
hw/ppc/Makefile.objs | 2 +-
hw/ppc/pnv.c | 94 +++++-----
hw/ppc/pnv_bmc.c | 2 +-
hw/ppc/pnv_core.c | 8 +-
hw/ppc/pnv_lpc.c | 6 +-
hw/ppc/pnv_psi.c | 4 +-
hw/ppc/pnv_xscom.c | 10 +-
hw/ppc/spapr.c | 47 +++--
hw/ppc/spapr_caps.c | 341 ++++++++++++++++++++++++++++++++++
hw/ppc/spapr_pci.c | 6 +-
hw/ppc/spapr_pci_vfio.c | 2 +-
include/hw/i2c/ppc4xx_i2c.h | 3 +
include/hw/ppc/pnv.h | 10 +-
include/hw/ppc/pnv_xscom.h | 4 +-
include/hw/ppc/spapr.h | 46 +++++
pc-bios/README | 2 +-
pc-bios/slof.bin | Bin 905200 -> 913880 bytes
roms/SLOF | 2 +-
target/ppc/kvm.c | 27 +--
target/ppc/kvm_ppc.h | 2 -
target/ppc/translate.c | 29 ++-
28 files changed, 1095 insertions(+), 161 deletions(-)
create mode 100644 hw/ide/sii3112.c
create mode 100644 hw/ppc/spapr_caps.c
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 01/14] target-ppc: optimize cmp translation
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 02/14] pseries: Update SLOF firmware image to qemu-slof-20171214 David Gibson
` (13 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell
Cc: groug, qemu-ppc, qemu-devel, mdroth, pbonzini@redhat.com,
David Gibson
From: "pbonzini@redhat.com" <pbonzini@redhat.com>
We know that only one bit (in addition to SO) is going to be set in
the condition register, so do two movconds instead of three setconds,
three shifts and two ORs.
For ppc64-linux-user, the code size reduction is around 5% and the
performance improvement slightly less than 10%. For softmmu, the
improvement is around 5%.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4075fc8589..8a6bd329d0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -605,27 +605,22 @@ static opc_handler_t invalid_handler = {
static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
{
TCGv t0 = tcg_temp_new();
- TCGv_i32 t1 = tcg_temp_new_i32();
-
- tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
-
- tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ TCGv t1 = tcg_temp_new();
+ TCGv_i32 t = tcg_temp_new_i32();
- tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ tcg_gen_movi_tl(t0, CRF_EQ);
+ tcg_gen_movi_tl(t1, CRF_LT);
+ tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0);
+ tcg_gen_movi_tl(t1, CRF_GT);
+ tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0);
- tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ tcg_gen_trunc_tl_i32(t, t0);
+ tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
+ tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
tcg_temp_free(t0);
- tcg_temp_free_i32(t1);
+ tcg_temp_free(t1);
+ tcg_temp_free_i32(t);
}
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 02/14] pseries: Update SLOF firmware image to qemu-slof-20171214
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 01/14] target-ppc: optimize cmp translation David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 03/14] sm501: Add panel hardware cursor registers also to read function David Gibson
` (12 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell
Cc: groug, qemu-ppc, qemu-devel, mdroth, Alexey Kardashevskiy,
David Gibson
From: Alexey Kardashevskiy <aik@ozlabs.ru>
The main changes are:
- able to handle more devices with specified bootindex;
- implements flatten device tree rendering, for both QEMU and guest kernel.
The full list is:
> boot: use a temporary bootdev-buf
> boot: do not concatenate bootdev
> libvirtio: Mark struct virtio_scsi_req_cmd as packed
> fdt: Implement "fdt-fetch" method for client interface
> rtas: Store RTAS address and entry in the device tree
> board-qemu: Fix slof-build-id length
> fdt: Pass the resulting device tree to QEMU
> fdt: Fix version and add a word for FDT header size
> tree: Rework set-chosen-cpu and store /chosen ihandle and phandle
> node: Add some documentation
> Revert various SLOF-to-QEMU private hypercalls
> Use input-device and output-device
> netboot: Create bootp-response when bootp is used
> libnet/ipv6: assign times_asked value directly
> usb-xhci: Reset ERSTSZ together with ERSTBA
> virtio-net: rework the driver to support multiple open
> board-qemu: add private hcall to inform host on "phandle" update
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
pc-bios/README | 2 +-
pc-bios/slof.bin | Bin 905200 -> 913880 bytes
roms/SLOF | 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/pc-bios/README b/pc-bios/README
index 25fc6ce63f..a843e1e8b1 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -17,7 +17,7 @@
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
https://github.com/aik/SLOF, and the image currently in qemu is
- built from git tag qemu-slof-20170724.
+ built from git tag qemu-slof-20171214.
- sgabios (the Serial Graphics Adapter option ROM) provides a means for
legacy x86 software to communicate with an attached serial console as
diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin
index 6bb48d40a0929bc9d1e2846a97a91f96d321d60c..d46c83efb706e4664fec834234ba69d96ede3473 100644
GIT binary patch
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CkeoFD
diff --git a/roms/SLOF b/roms/SLOF
index 89f519f09b..fa981320a1 160000
--- a/roms/SLOF
+++ b/roms/SLOF
@@ -1 +1 @@
-Subproject commit 89f519f09bf850918b60526e50409afb663418aa
+Subproject commit fa981320a1e0968d6fc1b8de319723ff8212b337
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 03/14] sm501: Add panel hardware cursor registers also to read function
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 01/14] target-ppc: optimize cmp translation David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 02/14] pseries: Update SLOF firmware image to qemu-slof-20171214 David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 04/14] sm501: Add some more unimplemented registers David Gibson
` (11 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell
Cc: groug, qemu-ppc, qemu-devel, mdroth, BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
These were forgotten when adding panel layer support in ffd39257018
"SM501 emulation for R2D-SH4".
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[dwg: Added reference to earlier commit in message]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/display/sm501.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 7f1822421a..b9b611131e 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -956,6 +956,19 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
ret = s->dc_panel_v_sync;
break;
+ case SM501_DC_PANEL_HWC_ADDR:
+ ret = s->dc_panel_hwc_addr;
+ break;
+ case SM501_DC_PANEL_HWC_LOC:
+ ret = s->dc_panel_hwc_location;
+ break;
+ case SM501_DC_PANEL_HWC_COLOR_1_2:
+ ret = s->dc_panel_hwc_color_1_2;
+ break;
+ case SM501_DC_PANEL_HWC_COLOR_3:
+ ret = s->dc_panel_hwc_color_3;
+ break;
+
case SM501_DC_VIDEO_CONTROL:
ret = s->dc_video_control;
break;
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 04/14] sm501: Add some more unimplemented registers
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (2 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 03/14] sm501: Add panel hardware cursor registers also to read function David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 05/14] ppc4xx_i2c: Implement basic I2C functions David Gibson
` (10 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell
Cc: groug, qemu-ppc, qemu-devel, mdroth, BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
These are not really implemented (just return zero or default values)
but add these so guests accessing them can run.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/display/sm501.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index b9b611131e..4f7dc59b25 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -795,6 +795,8 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
case SM501_ARBTRTN_CONTROL:
ret = s->arbitration_control;
break;
+ case SM501_COMMAND_LIST_STATUS:
+ ret = 0x00180002; /* FIFOs are empty, everything idle */
case SM501_IRQ_MASK:
ret = s->irq_mask;
break;
@@ -812,6 +814,9 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
case SM501_POWER_MODE_CONTROL:
ret = s->power_mode_control;
break;
+ case SM501_ENDIAN_CONTROL:
+ ret = 0; /* Only default little endian mode is supported */
+ break;
default:
printf("sm501 system config : not implemented register read."
@@ -865,6 +870,12 @@ static void sm501_system_config_write(void *opaque, hwaddr addr,
case SM501_POWER_MODE_CONTROL:
s->power_mode_control = value & 0x00000003;
break;
+ case SM501_ENDIAN_CONTROL:
+ if (value & 0x00000001) {
+ printf("sm501 system config : big endian mode not implemented.\n");
+ abort();
+ }
+ break;
default:
printf("sm501 system config : not implemented register write."
@@ -924,6 +935,9 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
case SM501_DC_PANEL_PANNING_CONTROL:
ret = s->dc_panel_panning_control;
break;
+ case SM501_DC_PANEL_COLOR_KEY:
+ /* Not implemented yet */
+ break;
case SM501_DC_PANEL_FB_ADDR:
ret = s->dc_panel_fb_addr;
break;
@@ -1035,6 +1049,9 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
case SM501_DC_PANEL_PANNING_CONTROL:
s->dc_panel_panning_control = value & 0xFF3FFF3F;
break;
+ case SM501_DC_PANEL_COLOR_KEY:
+ /* Not implemented yet */
+ break;
case SM501_DC_PANEL_FB_ADDR:
s->dc_panel_fb_addr = value & 0x8FFFFFF0;
break;
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 05/14] ppc4xx_i2c: Implement basic I2C functions
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (3 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 04/14] sm501: Add some more unimplemented registers David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 06/14] ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency David Gibson
` (9 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell
Cc: groug, qemu-ppc, qemu-devel, mdroth, BALATON Zoltan,
François Revol, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
Enough to please U-Boot and make it able to detect SDRAM SPD EEPROMs
Signed-off-by: François Revol <revol@free.fr>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/i2c/ppc4xx_i2c.c | 198 +++++++++++++++++++++++++++++++++++++-------
include/hw/i2c/ppc4xx_i2c.h | 3 +
2 files changed, 171 insertions(+), 30 deletions(-)
diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c
index 5a6bde951e..e873a445da 100644
--- a/hw/i2c/ppc4xx_i2c.c
+++ b/hw/i2c/ppc4xx_i2c.c
@@ -2,6 +2,8 @@
* PPC4xx I2C controller emulation
*
* Copyright (c) 2007 Jocelyn Mayer
+ * Copyright (c) 2012 François Revol
+ * Copyright (c) 2016 BALATON Zoltan
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -25,26 +27,118 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
+#include "qemu/log.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/i2c/ppc4xx_i2c.h"
-/*#define DEBUG_I2C*/
+#define PPC4xx_I2C_MEM_SIZE 0x12
-#define PPC4xx_I2C_MEM_SIZE 0x11
+#define IIC_CNTL_PT (1 << 0)
+#define IIC_CNTL_READ (1 << 1)
+#define IIC_CNTL_CHT (1 << 2)
+#define IIC_CNTL_RPST (1 << 3)
+
+#define IIC_STS_PT (1 << 0)
+#define IIC_STS_ERR (1 << 2)
+#define IIC_STS_MDBS (1 << 5)
+
+#define IIC_EXTSTS_XFRA (1 << 0)
+
+#define IIC_XTCNTLSS_SRST (1 << 0)
+
+static void ppc4xx_i2c_reset(DeviceState *s)
+{
+ PPC4xxI2CState *i2c = PPC4xx_I2C(s);
+
+ /* FIXME: Should also reset bus?
+ *if (s->address != ADDR_RESET) {
+ * i2c_end_transfer(s->bus);
+ *}
+ */
+
+ i2c->mdata = 0;
+ i2c->lmadr = 0;
+ i2c->hmadr = 0;
+ i2c->cntl = 0;
+ i2c->mdcntl = 0;
+ i2c->sts = 0;
+ i2c->extsts = 0x8f;
+ i2c->sdata = 0;
+ i2c->lsadr = 0;
+ i2c->hsadr = 0;
+ i2c->clkdiv = 0;
+ i2c->intrmsk = 0;
+ i2c->xfrcnt = 0;
+ i2c->xtcntlss = 0;
+ i2c->directcntl = 0x0f;
+ i2c->intr = 0;
+}
+
+static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c)
+{
+ return true;
+}
static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
{
PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);
uint64_t ret;
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
switch (addr) {
case 0x00:
- /*i2c_readbyte(&i2c->mdata);*/
ret = i2c->mdata;
+ if (ppc4xx_i2c_is_master(i2c)) {
+ ret = 0xff;
+
+ if (!(i2c->sts & IIC_STS_MDBS)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
+ "without starting transfer\n",
+ TYPE_PPC4xx_I2C, __func__);
+ } else {
+ int pending = (i2c->cntl >> 4) & 3;
+
+ /* get the next byte */
+ int byte = i2c_recv(i2c->bus);
+
+ if (byte < 0) {
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "
+ "for device 0x%02x\n", TYPE_PPC4xx_I2C,
+ __func__, i2c->lmadr);
+ ret = 0xff;
+ } else {
+ ret = byte;
+ /* Raise interrupt if enabled */
+ /*ppc4xx_i2c_raise_interrupt(i2c)*/;
+ }
+
+ if (!pending) {
+ i2c->sts &= ~IIC_STS_MDBS;
+ /*i2c_end_transfer(i2c->bus);*/
+ /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/
+ } else if (pending) {
+ /* current smbus implementation doesn't like
+ multibyte xfer repeated start */
+ i2c_end_transfer(i2c->bus);
+ if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {
+ /* if non zero is returned, the adress is not valid */
+ i2c->sts &= ~IIC_STS_PT;
+ i2c->sts |= IIC_STS_ERR;
+ i2c->extsts |= IIC_EXTSTS_XFRA;
+ } else {
+ /*i2c->sts |= IIC_STS_PT;*/
+ i2c->sts |= IIC_STS_MDBS;
+ i2c->sts &= ~IIC_STS_ERR;
+ i2c->extsts = 0;
+ }
+ }
+ pending--;
+ i2c->cntl = (i2c->cntl & 0xcf) | (pending << 4);
+ }
+ } else {
+ qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
+ TYPE_PPC4xx_I2C, __func__);
+ }
break;
case 0x02:
ret = i2c->sdata;
@@ -88,13 +182,15 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
case 0x10:
ret = i2c->directcntl;
break;
+ case 0x11:
+ ret = i2c->intr;
+ break;
default:
- ret = 0x00;
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr);
+ ret = 0;
break;
}
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " %02" PRIx64 "\n", __func__, addr, ret);
-#endif
return ret;
}
@@ -103,26 +199,70 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned int size)
{
PPC4xxI2CState *i2c = opaque;
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n",
- __func__, addr, value);
-#endif
+
switch (addr) {
case 0x00:
i2c->mdata = value;
- /*i2c_sendbyte(&i2c->mdata);*/
+ if (!i2c_bus_busy(i2c->bus)) {
+ /* assume we start a write transfer */
+ if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) {
+ /* if non zero is returned, the adress is not valid */
+ i2c->sts &= ~IIC_STS_PT;
+ i2c->sts |= IIC_STS_ERR;
+ i2c->extsts |= IIC_EXTSTS_XFRA;
+ } else {
+ i2c->sts |= IIC_STS_PT;
+ i2c->sts &= ~IIC_STS_ERR;
+ i2c->extsts = 0;
+ }
+ }
+ if (i2c_bus_busy(i2c->bus)) {
+ if (i2c_send(i2c->bus, i2c->mdata)) {
+ /* if the target return non zero then end the transfer */
+ i2c->sts &= ~IIC_STS_PT;
+ i2c->sts |= IIC_STS_ERR;
+ i2c->extsts |= IIC_EXTSTS_XFRA;
+ i2c_end_transfer(i2c->bus);
+ }
+ }
break;
case 0x02:
i2c->sdata = value;
break;
case 0x04:
i2c->lmadr = value;
+ if (i2c_bus_busy(i2c->bus)) {
+ i2c_end_transfer(i2c->bus);
+ }
break;
case 0x05:
i2c->hmadr = value;
break;
case 0x06:
i2c->cntl = value;
+ if (i2c->cntl & IIC_CNTL_PT) {
+ if (i2c->cntl & IIC_CNTL_READ) {
+ if (i2c_bus_busy(i2c->bus)) {
+ /* end previous transfer */
+ i2c->sts &= ~IIC_STS_PT;
+ i2c_end_transfer(i2c->bus);
+ }
+ if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {
+ /* if non zero is returned, the adress is not valid */
+ i2c->sts &= ~IIC_STS_PT;
+ i2c->sts |= IIC_STS_ERR;
+ i2c->extsts |= IIC_EXTSTS_XFRA;
+ } else {
+ /*i2c->sts |= IIC_STS_PT;*/
+ i2c->sts |= IIC_STS_MDBS;
+ i2c->sts &= ~IIC_STS_ERR;
+ i2c->extsts = 0;
+ }
+ } else {
+ /* we actually already did the write transfer... */
+ i2c->sts &= ~IIC_STS_PT;
+ }
+ }
break;
case 0x07:
i2c->mdcntl = value & 0xDF;
@@ -135,6 +275,7 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
break;
case 0x0A:
i2c->lsadr = value;
+ /*i2c_set_slave_address(i2c->bus, i2c->lsadr);*/
break;
case 0x0B:
i2c->hsadr = value;
@@ -149,11 +290,23 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
i2c->xfrcnt = value & 0x77;
break;
case 0x0F:
+ if (value & IIC_XTCNTLSS_SRST) {
+ /* Is it actually a full reset? U-Boot sets some regs before */
+ ppc4xx_i2c_reset(DEVICE(i2c));
+ break;
+ }
i2c->xtcntlss = value;
break;
case 0x10:
i2c->directcntl = value & 0x7;
break;
+ case 0x11:
+ i2c->intr = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr);
+ break;
}
}
@@ -167,21 +320,6 @@ static const MemoryRegionOps ppc4xx_i2c_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ppc4xx_i2c_reset(DeviceState *s)
-{
- PPC4xxI2CState *i2c = PPC4xx_I2C(s);
-
- i2c->mdata = 0x00;
- i2c->sdata = 0x00;
- i2c->cntl = 0x00;
- i2c->mdcntl = 0x00;
- i2c->sts = 0x00;
- i2c->extsts = 0x00;
- i2c->clkdiv = 0x00;
- i2c->xfrcnt = 0x00;
- i2c->directcntl = 0x0F;
-}
-
static void ppc4xx_i2c_init(Object *o)
{
PPC4xxI2CState *s = PPC4xx_I2C(o);
diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h
index 3450bda577..3c603071bd 100644
--- a/include/hw/i2c/ppc4xx_i2c.h
+++ b/include/hw/i2c/ppc4xx_i2c.h
@@ -2,6 +2,8 @@
* PPC4xx I2C controller emulation
*
* Copyright (c) 2007 Jocelyn Mayer
+ * Copyright (c) 2012 François Revol
+ * Copyright (c) 2016 BALATON Zoltan
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -55,6 +57,7 @@ typedef struct PPC4xxI2CState {
uint8_t xfrcnt;
uint8_t xtcntlss;
uint8_t directcntl;
+ uint8_t intr;
} PPC4xxI2CState;
#endif /* PPC4XX_I2C_H */
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 06/14] ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (4 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 05/14] ppc4xx_i2c: Implement basic I2C functions David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 07/14] spapr: Capabilities infrastructure David Gibson
` (8 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell
Cc: groug, qemu-ppc, qemu-devel, mdroth, Cédric Le Goater,
David Gibson
From: Cédric Le Goater <clg@kaod.org>
The 'pnv' prefix is now used for all and the routines populating the
device tree start with 'pnv_dt'. The handler of the PnvXScomInterface
is also renamed to 'dt_xscom' which should reflect that it is
populating the device tree under the 'xscom@' node of the chip.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 94 ++++++++++++++++++++++------------------------
hw/ppc/pnv_bmc.c | 2 +-
hw/ppc/pnv_core.c | 8 ++--
hw/ppc/pnv_lpc.c | 6 +--
hw/ppc/pnv_psi.c | 4 +-
hw/ppc/pnv_xscom.c | 10 ++---
include/hw/ppc/pnv.h | 10 ++---
include/hw/ppc/pnv_xscom.h | 4 +-
8 files changed, 67 insertions(+), 71 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 94ffc8e137..9475e8479c 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -77,8 +77,7 @@ static const char *pnv_chip_core_typename(const PnvChip *o)
* that has a different "affinity". In practice, it means one range
* per chip.
*/
-static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
- hwaddr size)
+static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
{
char *mem_name;
uint64_t mem_reg_property[2];
@@ -119,7 +118,7 @@ static int get_cpus_node(void *fdt)
* device tree, used in XSCOM to address cores and in interrupt
* servers.
*/
-static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
+static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
{
CPUState *cs = CPU(DEVICE(pc->threads));
DeviceClass *dc = DEVICE_GET_CLASS(cs);
@@ -228,8 +227,8 @@ static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
servers_prop, sizeof(servers_prop))));
}
-static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir,
- uint32_t nr_threads)
+static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
+ uint32_t nr_threads)
{
uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
char *name;
@@ -277,13 +276,13 @@ static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt)
return offset;
}
-static void powernv_populate_chip(PnvChip *chip, void *fdt)
+static void pnv_dt_chip(PnvChip *chip, void *fdt)
{
const char *typename = pnv_chip_core_typename(chip);
size_t typesize = object_type_get_instance_size(typename);
int i;
- pnv_xscom_populate(chip, fdt, 0);
+ pnv_dt_xscom(chip, fdt, 0);
/* The default LPC bus of a multichip system is on chip 0. It's
* recognized by the firmware (skiboot) using a "primary"
@@ -298,20 +297,18 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
- powernv_create_core_node(chip, pnv_core, fdt);
+ pnv_dt_core(chip, pnv_core, fdt);
/* Interrupt Control Presenters (ICP). One per core. */
- powernv_populate_icp(chip, fdt, pnv_core->pir,
- CPU_CORE(pnv_core)->nr_threads);
+ pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
}
if (chip->ram_size) {
- powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
- chip->ram_size);
+ pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
}
}
-static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
+static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
{
uint32_t io_base = d->ioport_id;
uint32_t io_regs[] = {
@@ -331,7 +328,7 @@ static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
_FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
}
-static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
+static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
{
const char compatible[] = "ns16550\0pnpPNP,501";
uint32_t io_base = d->ioport_id;
@@ -362,7 +359,7 @@ static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
_FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
}
-static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
+static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
{
const char compatible[] = "bt\0ipmi-bt";
uint32_t io_base;
@@ -401,17 +398,17 @@ typedef struct ForeachPopulateArgs {
int offset;
} ForeachPopulateArgs;
-static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
+static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
{
ForeachPopulateArgs *args = opaque;
ISADevice *d = ISA_DEVICE(dev);
if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
- powernv_populate_rtc(d, args->fdt, args->offset);
+ pnv_dt_rtc(d, args->fdt, args->offset);
} else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
- powernv_populate_serial(d, args->fdt, args->offset);
+ pnv_dt_serial(d, args->fdt, args->offset);
} else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
- powernv_populate_ipmi_bt(d, args->fdt, args->offset);
+ pnv_dt_ipmi_bt(d, args->fdt, args->offset);
} else {
error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
d->ioport_id);
@@ -420,7 +417,7 @@ static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
return 0;
}
-static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset)
+static void pnv_dt_isa(ISABus *bus, void *fdt, int lpc_offset)
{
ForeachPopulateArgs args = {
.fdt = fdt,
@@ -429,14 +426,13 @@ static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset)
/* ISA devices are not necessarily parented to the ISA bus so we
* can not use object_child_foreach() */
- qbus_walk_children(BUS(bus), powernv_populate_isa_device,
- NULL, NULL, NULL, &args);
+ qbus_walk_children(BUS(bus), pnv_dt_isa_device, NULL, NULL, NULL, &args);
}
-static void *powernv_create_fdt(MachineState *machine)
+static void *pnv_dt_create(MachineState *machine)
{
const char plat_compat[] = "qemu,powernv\0ibm,powernv";
- PnvMachineState *pnv = POWERNV_MACHINE(machine);
+ PnvMachineState *pnv = PNV_MACHINE(machine);
void *fdt;
char *buf;
int off;
@@ -479,15 +475,15 @@ static void *powernv_create_fdt(MachineState *machine)
/* Populate device tree for each chip */
for (i = 0; i < pnv->num_chips; i++) {
- powernv_populate_chip(pnv->chips[i], fdt);
+ pnv_dt_chip(pnv->chips[i], fdt);
}
/* Populate ISA devices on chip 0 */
lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt);
- powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset);
+ pnv_dt_isa(pnv->isa_bus, fdt, lpc_offset);
if (pnv->bmc) {
- pnv_bmc_populate_sensors(pnv->bmc, fdt);
+ pnv_dt_bmc_sensors(pnv->bmc, fdt);
}
return fdt;
@@ -495,17 +491,17 @@ static void *powernv_create_fdt(MachineState *machine)
static void pnv_powerdown_notify(Notifier *n, void *opaque)
{
- PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine());
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
if (pnv->bmc) {
pnv_bmc_powerdown(pnv->bmc);
}
}
-static void ppc_powernv_reset(void)
+static void pnv_reset(void)
{
MachineState *machine = MACHINE(qdev_get_machine());
- PnvMachineState *pnv = POWERNV_MACHINE(machine);
+ PnvMachineState *pnv = PNV_MACHINE(machine);
void *fdt;
Object *obj;
@@ -524,7 +520,7 @@ static void ppc_powernv_reset(void)
pnv->bmc = IPMI_BMC(obj);
}
- fdt = powernv_create_fdt(machine);
+ fdt = pnv_dt_create(machine);
/* Pack resulting tree */
_FDT((fdt_pack(fdt)));
@@ -552,9 +548,9 @@ static ISABus *pnv_isa_create(PnvChip *chip)
return isa_bus;
}
-static void ppc_powernv_init(MachineState *machine)
+static void pnv_init(MachineState *machine)
{
- PnvMachineState *pnv = POWERNV_MACHINE(machine);
+ PnvMachineState *pnv = PNV_MACHINE(machine);
MemoryRegion *ram;
char *fw_filename;
long fw_size;
@@ -567,7 +563,7 @@ static void ppc_powernv_init(MachineState *machine)
}
ram = g_new(MemoryRegion, 1);
- memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
+ memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
machine->ram_size);
memory_region_add_subregion(get_system_memory(), 0, ram);
@@ -974,7 +970,7 @@ static void pnv_chip_class_init(ObjectClass *klass, void *data)
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
- PnvMachineState *pnv = POWERNV_MACHINE(xi);
+ PnvMachineState *pnv = PNV_MACHINE(xi);
int i;
for (i = 0; i < pnv->num_chips; i++) {
@@ -987,7 +983,7 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
static void pnv_ics_resend(XICSFabric *xi)
{
- PnvMachineState *pnv = POWERNV_MACHINE(xi);
+ PnvMachineState *pnv = PNV_MACHINE(xi);
int i;
for (i = 0; i < pnv->num_chips; i++) {
@@ -1021,7 +1017,7 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
static void pnv_pic_print_info(InterruptStatsProvider *obj,
Monitor *mon)
{
- PnvMachineState *pnv = POWERNV_MACHINE(obj);
+ PnvMachineState *pnv = PNV_MACHINE(obj);
int i;
CPUState *cs;
@@ -1039,13 +1035,13 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
+ visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
}
static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- PnvMachineState *pnv = POWERNV_MACHINE(obj);
+ PnvMachineState *pnv = PNV_MACHINE(obj);
uint32_t num_chips;
Error *local_err = NULL;
@@ -1067,13 +1063,13 @@ static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
pnv->num_chips = num_chips;
}
-static void powernv_machine_initfn(Object *obj)
+static void pnv_machine_initfn(Object *obj)
{
- PnvMachineState *pnv = POWERNV_MACHINE(obj);
+ PnvMachineState *pnv = PNV_MACHINE(obj);
pnv->num_chips = 1;
}
-static void powernv_machine_class_props_init(ObjectClass *oc)
+static void pnv_machine_class_props_init(ObjectClass *oc)
{
object_class_property_add(oc, "num-chips", "uint32",
pnv_get_num_chips, pnv_set_num_chips,
@@ -1083,15 +1079,15 @@ static void powernv_machine_class_props_init(ObjectClass *oc)
NULL);
}
-static void powernv_machine_class_init(ObjectClass *oc, void *data)
+static void pnv_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
mc->desc = "IBM PowerNV (Non-Virtualized)";
- mc->init = ppc_powernv_init;
- mc->reset = ppc_powernv_reset;
+ mc->init = pnv_init;
+ mc->reset = pnv_reset;
mc->max_cpus = MAX_CPUS;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
@@ -1104,7 +1100,7 @@ static void powernv_machine_class_init(ObjectClass *oc, void *data)
xic->ics_resend = pnv_ics_resend;
ispc->print_info = pnv_pic_print_info;
- powernv_machine_class_props_init(oc);
+ pnv_machine_class_props_init(oc);
}
#define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \
@@ -1116,11 +1112,11 @@ static void powernv_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo types[] = {
{
- .name = TYPE_POWERNV_MACHINE,
+ .name = TYPE_PNV_MACHINE,
.parent = TYPE_MACHINE,
.instance_size = sizeof(PnvMachineState),
- .instance_init = powernv_machine_initfn,
- .class_init = powernv_machine_class_init,
+ .instance_init = pnv_machine_initfn,
+ .class_init = pnv_machine_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_XICS_FABRIC },
{ TYPE_INTERRUPT_STATS_PROVIDER },
diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
index 7b60b4c360..b2cf441ee7 100644
--- a/hw/ppc/pnv_bmc.c
+++ b/hw/ppc/pnv_bmc.c
@@ -73,7 +73,7 @@ void pnv_bmc_powerdown(IPMIBmc *bmc)
pnv_gen_oem_sel(bmc, SOFT_OFF);
}
-void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt)
+void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt)
{
int offset;
int i;
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 03317db853..7e8a76df44 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -37,7 +37,7 @@ static const char *pnv_core_cpu_typename(PnvCore *pc)
return cpu_type;
}
-static void powernv_cpu_reset(void *opaque)
+static void pnv_cpu_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
CPUState *cs = CPU(cpu);
@@ -54,7 +54,7 @@ static void powernv_cpu_reset(void *opaque)
env->msr |= MSR_HVB; /* Hypervisor mode */
}
-static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
+static void pnv_cpu_init(PowerPCCPU *cpu, Error **errp)
{
CPUPPCState *env = &cpu->env;
int core_pir;
@@ -73,7 +73,7 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
- qemu_register_reset(powernv_cpu_reset, cpu);
+ qemu_register_reset(pnv_cpu_reset, cpu);
}
/*
@@ -139,7 +139,7 @@ static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp)
return;
}
- powernv_cpu_init(cpu, &local_err);
+ pnv_cpu_init(cpu, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index f03a80a29b..b777b78e18 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -92,7 +92,7 @@ enum {
#define LPC_HC_REGS_OPB_SIZE 0x00001000
-static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
+static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
{
const char compat[] = "ibm,power8-lpc\0ibm,lpc";
char *name;
@@ -482,7 +482,7 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
- xdc->populate = pnv_lpc_populate;
+ xdc->dt_xscom = pnv_lpc_dt_xscom;
dc->realize = pnv_lpc_realize;
}
@@ -515,7 +515,7 @@ type_init(pnv_lpc_register_types)
*/
static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
{
- PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine());
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
uint32_t old_state = pnv->cpld_irqstate;
PnvLpcController *lpc = PNV_LPC(opaque);
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 9876c26622..5b969127c3 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -510,7 +510,7 @@ static void pnv_psi_realize(DeviceState *dev, Error **errp)
}
}
-static int pnv_psi_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset)
+static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
{
const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
char *name;
@@ -546,7 +546,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
- xdc->populate = pnv_psi_populate;
+ xdc->dt_xscom = pnv_psi_dt_xscom;
dc->realize = pnv_psi_realize;
dc->props = pnv_psi_properties;
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 38bc85f117..e51d634f40 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -207,15 +207,15 @@ typedef struct ForeachPopulateArgs {
int xscom_offset;
} ForeachPopulateArgs;
-static int xscom_populate_child(Object *child, void *opaque)
+static int xscom_dt_child(Object *child, void *opaque)
{
if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
ForeachPopulateArgs *args = opaque;
PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
- if (xc->populate) {
- _FDT((xc->populate(xd, args->fdt, args->xscom_offset)));
+ if (xc->dt_xscom) {
+ _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
}
}
return 0;
@@ -224,7 +224,7 @@ static int xscom_populate_child(Object *child, void *opaque)
static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
-int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset)
+int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
{
uint64_t reg[] = { cpu_to_be64(PNV_XSCOM_BASE(chip)),
cpu_to_be64(PNV_XSCOM_SIZE) };
@@ -255,7 +255,7 @@ int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset)
args.fdt = fdt;
args.xscom_offset = xscom_offset;
- object_child_foreach(OBJECT(chip), xscom_populate_child, &args);
+ object_child_foreach(OBJECT(chip), xscom_dt_child, &args);
return 0;
}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 59524cd42b..61896f9fd7 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -26,7 +26,7 @@
#include "hw/ppc/pnv_psi.h"
#include "hw/ppc/pnv_occ.h"
-#define TYPE_PNV_CHIP "powernv-chip"
+#define TYPE_PNV_CHIP "pnv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
#define PNV_CHIP_CLASS(klass) \
OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
@@ -117,9 +117,9 @@ typedef struct PnvChipClass {
#define PNV_CHIP_INDEX(chip) \
(((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
-#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv")
-#define POWERNV_MACHINE(obj) \
- OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)
+#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
+#define PNV_MACHINE(obj) \
+ OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
typedef struct PnvMachineState {
/*< private >*/
@@ -144,7 +144,7 @@ typedef struct PnvMachineState {
/*
* BMC helpers
*/
-void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt);
+void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
void pnv_bmc_powerdown(IPMIBmc *bmc);
/*
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 38077b4796..7252e219e2 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -36,7 +36,7 @@ typedef struct PnvXScomInterface {
typedef struct PnvXScomInterfaceClass {
InterfaceClass parent;
- int (*populate)(PnvXScomInterface *dev, void *fdt, int offset);
+ int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset);
} PnvXScomInterfaceClass;
/*
@@ -67,7 +67,7 @@ typedef struct PnvXScomInterfaceClass {
#define PNV_XSCOM_OCC_SIZE 0x6000
extern void pnv_xscom_realize(PnvChip *chip, Error **errp);
-extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset);
+extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset);
extern void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
MemoryRegion *mr);
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 07/14] spapr: Capabilities infrastructure
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (5 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 06/14] ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 08/14] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability David Gibson
` (7 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-ppc, qemu-devel, mdroth, David Gibson
Because PAPR is a paravirtual environment access to certain CPU (or other)
facilities can be blocked by the hypervisor. PAPR provides ways to
advertise in the device tree whether or not those features are available to
the guest.
In some places we automatically determine whether to make a feature
available based on whether our host can support it, in most cases this is
based on limitations in the available KVM implementation.
Although we correctly advertise this to the guest, it means that host
factors might make changes to the guest visible environment which is bad:
as well as generaly reducing reproducibility, it means that a migration
between different host environments can easily go bad.
We've mostly gotten away with it because the environments considered mature
enough to be well supported (basically, KVM on POWER8) have had consistent
feature availability. But, it's still not right and some limitations on
POWER9 is going to make it more of an issue in future.
This introduces an infrastructure for defining "sPAPR capabilities". These
are set by default based on the machine version, masked by the capabilities
of the chosen cpu, but can be overriden with machine properties.
The intention is at reset time we verify that the requested capabilities
can be supported on the host (considering TCG, KVM and/or host cpu
limitations). If not we simply fail, rather than silently modifying the
advertised featureset to the guest.
This does mean that certain configurations that "worked" may now fail, but
such configurations were already more subtly broken.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/Makefile.objs | 2 +-
hw/ppc/spapr.c | 7 ++
hw/ppc/spapr_caps.c | 181 +++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 31 +++++++++
4 files changed, 220 insertions(+), 1 deletion(-)
create mode 100644 hw/ppc/spapr_caps.c
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 7efc686748..1faff853b7 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -1,7 +1,7 @@
# shared objects
obj-y += ppc.o ppc_booke.o fdt.o
# IBM pSeries (sPAPR)
-obj-$(CONFIG_PSERIES) += spapr.o spapr_vio.o spapr_events.o
+obj-$(CONFIG_PSERIES) += spapr.o spapr_caps.o spapr_vio.o spapr_events.o
obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 6785a90c60..d472baef8d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1466,6 +1466,8 @@ static void spapr_machine_reset(void)
/* Check for unknown sysbus devices */
foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
+ spapr_caps_reset(spapr);
+
first_ppc_cpu = POWERPC_CPU(first_cpu);
if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
@@ -2311,6 +2313,8 @@ static void spapr_machine_init(MachineState *machine)
char *filename;
Error *resize_hpt_err = NULL;
+ spapr_caps_validate(spapr, &error_fatal);
+
msi_nonbroken = true;
QLIST_INIT(&spapr->phbs);
@@ -3819,6 +3823,9 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
* in which LMBs are represented and hot-added
*/
mc->numa_mem_align_shift = 28;
+
+ smc->default_caps = spapr_caps(0);
+ spapr_caps_add_properties(smc, &error_abort);
}
static const TypeInfo spapr_machine_info = {
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
new file mode 100644
index 0000000000..968ba7b857
--- /dev/null
+++ b/hw/ppc/spapr_caps.c
@@ -0,0 +1,181 @@
+/*
+ * QEMU PowerPC pSeries Logical Partition capabilities handling
+ *
+ * Copyright (c) 2017 David Gibson, Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+
+#include "hw/ppc/spapr.h"
+
+typedef struct sPAPRCapabilityInfo {
+ const char *name;
+ const char *description;
+ uint64_t flag;
+
+ /* Make sure the virtual hardware can support this capability */
+ void (*allow)(sPAPRMachineState *spapr, Error **errp);
+
+ /* If possible, tell the virtual hardware not to allow the cap to
+ * be used at all */
+ void (*disallow)(sPAPRMachineState *spapr, Error **errp);
+} sPAPRCapabilityInfo;
+
+static sPAPRCapabilityInfo capability_table[] = {
+};
+
+static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
+ CPUState *cs)
+{
+ sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
+ sPAPRCapabilities caps;
+
+ caps = smc->default_caps;
+
+ /* TODO: clamp according to cpu model */
+
+ return caps;
+}
+
+void spapr_caps_reset(sPAPRMachineState *spapr)
+{
+ Error *local_err = NULL;
+ sPAPRCapabilities caps;
+ int i;
+
+ /* First compute the actual set of caps we're running with.. */
+ caps = default_caps_with_cpu(spapr, first_cpu);
+
+ caps.mask |= spapr->forced_caps.mask;
+ caps.mask &= ~spapr->forbidden_caps.mask;
+
+ spapr->effective_caps = caps;
+
+ /* .. then apply those caps to the virtual hardware */
+
+ for (i = 0; i < ARRAY_SIZE(capability_table); i++) {
+ sPAPRCapabilityInfo *info = &capability_table[i];
+
+ if (spapr->effective_caps.mask & info->flag) {
+ /* Failure to allow a cap is fatal - if the guest doesn't
+ * have it, we'll be supplying an incorrect environment */
+ if (info->allow) {
+ info->allow(spapr, &error_fatal);
+ }
+ } else {
+ /* Failure to enforce a cap is only a warning. The guest
+ * shouldn't be using it, since it's not advertised, so it
+ * doesn't get to complain about weird behaviour if it
+ * goes ahead anyway */
+ if (info->disallow) {
+ info->disallow(spapr, &local_err);
+ }
+ if (local_err) {
+ warn_report_err(local_err);
+ local_err = NULL;
+ }
+ }
+ }
+}
+
+static void spapr_cap_get(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ sPAPRCapabilityInfo *cap = opaque;
+ sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
+ bool value = spapr_has_cap(spapr, cap->flag);
+
+ /* TODO: Could this get called before effective_caps is finalized
+ * in spapr_caps_reset()? */
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+static void spapr_cap_set(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ sPAPRCapabilityInfo *cap = opaque;
+ sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
+ bool value;
+ Error *local_err = NULL;
+
+ visit_type_bool(v, name, &value, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (value) {
+ spapr->forced_caps.mask |= cap->flag;
+ } else {
+ spapr->forbidden_caps.mask |= cap->flag;
+ }
+}
+
+void spapr_caps_validate(sPAPRMachineState *spapr, Error **errp)
+{
+ uint64_t allcaps = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(capability_table); i++) {
+ g_assert((allcaps & capability_table[i].flag) == 0);
+ allcaps |= capability_table[i].flag;
+ }
+
+ g_assert((spapr->forced_caps.mask & ~allcaps) == 0);
+ g_assert((spapr->forbidden_caps.mask & ~allcaps) == 0);
+
+ if (spapr->forced_caps.mask & spapr->forbidden_caps.mask) {
+ error_setg(errp, "Some sPAPR capabilities set both on and off");
+ return;
+ }
+
+ /* Check for any caps incompatible with other caps. Nothing to do
+ * yet */
+}
+
+void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp)
+{
+ Error *local_err = NULL;
+ ObjectClass *klass = OBJECT_CLASS(smc);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(capability_table); i++) {
+ sPAPRCapabilityInfo *cap = &capability_table[i];
+ const char *name = g_strdup_printf("cap-%s", cap->name);
+
+ object_class_property_add(klass, name, "bool",
+ spapr_cap_get, spapr_cap_set, NULL,
+ cap, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ object_class_property_set_description(klass, name, cap->description,
+ &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ }
+}
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 14757b805e..5569caf1d4 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -50,6 +50,15 @@ typedef enum {
SPAPR_RESIZE_HPT_REQUIRED,
} sPAPRResizeHPT;
+/**
+ * Capabilities
+ */
+
+typedef struct sPAPRCapabilities sPAPRCapabilities;
+struct sPAPRCapabilities {
+ uint64_t mask;
+};
+
/**
* sPAPRMachineClass:
*/
@@ -66,6 +75,7 @@ struct sPAPRMachineClass {
hwaddr *mmio32, hwaddr *mmio64,
unsigned n_dma, uint32_t *liobns, Error **errp);
sPAPRResizeHPT resize_hpt_default;
+ sPAPRCapabilities default_caps;
};
/**
@@ -127,6 +137,9 @@ struct sPAPRMachineState {
MemoryHotplugState hotplug_memory;
const char *icp_type;
+
+ sPAPRCapabilities forced_caps, forbidden_caps;
+ sPAPRCapabilities effective_caps;
};
#define H_SUCCESS 0
@@ -724,4 +737,22 @@ int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
+/*
+ * Handling of optional capabilities
+ */
+static inline sPAPRCapabilities spapr_caps(uint64_t mask)
+{
+ sPAPRCapabilities caps = { mask };
+ return caps;
+}
+
+static inline bool spapr_has_cap(sPAPRMachineState *spapr, uint64_t cap)
+{
+ return !!(spapr->effective_caps.mask & cap);
+}
+
+void spapr_caps_reset(sPAPRMachineState *spapr);
+void spapr_caps_validate(sPAPRMachineState *spapr, Error **errp);
+void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp);
+
#endif /* HW_SPAPR_H */
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 08/14] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (6 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 07/14] spapr: Capabilities infrastructure David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 09/14] spapr: Validate capabilities on migration David Gibson
` (6 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-ppc, qemu-devel, mdroth, David Gibson
This adds an spapr capability bit for Hardware Transactional Memory. It is
enabled by default for pseries-2.11 and earlier machine types. with POWER8
or later CPUs (as it must be, since earlier qemu versions would implicitly
allow it). However it is disabled by default for the latest pseries-2.12
machine type.
This means that with the latest machine type, HTM will not be available,
regardless of CPU, unless it is explicitly enabled on the command line.
That change is made on the basis that:
* This way running with -M pseries,accel=tcg will start with whatever cpu
and will provide the same guest visible model as with accel=kvm.
- More specifically, this means existing make check tests don't have
to be modified to use cap-htm=off in order to run with TCG
* We hope to add a new "HTM without suspend" feature in the not too
distant future which could work on both POWER8 and POWER9 cpus, and
could be enabled by default.
* Best guesses suggest that future POWER cpus may well only support the
HTM-without-suspend model, not the (frankly, horribly overcomplicated)
POWER8 style HTM with suspend.
* Anecdotal evidence suggests problems with HTM being enabled when it
wasn't wanted are more common than being missing when it was.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr.c | 15 ++++++++++-----
hw/ppc/spapr_caps.c | 29 ++++++++++++++++++++++++++++-
include/hw/ppc/spapr.h | 3 +++
3 files changed, 41 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d472baef8d..f8fee8ebcf 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -253,7 +253,9 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
}
/* Populate the "ibm,pa-features" property */
-static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int offset,
+static void spapr_populate_pa_features(sPAPRMachineState *spapr,
+ PowerPCCPU *cpu,
+ void *fdt, int offset,
bool legacy_guest)
{
CPUPPCState *env = &cpu->env;
@@ -318,7 +320,7 @@ static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int offset,
*/
pa_features[3] |= 0x20;
}
- if (kvmppc_has_cap_htm() && pa_size > 24) {
+ if (spapr_has_cap(spapr, SPAPR_CAP_HTM) && pa_size > 24) {
pa_features[24] |= 0x80; /* Transactional memory support */
}
if (legacy_guest && pa_size > 40) {
@@ -384,8 +386,8 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
return ret;
}
- spapr_populate_pa_features(cpu, fdt, offset,
- spapr->cas_legacy_guest_workaround);
+ spapr_populate_pa_features(spapr, cpu, fdt, offset,
+ spapr->cas_legacy_guest_workaround);
}
return ret;
}
@@ -579,7 +581,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
page_sizes_prop, page_sizes_prop_size)));
}
- spapr_populate_pa_features(cpu, fdt, offset, false);
+ spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
cs->cpu_index / vcpus_per_socket)));
@@ -3903,7 +3905,10 @@ static void spapr_machine_2_11_instance_options(MachineState *machine)
static void spapr_machine_2_11_class_options(MachineClass *mc)
{
+ sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
+
spapr_machine_2_12_class_options(mc);
+ smc->default_caps = spapr_caps(SPAPR_CAP_HTM);
SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
}
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 968ba7b857..3b35b91a5b 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -24,6 +24,10 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
+#include "sysemu/hw_accel.h"
+#include "target/ppc/cpu.h"
+#include "cpu-models.h"
+#include "kvm_ppc.h"
#include "hw/ppc/spapr.h"
@@ -40,18 +44,41 @@ typedef struct sPAPRCapabilityInfo {
void (*disallow)(sPAPRMachineState *spapr, Error **errp);
} sPAPRCapabilityInfo;
+static void cap_htm_allow(sPAPRMachineState *spapr, Error **errp)
+{
+ if (tcg_enabled()) {
+ error_setg(errp,
+ "No Transactional Memory support in TCG, try cap-htm=off");
+ } else if (kvm_enabled() && !kvmppc_has_cap_htm()) {
+ error_setg(errp,
+"KVM implementation does not support Transactional Memory, try cap-htm=off"
+ );
+ }
+}
+
static sPAPRCapabilityInfo capability_table[] = {
+ {
+ .name = "htm",
+ .description = "Allow Hardware Transactional Memory (HTM)",
+ .flag = SPAPR_CAP_HTM,
+ .allow = cap_htm_allow,
+ /* TODO: add cap_htm_disallow */
+ },
};
static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
CPUState *cs)
{
sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
sPAPRCapabilities caps;
caps = smc->default_caps;
- /* TODO: clamp according to cpu model */
+ if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07,
+ 0, spapr->max_compat_pvr)) {
+ caps.mask &= ~SPAPR_CAP_HTM;
+ }
return caps;
}
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 5569caf1d4..dc64f4ebcb 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -54,6 +54,9 @@ typedef enum {
* Capabilities
*/
+/* Hardware Transactional Memory */
+#define SPAPR_CAP_HTM 0x0000000000000001ULL
+
typedef struct sPAPRCapabilities sPAPRCapabilities;
struct sPAPRCapabilities {
uint64_t mask;
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 09/14] spapr: Validate capabilities on migration
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (7 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 08/14] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 10/14] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM David Gibson
` (5 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-ppc, qemu-devel, mdroth, David Gibson
Now that the "pseries" machine type implements optional capabilities (well,
one so far) there's the possibility of having different capabilities
available at either end of a migration. Although arguably a user error,
it would be nice to catch this situation and fail as gracefully as we can.
This adds code to migrate the capabilities flags. These aren't pulled
directly into the destination's configuration since what the user has
specified on the destination command line should take precedence. However,
they are checked against the destination capabilities.
If the source was using a capability which is absent on the destination,
we fail the migration, since that could easily cause a guest crash or other
bad behaviour. If the source lacked a capability which is present on the
destination we warn, but allow the migration to proceed.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr.c | 6 ++++
hw/ppc/spapr_caps.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++--
include/hw/ppc/spapr.h | 6 ++++
3 files changed, 105 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f8fee8ebcf..86fc83f9c2 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1589,6 +1589,11 @@ static int spapr_post_load(void *opaque, int version_id)
sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
int err = 0;
+ err = spapr_caps_post_migration(spapr);
+ if (err) {
+ return err;
+ }
+
if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
CPUState *cs;
CPU_FOREACH(cs) {
@@ -1755,6 +1760,7 @@ static const VMStateDescription vmstate_spapr = {
&vmstate_spapr_ov5_cas,
&vmstate_spapr_patb_entry,
&vmstate_spapr_pending_events,
+ &vmstate_spapr_caps,
NULL
}
};
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 3b35b91a5b..cad40fe49a 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
+#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "sysemu/hw_accel.h"
@@ -83,6 +84,93 @@ static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
return caps;
}
+static bool spapr_caps_needed(void *opaque)
+{
+ sPAPRMachineState *spapr = opaque;
+
+ return (spapr->forced_caps.mask != 0) || (spapr->forbidden_caps.mask != 0);
+}
+
+/* This has to be called from the top-level spapr post_load, not the
+ * caps specific one. Otherwise it wouldn't be called when the source
+ * caps are all defaults, which could still conflict with overridden
+ * caps on the destination */
+int spapr_caps_post_migration(sPAPRMachineState *spapr)
+{
+ uint64_t allcaps = 0;
+ int i;
+ bool ok = true;
+ sPAPRCapabilities dstcaps = spapr->effective_caps;
+ sPAPRCapabilities srccaps;
+
+ srccaps = default_caps_with_cpu(spapr, first_cpu);
+ srccaps.mask |= spapr->mig_forced_caps.mask;
+ srccaps.mask &= ~spapr->mig_forbidden_caps.mask;
+
+ for (i = 0; i < ARRAY_SIZE(capability_table); i++) {
+ sPAPRCapabilityInfo *info = &capability_table[i];
+
+ allcaps |= info->flag;
+
+ if ((srccaps.mask & info->flag) && !(dstcaps.mask & info->flag)) {
+ error_report("cap-%s=on in incoming stream, but off in destination",
+ info->name);
+ ok = false;
+ }
+
+ if (!(srccaps.mask & info->flag) && (dstcaps.mask & info->flag)) {
+ warn_report("cap-%s=off in incoming stream, but on in destination",
+ info->name);
+ }
+ }
+
+ if (spapr->mig_forced_caps.mask & ~allcaps) {
+ error_report(
+ "Unknown capabilities 0x%"PRIx64" enabled in incoming stream",
+ spapr->mig_forced_caps.mask & ~allcaps);
+ ok = false;
+ }
+ if (spapr->mig_forbidden_caps.mask & ~allcaps) {
+ warn_report(
+ "Unknown capabilities 0x%"PRIx64" disabled in incoming stream",
+ spapr->mig_forbidden_caps.mask & ~allcaps);
+ }
+
+ return ok ? 0 : -EINVAL;
+}
+
+static int spapr_caps_pre_save(void *opaque)
+{
+ sPAPRMachineState *spapr = opaque;
+
+ spapr->mig_forced_caps = spapr->forced_caps;
+ spapr->mig_forbidden_caps = spapr->forbidden_caps;
+ return 0;
+}
+
+static int spapr_caps_pre_load(void *opaque)
+{
+ sPAPRMachineState *spapr = opaque;
+
+ spapr->mig_forced_caps = spapr_caps(0);
+ spapr->mig_forbidden_caps = spapr_caps(0);
+ return 0;
+}
+
+const VMStateDescription vmstate_spapr_caps = {
+ .name = "spapr/caps",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = spapr_caps_needed,
+ .pre_save = spapr_caps_pre_save,
+ .pre_load = spapr_caps_pre_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(mig_forced_caps.mask, sPAPRMachineState),
+ VMSTATE_UINT64(mig_forbidden_caps.mask, sPAPRMachineState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
void spapr_caps_reset(sPAPRMachineState *spapr)
{
Error *local_err = NULL;
@@ -92,6 +180,11 @@ void spapr_caps_reset(sPAPRMachineState *spapr)
/* First compute the actual set of caps we're running with.. */
caps = default_caps_with_cpu(spapr, first_cpu);
+ /* Remove unnecessary forced/forbidden bits (this will help us
+ * with migration) */
+ spapr->forced_caps.mask &= ~caps.mask;
+ spapr->forbidden_caps.mask &= caps.mask;
+
caps.mask |= spapr->forced_caps.mask;
caps.mask &= ~spapr->forbidden_caps.mask;
@@ -175,9 +268,6 @@ void spapr_caps_validate(sPAPRMachineState *spapr, Error **errp)
error_setg(errp, "Some sPAPR capabilities set both on and off");
return;
}
-
- /* Check for any caps incompatible with other caps. Nothing to do
- * yet */
}
void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index dc64f4ebcb..5c85f39c3b 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -54,6 +54,8 @@ typedef enum {
* Capabilities
*/
+/* These bits go in the migration stream, so they can't be reassigned */
+
/* Hardware Transactional Memory */
#define SPAPR_CAP_HTM 0x0000000000000001ULL
@@ -142,6 +144,7 @@ struct sPAPRMachineState {
const char *icp_type;
sPAPRCapabilities forced_caps, forbidden_caps;
+ sPAPRCapabilities mig_forced_caps, mig_forbidden_caps;
sPAPRCapabilities effective_caps;
};
@@ -743,6 +746,8 @@ qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
/*
* Handling of optional capabilities
*/
+extern const VMStateDescription vmstate_spapr_caps;
+
static inline sPAPRCapabilities spapr_caps(uint64_t mask)
{
sPAPRCapabilities caps = { mask };
@@ -757,5 +762,6 @@ static inline bool spapr_has_cap(sPAPRMachineState *spapr, uint64_t cap)
void spapr_caps_reset(sPAPRMachineState *spapr);
void spapr_caps_validate(sPAPRMachineState *spapr, Error **errp);
void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp);
+int spapr_caps_post_migration(sPAPRMachineState *spapr);
#endif /* HW_SPAPR_H */
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 10/14] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (8 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 09/14] spapr: Validate capabilities on migration David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 11/14] spapr: Handle VMX/VSX presence as an spapr capability flag David Gibson
` (4 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-ppc, qemu-devel, mdroth, David Gibson
When constructing the "host" cpu class we modify whether the VMX and VSX
vector extensions and DFP (Decimal Floating Point) are available
based on whether KVM can support those instructions. This can depend on
policy in the host kernel as well as on the actual host cpu capabilities.
However, the way we probe for this is not very nice: we explicitly check
the host's device tree. That works in practice, but it's not really
correct, since the device tree is a property of the host kernel's platform
which we don't really know about. We get away with it because the only
modern POWER platforms happen to encode VMX, VSX and DFP availability in
the device tree in the same way.
Arguably we should have an explicit KVM capability for this, but we haven't
needed one so far. Barring specific KVM policies which don't yet exist,
each of these instruction classes will be available in the guest if and
only if they're available in the qemu userspace process. We can determine
that from the ELF AUX vector we're supplied with.
Once reworked like this, there are no more callers for kvmppc_get_vmx() and
kvmppc_get_dfp() so remove them.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
target/ppc/kvm.c | 27 ++++++---------------------
target/ppc/kvm_ppc.h | 2 --
2 files changed, 6 insertions(+), 23 deletions(-)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 4664a3ce9d..518dd06e98 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2011,16 +2011,6 @@ uint64_t kvmppc_get_clockfreq(void)
return kvmppc_read_int_cpu_dt("clock-frequency");
}
-uint32_t kvmppc_get_vmx(void)
-{
- return kvmppc_read_int_cpu_dt("ibm,vmx");
-}
-
-uint32_t kvmppc_get_dfp(void)
-{
- return kvmppc_read_int_cpu_dt("ibm,dfp");
-}
-
static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
@@ -2404,23 +2394,18 @@ static void alter_insns(uint64_t *word, uint64_t flags, bool on)
static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
{
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
- uint32_t vmx = kvmppc_get_vmx();
- uint32_t dfp = kvmppc_get_dfp();
uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
/* Now fix up the class with information we can query from the host */
pcc->pvr = mfpvr();
- if (vmx != -1) {
- /* Only override when we know what the host supports */
- alter_insns(&pcc->insns_flags, PPC_ALTIVEC, vmx > 0);
- alter_insns(&pcc->insns_flags2, PPC2_VSX, vmx > 1);
- }
- if (dfp != -1) {
- /* Only override when we know what the host supports */
- alter_insns(&pcc->insns_flags2, PPC2_DFP, dfp);
- }
+ alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
+ qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
+ alter_insns(&pcc->insns_flags2, PPC2_VSX,
+ qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
+ alter_insns(&pcc->insns_flags2, PPC2_DFP,
+ qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
if (dcache_size != -1) {
pcc->l1_dcache_size = dcache_size;
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index d6be38ecaf..ecb55493cc 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -15,8 +15,6 @@
uint32_t kvmppc_get_tbfreq(void);
uint64_t kvmppc_get_clockfreq(void);
-uint32_t kvmppc_get_vmx(void);
-uint32_t kvmppc_get_dfp(void);
bool kvmppc_get_host_model(char **buf);
bool kvmppc_get_host_serial(char **buf);
int kvmppc_get_hasidle(CPUPPCState *env);
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 11/14] spapr: Handle VMX/VSX presence as an spapr capability flag
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (9 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 10/14] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 12/14] spapr: Handle Decimal Floating Point (DFP) as an optional capability David Gibson
` (3 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-ppc, qemu-devel, mdroth, David Gibson
We currently have some conditionals in the spapr device tree code to decide
whether or not to advertise the availability of the VMX (aka Altivec) and
VSX vector extensions to the guest, based on whether the guest cpu has
those features.
This can lead to confusion and subtle failures on migration, since it makes
a guest visible change based only on host capabilities. We now have a
better mechanism for this, in spapr capabilities flags, which explicitly
depend on user options rather than host capabilities.
Rework the advertisement of VSX and VMX based on a new VSX capability. We
no longer bother with a conditional for VMX support, because every CPU
that's ever been supported by the pseries machine type supports VMX.
NOTE: Some userspace distributions (e.g. RHEL7.4) already rely on
availability of VSX in libc, so using cap-vsx=off may lead to a fatal
SIGILL in init.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr.c | 20 +++++++++++---------
hw/ppc/spapr_caps.c | 25 +++++++++++++++++++++++++
include/hw/ppc/spapr.h | 3 +++
3 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 86fc83f9c2..693dd6f7b3 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -557,14 +557,16 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
segs, sizeof(segs))));
}
- /* Advertise VMX/VSX (vector extensions) if available
- * 0 / no property == no vector extensions
+ /* Advertise VSX (vector extensions) if available
* 1 == VMX / Altivec available
- * 2 == VSX available */
- if (env->insns_flags & PPC_ALTIVEC) {
- uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
-
- _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
+ * 2 == VSX available
+ *
+ * Only CPUs for which we create core types in spapr_cpu_core.c
+ * are possible, and all of those have VMX */
+ if (spapr_has_cap(spapr, SPAPR_CAP_VSX)) {
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
+ } else {
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
}
/* Advertise DFP (Decimal Floating Point) if available
@@ -3832,7 +3834,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
*/
mc->numa_mem_align_shift = 28;
- smc->default_caps = spapr_caps(0);
+ smc->default_caps = spapr_caps(SPAPR_CAP_VSX);
spapr_caps_add_properties(smc, &error_abort);
}
@@ -3914,7 +3916,7 @@ static void spapr_machine_2_11_class_options(MachineClass *mc)
sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
spapr_machine_2_12_class_options(mc);
- smc->default_caps = spapr_caps(SPAPR_CAP_HTM);
+ smc->default_caps = spapr_caps(SPAPR_CAP_HTM | SPAPR_CAP_VSX);
SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
}
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index cad40fe49a..7c855c67ad 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -57,6 +57,19 @@ static void cap_htm_allow(sPAPRMachineState *spapr, Error **errp)
}
}
+static void cap_vsx_allow(sPAPRMachineState *spapr, Error **errp)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ CPUPPCState *env = &cpu->env;
+
+ /* Allowable CPUs in spapr_cpu_core.c should already have gotten
+ * rid of anything that doesn't do VMX */
+ g_assert(env->insns_flags & PPC_ALTIVEC);
+ if (!(env->insns_flags2 & PPC2_VSX)) {
+ error_setg(errp, "VSX support not available, try cap-vsx=off");
+ }
+}
+
static sPAPRCapabilityInfo capability_table[] = {
{
.name = "htm",
@@ -65,6 +78,13 @@ static sPAPRCapabilityInfo capability_table[] = {
.allow = cap_htm_allow,
/* TODO: add cap_htm_disallow */
},
+ {
+ .name = "vsx",
+ .description = "Allow Vector Scalar Extensions (VSX)",
+ .flag = SPAPR_CAP_VSX,
+ .allow = cap_vsx_allow,
+ /* TODO: add cap_vsx_disallow */
+ },
};
static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
@@ -81,6 +101,11 @@ static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
caps.mask &= ~SPAPR_CAP_HTM;
}
+ if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06,
+ 0, spapr->max_compat_pvr)) {
+ caps.mask &= ~SPAPR_CAP_VSX;
+ }
+
return caps;
}
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 5c85f39c3b..148a03d189 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -59,6 +59,9 @@ typedef enum {
/* Hardware Transactional Memory */
#define SPAPR_CAP_HTM 0x0000000000000001ULL
+/* Vector Scalar Extensions */
+#define SPAPR_CAP_VSX 0x0000000000000002ULL
+
typedef struct sPAPRCapabilities sPAPRCapabilities;
struct sPAPRCapabilities {
uint64_t mask;
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 12/14] spapr: Handle Decimal Floating Point (DFP) as an optional capability
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (10 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 11/14] spapr: Handle VMX/VSX presence as an spapr capability flag David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 13/14] spapr_pci: use warn_report() David Gibson
` (2 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-ppc, qemu-devel, mdroth, David Gibson
Decimal Floating Point has been available on POWER7 and later (server)
cpus. However, it can be disabled on the hypervisor, meaning that it's
not available to guests.
We currently handle this by conditionally advertising DFP support in the
device tree depending on whether the guest CPU model supports it - which
can also depend on what's allowed in the host for -cpu host. That can lead
to confusion on migration, since host properties are silently affecting
guest visible properties.
This patch handles it by treating it as an optional capability for the
pseries machine type.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr.c | 7 ++++---
hw/ppc/spapr_caps.c | 18 ++++++++++++++++++
include/hw/ppc/spapr.h | 3 +++
3 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 693dd6f7b3..e22888ba06 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -572,7 +572,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
/* Advertise DFP (Decimal Floating Point) if available
* 0 / no property == no DFP
* 1 == DFP available */
- if (env->insns_flags2 & PPC2_DFP) {
+ if (spapr_has_cap(spapr, SPAPR_CAP_DFP)) {
_FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
}
@@ -3834,7 +3834,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
*/
mc->numa_mem_align_shift = 28;
- smc->default_caps = spapr_caps(SPAPR_CAP_VSX);
+ smc->default_caps = spapr_caps(SPAPR_CAP_VSX | SPAPR_CAP_DFP);
spapr_caps_add_properties(smc, &error_abort);
}
@@ -3916,7 +3916,8 @@ static void spapr_machine_2_11_class_options(MachineClass *mc)
sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
spapr_machine_2_12_class_options(mc);
- smc->default_caps = spapr_caps(SPAPR_CAP_HTM | SPAPR_CAP_VSX);
+ smc->default_caps = spapr_caps(SPAPR_CAP_HTM | SPAPR_CAP_VSX
+ | SPAPR_CAP_DFP);
SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
}
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 7c855c67ad..9d070a306c 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -70,6 +70,16 @@ static void cap_vsx_allow(sPAPRMachineState *spapr, Error **errp)
}
}
+static void cap_dfp_allow(sPAPRMachineState *spapr, Error **errp)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ CPUPPCState *env = &cpu->env;
+
+ if (!(env->insns_flags2 & PPC2_DFP)) {
+ error_setg(errp, "DFP support not available, try cap-dfp=off");
+ }
+}
+
static sPAPRCapabilityInfo capability_table[] = {
{
.name = "htm",
@@ -85,6 +95,13 @@ static sPAPRCapabilityInfo capability_table[] = {
.allow = cap_vsx_allow,
/* TODO: add cap_vsx_disallow */
},
+ {
+ .name = "dfp",
+ .description = "Allow Decimal Floating Point (DFP)",
+ .flag = SPAPR_CAP_DFP,
+ .allow = cap_dfp_allow,
+ /* TODO: add cap_dfp_disallow */
+ },
};
static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
@@ -104,6 +121,7 @@ static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06,
0, spapr->max_compat_pvr)) {
caps.mask &= ~SPAPR_CAP_VSX;
+ caps.mask &= ~SPAPR_CAP_DFP;
}
return caps;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 148a03d189..26ac17e641 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -62,6 +62,9 @@ typedef enum {
/* Vector Scalar Extensions */
#define SPAPR_CAP_VSX 0x0000000000000002ULL
+/* Decimal Floating Point */
+#define SPAPR_CAP_DFP 0x0000000000000004ULL
+
typedef struct sPAPRCapabilities sPAPRCapabilities;
struct sPAPRCapabilities {
uint64_t mask;
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 13/14] spapr_pci: use warn_report()
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (11 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 12/14] spapr: Handle Decimal Floating Point (DFP) as an optional capability David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 14/14] hw/ide: Emulate SiI3112 SATA controller David Gibson
2017-12-20 11:29 ` [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 Peter Maydell
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-ppc, qemu-devel, mdroth, David Gibson
From: Greg Kurz <groug@kaod.org>
These two are definitely warnings. Let's use the appropriate API.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_pci.c | 6 +++---
hw/ppc/spapr_pci_vfio.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 88797b3d36..695c820911 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -1696,9 +1696,9 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
/* DMA setup */
if (((sphb->page_size_mask & qemu_getrampagesize()) == 0)
&& kvm_enabled()) {
- error_report("System page size 0x%lx is not enabled in page_size_mask "
- "(0x%"PRIx64"). Performance may be slow",
- qemu_getrampagesize(), sphb->page_size_mask);
+ warn_report("System page size 0x%lx is not enabled in page_size_mask "
+ "(0x%"PRIx64"). Performance may be slow",
+ qemu_getrampagesize(), sphb->page_size_mask);
}
for (i = 0; i < windows_supported; ++i) {
diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c
index 8448e0b024..1f775ea93d 100644
--- a/hw/ppc/spapr_pci_vfio.c
+++ b/hw/ppc/spapr_pci_vfio.c
@@ -50,7 +50,7 @@ static Property spapr_phb_vfio_properties[] = {
static void spapr_phb_vfio_instance_init(Object *obj)
{
if (!qtest_enabled()) {
- error_report("spapr-pci-vfio-host-bridge is deprecated");
+ warn_report("spapr-pci-vfio-host-bridge is deprecated");
}
}
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL 14/14] hw/ide: Emulate SiI3112 SATA controller
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (12 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 13/14] spapr_pci: use warn_report() David Gibson
@ 2017-12-19 4:29 ` David Gibson
2017-12-20 11:29 ` [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 Peter Maydell
14 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2017-12-19 4:29 UTC (permalink / raw)
To: peter.maydell
Cc: groug, qemu-ppc, qemu-devel, mdroth, BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
This is a common generic PCI SATA controller that is also used in PCs
but more importantly guests running on the Sam460ex board prefer this
card and have a driver for it (unlike for other SATA controllers
already emulated).
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
MAINTAINERS | 6 +
default-configs/ppcemb-softmmu.mak | 1 +
hw/ide/Makefile.objs | 1 +
hw/ide/sii3112.c | 368 +++++++++++++++++++++++++++++++++++++
hw/ide/trace-events | 5 +
5 files changed, 381 insertions(+)
create mode 100644 hw/ide/sii3112.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 8859a50c36..399ba2c94b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -765,6 +765,12 @@ L: qemu-ppc@nongnu.org
S: Odd Fixes
F: hw/ppc/virtex_ml507.c
+sam460ex
+M: BALATON Zoltan <balaton@eik.bme.hu>
+L: qemu-ppc@nongnu.org
+S: Maintained
+F: hw/ide/sii3112.c
+
SH4 Machines
------------
R2D
diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-softmmu.mak
index 13917fb7a3..5db4618a5a 100644
--- a/default-configs/ppcemb-softmmu.mak
+++ b/default-configs/ppcemb-softmmu.mak
@@ -16,3 +16,4 @@ CONFIG_I8259=y
CONFIG_XILINX=y
CONFIG_XILINX_ETHLITE=y
CONFIG_SM501=y
+CONFIG_IDE_SII3112=y
diff --git a/hw/ide/Makefile.objs b/hw/ide/Makefile.objs
index f0edca3300..fc328ffbe8 100644
--- a/hw/ide/Makefile.objs
+++ b/hw/ide/Makefile.objs
@@ -11,3 +11,4 @@ common-obj-$(CONFIG_MICRODRIVE) += microdrive.o
common-obj-$(CONFIG_AHCI) += ahci.o
common-obj-$(CONFIG_AHCI) += ich.o
common-obj-$(CONFIG_ALLWINNER_A10) += ahci-allwinner.o
+common-obj-$(CONFIG_IDE_SII3112) += sii3112.o
diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c
new file mode 100644
index 0000000000..e2f5562bb7
--- /dev/null
+++ b/hw/ide/sii3112.c
@@ -0,0 +1,368 @@
+/*
+ * QEMU SiI3112A PCI to Serial ATA Controller Emulation
+ *
+ * Copyright (C) 2017 BALATON Zoltan <balaton@eik.bme.hu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+/* For documentation on this and similar cards see:
+ * http://wiki.osdev.org/User:Quok/Silicon_Image_Datasheets
+ */
+
+#include <qemu/osdep.h>
+#include <hw/ide/pci.h>
+#include "trace.h"
+
+#define TYPE_SII3112_PCI "sii3112"
+#define SII3112_PCI(obj) OBJECT_CHECK(SiI3112PCIState, (obj), \
+ TYPE_SII3112_PCI)
+
+typedef struct SiI3112Regs {
+ uint32_t confstat;
+ uint32_t scontrol;
+ uint16_t sien;
+ uint8_t swdata;
+} SiI3112Regs;
+
+typedef struct SiI3112PCIState {
+ PCIIDEState i;
+ MemoryRegion mmio;
+ SiI3112Regs regs[2];
+} SiI3112PCIState;
+
+/* The sii3112_reg_read and sii3112_reg_write functions implement the
+ * Internal Register Space - BAR5 (section 6.7 of the data sheet).
+ */
+
+static uint64_t sii3112_reg_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ SiI3112PCIState *d = opaque;
+ uint64_t val = 0;
+
+ switch (addr) {
+ case 0x00:
+ val = d->i.bmdma[0].cmd;
+ break;
+ case 0x01:
+ val = d->regs[0].swdata;
+ break;
+ case 0x02:
+ val = d->i.bmdma[0].status;
+ break;
+ case 0x03:
+ val = 0;
+ break;
+ case 0x04 ... 0x07:
+ val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size);
+ break;
+ case 0x08:
+ val = d->i.bmdma[1].cmd;
+ break;
+ case 0x09:
+ val = d->regs[1].swdata;
+ break;
+ case 0x0a:
+ val = d->i.bmdma[1].status;
+ break;
+ case 0x0b:
+ val = 0;
+ break;
+ case 0x0c ... 0x0f:
+ val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size);
+ break;
+ case 0x10:
+ val = d->i.bmdma[0].cmd;
+ val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/
+ val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/
+ val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0);
+ val |= d->i.bmdma[0].status << 16;
+ val |= d->i.bmdma[1].status << 24;
+ break;
+ case 0x18:
+ val = d->i.bmdma[1].cmd;
+ val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0);
+ val |= d->i.bmdma[1].status << 16;
+ break;
+ case 0x80 ... 0x87:
+ if (size == 1) {
+ val = ide_ioport_read(&d->i.bus[0], addr - 0x80);
+ } else if (addr == 0x80) {
+ val = (size == 2) ? ide_data_readw(&d->i.bus[0], 0) :
+ ide_data_readl(&d->i.bus[0], 0);
+ } else {
+ val = (1ULL << (size * 8)) - 1;
+ }
+ break;
+ case 0x8a:
+ val = (size == 1) ? ide_status_read(&d->i.bus[0], 4) :
+ (1ULL << (size * 8)) - 1;
+ break;
+ case 0xa0:
+ val = d->regs[0].confstat;
+ break;
+ case 0xc0 ... 0xc7:
+ if (size == 1) {
+ val = ide_ioport_read(&d->i.bus[1], addr - 0xc0);
+ } else if (addr == 0xc0) {
+ val = (size == 2) ? ide_data_readw(&d->i.bus[1], 0) :
+ ide_data_readl(&d->i.bus[1], 0);
+ } else {
+ val = (1ULL << (size * 8)) - 1;
+ }
+ break;
+ case 0xca:
+ val = (size == 1) ? ide_status_read(&d->i.bus[0], 4) :
+ (1ULL << (size * 8)) - 1;
+ break;
+ case 0xe0:
+ val = d->regs[1].confstat;
+ break;
+ case 0x100:
+ val = d->regs[0].scontrol;
+ break;
+ case 0x104:
+ val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0;
+ break;
+ case 0x148:
+ val = d->regs[0].sien << 16;
+ break;
+ case 0x180:
+ val = d->regs[1].scontrol;
+ break;
+ case 0x184:
+ val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0;
+ break;
+ case 0x1c8:
+ val = d->regs[1].sien << 16;
+ break;
+ default:
+ val = 0;
+ }
+ trace_sii3112_read(size, addr, val);
+ return val;
+}
+
+static void sii3112_reg_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int size)
+{
+ SiI3112PCIState *d = opaque;
+
+ trace_sii3112_write(size, addr, val);
+ switch (addr) {
+ case 0x00:
+ case 0x10:
+ bmdma_cmd_writeb(&d->i.bmdma[0], val);
+ break;
+ case 0x01:
+ case 0x11:
+ d->regs[0].swdata = val & 0x3f;
+ break;
+ case 0x02:
+ case 0x12:
+ d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) |
+ (d->i.bmdma[0].status & ~val & 6);
+ break;
+ case 0x04 ... 0x07:
+ bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size);
+ break;
+ case 0x08:
+ case 0x18:
+ bmdma_cmd_writeb(&d->i.bmdma[1], val);
+ break;
+ case 0x09:
+ case 0x19:
+ d->regs[1].swdata = val & 0x3f;
+ break;
+ case 0x0a:
+ case 0x1a:
+ d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) |
+ (d->i.bmdma[1].status & ~val & 6);
+ break;
+ case 0x0c ... 0x0f:
+ bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);
+ break;
+ case 0x80 ... 0x87:
+ if (size == 1) {
+ ide_ioport_write(&d->i.bus[0], addr - 0x80, val);
+ } else if (addr == 0x80) {
+ if (size == 2) {
+ ide_data_writew(&d->i.bus[0], 0, val);
+ } else {
+ ide_data_writel(&d->i.bus[0], 0, val);
+ }
+ }
+ break;
+ case 0x8a:
+ if (size == 1) {
+ ide_cmd_write(&d->i.bus[0], 4, val);
+ }
+ break;
+ case 0xc0 ... 0xc7:
+ if (size == 1) {
+ ide_ioport_write(&d->i.bus[1], addr - 0xc0, val);
+ } else if (addr == 0xc0) {
+ if (size == 2) {
+ ide_data_writew(&d->i.bus[1], 0, val);
+ } else {
+ ide_data_writel(&d->i.bus[1], 0, val);
+ }
+ }
+ break;
+ case 0xca:
+ if (size == 1) {
+ ide_cmd_write(&d->i.bus[1], 4, val);
+ }
+ break;
+ case 0x100:
+ d->regs[0].scontrol = val & 0xfff;
+ if (val & 1) {
+ ide_bus_reset(&d->i.bus[0]);
+ }
+ break;
+ case 0x148:
+ d->regs[0].sien = (val >> 16) & 0x3eed;
+ break;
+ case 0x180:
+ d->regs[1].scontrol = val & 0xfff;
+ if (val & 1) {
+ ide_bus_reset(&d->i.bus[1]);
+ }
+ break;
+ case 0x1c8:
+ d->regs[1].sien = (val >> 16) & 0x3eed;
+ break;
+ default:
+ val = 0;
+ }
+}
+
+static const MemoryRegionOps sii3112_reg_ops = {
+ .read = sii3112_reg_read,
+ .write = sii3112_reg_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* the PCI irq level is the logical OR of the two channels */
+static void sii3112_update_irq(SiI3112PCIState *s)
+{
+ int i, set = 0;
+
+ for (i = 0; i < 2; i++) {
+ set |= s->regs[i].confstat & (1UL << 11);
+ }
+ pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0));
+}
+
+static void sii3112_set_irq(void *opaque, int channel, int level)
+{
+ SiI3112PCIState *s = opaque;
+
+ trace_sii3112_set_irq(channel, level);
+ if (level) {
+ s->regs[channel].confstat |= (1UL << 11);
+ } else {
+ s->regs[channel].confstat &= ~(1UL << 11);
+ }
+
+ sii3112_update_irq(s);
+}
+
+static void sii3112_reset(void *opaque)
+{
+ SiI3112PCIState *s = opaque;
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ s->regs[i].confstat = 0x6515 << 16;
+ ide_bus_reset(&s->i.bus[i]);
+ }
+}
+
+static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
+{
+ SiI3112PCIState *d = SII3112_PCI(dev);
+ PCIIDEState *s = PCI_IDE(dev);
+ MemoryRegion *mr;
+ qemu_irq *irq;
+ int i;
+
+ pci_config_set_interrupt_pin(dev->config, 1);
+ pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8);
+
+ /* BAR5 is in PCI memory space */
+ memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d,
+ "sii3112.bar5", 0x200);
+ pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
+
+ /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */
+ mr = g_new(MemoryRegion, 1);
+ memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8);
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr);
+ mr = g_new(MemoryRegion, 1);
+ memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4);
+ pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr);
+ mr = g_new(MemoryRegion, 1);
+ memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8);
+ pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr);
+ mr = g_new(MemoryRegion, 1);
+ memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4);
+ pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr);
+ mr = g_new(MemoryRegion, 1);
+ memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16);
+ pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr);
+
+ irq = qemu_allocate_irqs(sii3112_set_irq, d, 2);
+ for (i = 0; i < 2; i++) {
+ ide_bus_new(&s->bus[i], sizeof(s->bus[i]), DEVICE(dev), i, 1);
+ ide_init2(&s->bus[i], irq[i]);
+
+ bmdma_init(&s->bus[i], &s->bmdma[i], s);
+ s->bmdma[i].bus = &s->bus[i];
+ ide_register_restart_cb(&s->bus[i]);
+ }
+ qemu_register_reset(sii3112_reset, s);
+}
+
+static void sii3112_pci_exitfn(PCIDevice *dev)
+{
+ PCIIDEState *d = PCI_IDE(dev);
+ int i;
+
+ for (i = 0; i < 2; ++i) {
+ memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
+ memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
+ }
+}
+
+static void sii3112_pci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass);
+
+ pd->vendor_id = 0x1095;
+ pd->device_id = 0x3112;
+ pd->class_id = PCI_CLASS_STORAGE_RAID;
+ pd->revision = 1;
+ pd->realize = sii3112_pci_realize;
+ pd->exit = sii3112_pci_exitfn;
+ dc->desc = "SiI3112A SATA controller";
+ set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
+}
+
+static const TypeInfo sii3112_pci_info = {
+ .name = TYPE_SII3112_PCI,
+ .parent = TYPE_PCI_IDE,
+ .instance_size = sizeof(SiI3112PCIState),
+ .class_init = sii3112_pci_class_init,
+};
+
+static void sii3112_register_types(void)
+{
+ type_register_static(&sii3112_pci_info);
+}
+
+type_init(sii3112_register_types)
diff --git a/hw/ide/trace-events b/hw/ide/trace-events
index 601bd97d81..0c39cabe72 100644
--- a/hw/ide/trace-events
+++ b/hw/ide/trace-events
@@ -37,6 +37,11 @@ bmdma_addr_write(uint64_t data) "data: 0x%016"PRIx64
bmdma_read(uint64_t addr, uint8_t val) "bmdma: readb 0x%"PRIx64" : 0x%02x"
bmdma_write(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64" : 0x%02"PRIx64
+# hw/ide/sii3112.c
+sii3112_read(int size, uint64_t addr, uint64_t val) "bmdma: read (size %d) 0x%"PRIx64" : 0x%02"PRIx64
+sii3112_write(int size, uint64_t addr, uint64_t val) "bmdma: write (size %d) 0x%"PRIx64" : 0x%02"PRIx64
+sii3112_set_irq(int channel, int level) "channel %d level %d"
+
# hw/ide/via.c
bmdma_read_via(uint64_t addr, uint32_t val) "bmdma: readb 0x%"PRIx64" : 0x%02x"
bmdma_write_via(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64" : 0x%02"PRIx64
--
2.14.3
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
` (13 preceding siblings ...)
2017-12-19 4:29 ` [Qemu-devel] [PULL 14/14] hw/ide: Emulate SiI3112 SATA controller David Gibson
@ 2017-12-20 11:29 ` Peter Maydell
2017-12-20 13:45 ` David Gibson
14 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2017-12-20 11:29 UTC (permalink / raw)
To: David Gibson; +Cc: Greg Kurz, qemu-ppc, QEMU Developers, Michael Roth
On 19 December 2017 at 04:29, David Gibson <david@gibson.dropbear.id.au> wrote:
> The following changes since commit eaefea537b476cb853e2edbdc68e969ec777e4bb:
>
> Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging (2017-12-18 14:17:42 +0000)
>
> are available in the Git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20171219
>
> for you to fetch changes up to eec745d4366076dee068750ea80245e1a46e9c13:
>
> hw/ide: Emulate SiI3112 SATA controller (2017-12-19 15:24:28 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue 2017-12-19
>
> Here's a second batch of patches for qemu-2.12. Highlights are:
>
> * Optional capabilities for the "pseries" machine. This removes
> some places where we were changing guest visible properties based
> on host capabilities, which makes life very bad for migration.
> * SLOF update
> * Significant TCG speedup from Paolo
> * Several new devices for embedded platforms
> * Some minor cleanups
>
Migration test hangs on aarch32 host/ppc guest:
peter.m+ 3942 0.0 0.0 1452 412 pts/0 S+ Dec19 0:00 |
\_ /bin/sh -c
QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64
QTEST_QEMU_IMG=qemu-img MALLOC_PERTURB_=${MALLOC_PERTURB_:-$((
${RANDOM:-0} % 255 + 1))} gtester -k --verbose -m=quick
tests/spapr-phb-test tests/endianness-test tests/boot-order-test
tests/prom-env-test tests/pnv-xscom-test tests/drive_del-test
tests/migration-test tests/boot-serial-test tests/rtas-test
tests/pxe-test tests/usb-hcd-ohci-test tests/usb-hcd-uhci-test
tests/usb-hcd-xhci-test tests/virtio-net-test
tests/virtio-balloon-test tests/virtio-blk-test tests/virtio-rng-test
tests/virtio-scsi-test tests/virtio-9p-test tests/virtio-serial-test
tests/virtio-console-test tests/test-netfilter
tests/test-filter-mirror tests/test-filter-redirector
tests/display-vga-test tests/numa-test tests/ivshmem-test
tests/qmp-test tests/device-introspect-test tests/qom-test
tests/test-hmp
peter.m+ 3943 0.0 0.0 11984 1828 pts/0 Sl+ Dec19 0:00 |
\_ gtester -k --verbose -m=quick
tests/spapr-phb-test tests/endianness-test tests/boot-order-test
tests/prom-env-test tests/pnv-xscom-test tests/drive_del-test
tests/migration-test tests/boot-serial-test tests/rtas-test
tests/pxe-test tests/usb-hcd-ohci-test tests/usb-hcd-uhci-test
tests/usb-hcd-xhci-test tests/virtio-net-test
tests/virtio-balloon-test tests/virtio-blk-test tests/virtio-rng-test
tests/virtio-scsi-test tests/virtio-9p-test tests/virtio-serial-test
tests/virtio-console-test tests/test-netfilter
tests/test-filter-mirror tests/test-filter-redirector
tests/display-vga-test tests/numa-test tests/ivshmem-test
tests/qmp-test tests/device-introspect-test tests/qom-test
tests/test-hmp
peter.m+ 4041 99.9 0.0 3460 824 pts/0 R+ Dec19 809:16 |
\_ tests/migration-test --quiet
--keep-going -m=quick --GTestLogFD=6
peter.m+ 4042 99.9 0.4 607804 72924 pts/0 Sl+ Dec19 809:50 |
\_ ppc64-softmmu/qemu-system-ppc64
-qtest unix:/tmp/qtest-4041.sock,nowait -qtest-log /dev/null -qmp
unix:/tmp/qtest-4041.qmp,nowait -machine accel=qtest -display none
-machine accel=tcg -m 256M -name pcsource,debug-threads=on -serial
file:/tmp/migration-test-vxvkIZ/src_serial -drive
file=/tmp/migration-test-vxvkIZ/bootsect,if=pflash,format=raw
peter.m+ 4046 0.0 0.3 596596 49696 pts/0 Sl+ Dec19 0:01 |
\_ ppc64-softmmu/qemu-system-ppc64
-qtest unix:/tmp/qtest-4041.sock,nowait -qtest-log /dev/null -qmp
unix:/tmp/qtest-4041.qmp,nowait -machine accel=qtest -display none
-machine accel=tcg -m 256M -name pcdest,debug-threads=on -serial
file:/tmp/migration-test-vxvkIZ/dest_serial -incoming
unix:/tmp/migration-test-vxvkIZ/migsocket
Process 4041/4042 are using 100% CPU.
$ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 gtester -k
--verbose -m=quick tests/migration-test
TEST: tests/migration-test... (pid=5441)
/ppc64/migration/postcopy/unix:
[hangs]
My first guess is that this is a general 32-bit host issue
rather than an arm-host specific one; arm just happens to
be the only 32-bit system in my test set.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219
2017-12-20 11:29 ` [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 Peter Maydell
@ 2017-12-20 13:45 ` David Gibson
2017-12-21 8:40 ` David Gibson
0 siblings, 1 reply; 19+ messages in thread
From: David Gibson @ 2017-12-20 13:45 UTC (permalink / raw)
To: Peter Maydell; +Cc: Greg Kurz, qemu-ppc, QEMU Developers, Michael Roth
[-- Attachment #1: Type: text/plain, Size: 5105 bytes --]
On Wed, Dec 20, 2017 at 11:29:36AM +0000, Peter Maydell wrote:
> On 19 December 2017 at 04:29, David Gibson <david@gibson.dropbear.id.au> wrote:
> > The following changes since commit eaefea537b476cb853e2edbdc68e969ec777e4bb:
> >
> > Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging (2017-12-18 14:17:42 +0000)
> >
> > are available in the Git repository at:
> >
> > git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20171219
> >
> > for you to fetch changes up to eec745d4366076dee068750ea80245e1a46e9c13:
> >
> > hw/ide: Emulate SiI3112 SATA controller (2017-12-19 15:24:28 +1100)
> >
> > ----------------------------------------------------------------
> > ppc patch queue 2017-12-19
> >
> > Here's a second batch of patches for qemu-2.12. Highlights are:
> >
> > * Optional capabilities for the "pseries" machine. This removes
> > some places where we were changing guest visible properties based
> > on host capabilities, which makes life very bad for migration.
> > * SLOF update
> > * Significant TCG speedup from Paolo
> > * Several new devices for embedded platforms
> > * Some minor cleanups
> >
>
> Migration test hangs on aarch32 host/ppc guest:
>
> peter.m+ 3942 0.0 0.0 1452 412 pts/0 S+ Dec19 0:00 |
> \_ /bin/sh -c
> QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64
> QTEST_QEMU_IMG=qemu-img MALLOC_PERTURB_=${MALLOC_PERTURB_:-$((
> ${RANDOM:-0} % 255 + 1))} gtester -k --verbose -m=quick
> tests/spapr-phb-test tests/endianness-test tests/boot-order-test
> tests/prom-env-test tests/pnv-xscom-test tests/drive_del-test
> tests/migration-test tests/boot-serial-test tests/rtas-test
> tests/pxe-test tests/usb-hcd-ohci-test tests/usb-hcd-uhci-test
> tests/usb-hcd-xhci-test tests/virtio-net-test
> tests/virtio-balloon-test tests/virtio-blk-test tests/virtio-rng-test
> tests/virtio-scsi-test tests/virtio-9p-test tests/virtio-serial-test
> tests/virtio-console-test tests/test-netfilter
> tests/test-filter-mirror tests/test-filter-redirector
> tests/display-vga-test tests/numa-test tests/ivshmem-test
> tests/qmp-test tests/device-introspect-test tests/qom-test
> tests/test-hmp
> peter.m+ 3943 0.0 0.0 11984 1828 pts/0 Sl+ Dec19 0:00 |
> \_ gtester -k --verbose -m=quick
> tests/spapr-phb-test tests/endianness-test tests/boot-order-test
> tests/prom-env-test tests/pnv-xscom-test tests/drive_del-test
> tests/migration-test tests/boot-serial-test tests/rtas-test
> tests/pxe-test tests/usb-hcd-ohci-test tests/usb-hcd-uhci-test
> tests/usb-hcd-xhci-test tests/virtio-net-test
> tests/virtio-balloon-test tests/virtio-blk-test tests/virtio-rng-test
> tests/virtio-scsi-test tests/virtio-9p-test tests/virtio-serial-test
> tests/virtio-console-test tests/test-netfilter
> tests/test-filter-mirror tests/test-filter-redirector
> tests/display-vga-test tests/numa-test tests/ivshmem-test
> tests/qmp-test tests/device-introspect-test tests/qom-test
> tests/test-hmp
> peter.m+ 4041 99.9 0.0 3460 824 pts/0 R+ Dec19 809:16 |
> \_ tests/migration-test --quiet
> --keep-going -m=quick --GTestLogFD=6
> peter.m+ 4042 99.9 0.4 607804 72924 pts/0 Sl+ Dec19 809:50 |
> \_ ppc64-softmmu/qemu-system-ppc64
> -qtest unix:/tmp/qtest-4041.sock,nowait -qtest-log /dev/null -qmp
> unix:/tmp/qtest-4041.qmp,nowait -machine accel=qtest -display none
> -machine accel=tcg -m 256M -name pcsource,debug-threads=on -serial
> file:/tmp/migration-test-vxvkIZ/src_serial -drive
> file=/tmp/migration-test-vxvkIZ/bootsect,if=pflash,format=raw
> peter.m+ 4046 0.0 0.3 596596 49696 pts/0 Sl+ Dec19 0:01 |
> \_ ppc64-softmmu/qemu-system-ppc64
> -qtest unix:/tmp/qtest-4041.sock,nowait -qtest-log /dev/null -qmp
> unix:/tmp/qtest-4041.qmp,nowait -machine accel=qtest -display none
> -machine accel=tcg -m 256M -name pcdest,debug-threads=on -serial
> file:/tmp/migration-test-vxvkIZ/dest_serial -incoming
> unix:/tmp/migration-test-vxvkIZ/migsocket
>
>
> Process 4041/4042 are using 100% CPU.
>
> $ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 gtester -k
> --verbose -m=quick tests/migration-test
> TEST: tests/migration-test... (pid=5441)
> /ppc64/migration/postcopy/unix:
> [hangs]
>
> My first guess is that this is a general 32-bit host issue
> rather than an arm-host specific one; arm just happens to
> be the only 32-bit system in my test set.
Oh :(. I ran make check SPEED=slow in a 32-bit x86 container before
sending the pull request, and I just retried it now, so that doesn't
appear to be the case.
I haven't the foggiest what could be broken in an arm host specific
way, though. Nor do I have easy access to an arm system to track it
down on.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219
2017-12-20 13:45 ` David Gibson
@ 2017-12-21 8:40 ` David Gibson
2017-12-21 13:09 ` Peter Maydell
0 siblings, 1 reply; 19+ messages in thread
From: David Gibson @ 2017-12-21 8:40 UTC (permalink / raw)
To: Peter Maydell; +Cc: Greg Kurz, qemu-ppc, QEMU Developers, Michael Roth
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On Thu, Dec 21, 2017 at 12:45:50AM +1100, David Gibson wrote:
> On Wed, Dec 20, 2017 at 11:29:36AM +0000, Peter Maydell wrote:
> > On 19 December 2017 at 04:29, David Gibson <david@gibson.dropbear.id.au> wrote:
> > > The following changes since commit eaefea537b476cb853e2edbdc68e969ec777e4bb:
> > >
> > > Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging (2017-12-18 14:17:42 +0000)
> > >
> > > are available in the Git repository at:
> > >
> > > git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20171219
> > >
> > > for you to fetch changes up to eec745d4366076dee068750ea80245e1a46e9c13:
> > >
> > > hw/ide: Emulate SiI3112 SATA controller (2017-12-19 15:24:28 +1100)
> > >
> > > ----------------------------------------------------------------
> > > ppc patch queue 2017-12-19
> > >
> > > Here's a second batch of patches for qemu-2.12. Highlights are:
> > >
> > > * Optional capabilities for the "pseries" machine. This removes
> > > some places where we were changing guest visible properties based
> > > on host capabilities, which makes life very bad for migration.
> > > * SLOF update
> > > * Significant TCG speedup from Paolo
> > > * Several new devices for embedded platforms
> > > * Some minor cleanups
> > >
> >
> > Migration test hangs on aarch32 host/ppc guest:
> >
> > peter.m+ 3942 0.0 0.0 1452 412 pts/0 S+ Dec19 0:00 |
> > \_ /bin/sh -c
> > QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64
> > QTEST_QEMU_IMG=qemu-img MALLOC_PERTURB_=${MALLOC_PERTURB_:-$((
> > ${RANDOM:-0} % 255 + 1))} gtester -k --verbose -m=quick
> > tests/spapr-phb-test tests/endianness-test tests/boot-order-test
> > tests/prom-env-test tests/pnv-xscom-test tests/drive_del-test
> > tests/migration-test tests/boot-serial-test tests/rtas-test
> > tests/pxe-test tests/usb-hcd-ohci-test tests/usb-hcd-uhci-test
> > tests/usb-hcd-xhci-test tests/virtio-net-test
> > tests/virtio-balloon-test tests/virtio-blk-test tests/virtio-rng-test
> > tests/virtio-scsi-test tests/virtio-9p-test tests/virtio-serial-test
> > tests/virtio-console-test tests/test-netfilter
> > tests/test-filter-mirror tests/test-filter-redirector
> > tests/display-vga-test tests/numa-test tests/ivshmem-test
> > tests/qmp-test tests/device-introspect-test tests/qom-test
> > tests/test-hmp
> > peter.m+ 3943 0.0 0.0 11984 1828 pts/0 Sl+ Dec19 0:00 |
> > \_ gtester -k --verbose -m=quick
> > tests/spapr-phb-test tests/endianness-test tests/boot-order-test
> > tests/prom-env-test tests/pnv-xscom-test tests/drive_del-test
> > tests/migration-test tests/boot-serial-test tests/rtas-test
> > tests/pxe-test tests/usb-hcd-ohci-test tests/usb-hcd-uhci-test
> > tests/usb-hcd-xhci-test tests/virtio-net-test
> > tests/virtio-balloon-test tests/virtio-blk-test tests/virtio-rng-test
> > tests/virtio-scsi-test tests/virtio-9p-test tests/virtio-serial-test
> > tests/virtio-console-test tests/test-netfilter
> > tests/test-filter-mirror tests/test-filter-redirector
> > tests/display-vga-test tests/numa-test tests/ivshmem-test
> > tests/qmp-test tests/device-introspect-test tests/qom-test
> > tests/test-hmp
> > peter.m+ 4041 99.9 0.0 3460 824 pts/0 R+ Dec19 809:16 |
> > \_ tests/migration-test --quiet
> > --keep-going -m=quick --GTestLogFD=6
> > peter.m+ 4042 99.9 0.4 607804 72924 pts/0 Sl+ Dec19 809:50 |
> > \_ ppc64-softmmu/qemu-system-ppc64
> > -qtest unix:/tmp/qtest-4041.sock,nowait -qtest-log /dev/null -qmp
> > unix:/tmp/qtest-4041.qmp,nowait -machine accel=qtest -display none
> > -machine accel=tcg -m 256M -name pcsource,debug-threads=on -serial
> > file:/tmp/migration-test-vxvkIZ/src_serial -drive
> > file=/tmp/migration-test-vxvkIZ/bootsect,if=pflash,format=raw
> > peter.m+ 4046 0.0 0.3 596596 49696 pts/0 Sl+ Dec19 0:01 |
> > \_ ppc64-softmmu/qemu-system-ppc64
> > -qtest unix:/tmp/qtest-4041.sock,nowait -qtest-log /dev/null -qmp
> > unix:/tmp/qtest-4041.qmp,nowait -machine accel=qtest -display none
> > -machine accel=tcg -m 256M -name pcdest,debug-threads=on -serial
> > file:/tmp/migration-test-vxvkIZ/dest_serial -incoming
> > unix:/tmp/migration-test-vxvkIZ/migsocket
> >
> >
> > Process 4041/4042 are using 100% CPU.
> >
> > $ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 gtester -k
> > --verbose -m=quick tests/migration-test
> > TEST: tests/migration-test... (pid=5441)
> > /ppc64/migration/postcopy/unix:
> > [hangs]
> >
> > My first guess is that this is a general 32-bit host issue
> > rather than an arm-host specific one; arm just happens to
> > be the only 32-bit system in my test set.
>
> Oh :(. I ran make check SPEED=slow in a 32-bit x86 container before
> sending the pull request, and I just retried it now, so that doesn't
> appear to be the case.
>
> I haven't the foggiest what could be broken in an arm host specific
> way, though. Nor do I have easy access to an arm system to track it
> down on.
After I sent that I remembered my Raspberry Pi. Unfortunately, after
spending most of the day getting it compiled, I wasn't able to
reproduce the problem. The migration-test completed just fine with my
ppc-for-2.12 tree.
I'm not sure where to go from here, I don't even have a guess as to
which patch in the series might be causing the problem, since none of
them seem likely candidates.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219
2017-12-21 8:40 ` David Gibson
@ 2017-12-21 13:09 ` Peter Maydell
0 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2017-12-21 13:09 UTC (permalink / raw)
To: David Gibson; +Cc: Greg Kurz, qemu-ppc, QEMU Developers, Michael Roth
On 21 December 2017 at 08:40, David Gibson <david@gibson.dropbear.id.au> wrote:
> On Thu, Dec 21, 2017 at 12:45:50AM +1100, David Gibson wrote:
>> Oh :(. I ran make check SPEED=slow in a 32-bit x86 container before
>> sending the pull request, and I just retried it now, so that doesn't
>> appear to be the case.
>>
>> I haven't the foggiest what could be broken in an arm host specific
>> way, though. Nor do I have easy access to an arm system to track it
>> down on.
>
> After I sent that I remembered my Raspberry Pi. Unfortunately, after
> spending most of the day getting it compiled, I wasn't able to
> reproduce the problem. The migration-test completed just fine with my
> ppc-for-2.12 tree.
>
> I'm not sure where to go from here, I don't even have a guess as to
> which patch in the series might be causing the problem, since none of
> them seem likely candidates.
I can have another look with the setup that failed, but that won't be
until the new year, I'm afraid.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2017-12-21 13:09 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-12-19 4:29 [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 01/14] target-ppc: optimize cmp translation David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 02/14] pseries: Update SLOF firmware image to qemu-slof-20171214 David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 03/14] sm501: Add panel hardware cursor registers also to read function David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 04/14] sm501: Add some more unimplemented registers David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 05/14] ppc4xx_i2c: Implement basic I2C functions David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 06/14] ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 07/14] spapr: Capabilities infrastructure David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 08/14] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 09/14] spapr: Validate capabilities on migration David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 10/14] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 11/14] spapr: Handle VMX/VSX presence as an spapr capability flag David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 12/14] spapr: Handle Decimal Floating Point (DFP) as an optional capability David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 13/14] spapr_pci: use warn_report() David Gibson
2017-12-19 4:29 ` [Qemu-devel] [PULL 14/14] hw/ide: Emulate SiI3112 SATA controller David Gibson
2017-12-20 11:29 ` [Qemu-devel] [PULL 00/14] ppc-for-2.12 queue 20171219 Peter Maydell
2017-12-20 13:45 ` David Gibson
2017-12-21 8:40 ` David Gibson
2017-12-21 13:09 ` Peter Maydell
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