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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [Qemu-devel] [PATCH 11/38] target/hppa: Implement rfi
Date: Thu, 28 Dec 2017 22:31:18 -0800	[thread overview]
Message-ID: <20171229063145.29167-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/cpu.h       |  1 +
 target/hppa/helper.h    |  2 ++
 target/hppa/op_helper.c | 24 ++++++++++++++++++++++++
 target/hppa/translate.c | 31 +++++++++++++++++++++++++++++--
 4 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index c92c564a7f..6ec3430ae3 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -178,6 +178,7 @@ struct CPUHPPAState {
 
     target_ureg cr[32];      /* control registers */
     target_ureg cr_back[2];  /* back of cr17/cr18 */
+    target_ureg shadow[7];   /* shadow registers */
 
     /* Those resources are used only in QEMU core */
     CPU_COMMON
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 254a4da133..79d22ae486 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -78,5 +78,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
 DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
 
 #ifndef CONFIG_USER_ONLY
+DEF_HELPER_1(rfi, void, env)
+DEF_HELPER_1(rfi_r, void, env)
 DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr)
 #endif
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 1c3e043cc0..3f5dcbbca0 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -614,4 +614,28 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
     env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM);
     return psw & PSW_SM;
 }
+
+void HELPER(rfi)(CPUHPPAState *env)
+{
+    /* ??? On second reading this condition simply seems
+       to be undefined rather than a diagnosed trap.  */
+    if (env->psw & (PSW_I | PSW_R | PSW_Q)) {
+        helper_excp(env, EXCP_ILL);
+    }
+    env->iaoq_f = env->cr[CR_IIAOQ];
+    env->iaoq_b = env->cr_back[1];
+    cpu_hppa_put_psw(env, env->cr[CR_IPSW]);
+}
+
+void HELPER(rfi_r)(CPUHPPAState *env)
+{
+    env->gr[1] = env->shadow[0];
+    env->gr[8] = env->shadow[1];
+    env->gr[9] = env->shadow[2];
+    env->gr[16] = env->shadow[3];
+    env->gr[17] = env->shadow[4];
+    env->gr[24] = env->shadow[5];
+    env->gr[25] = env->shadow[6];
+    helper_rfi(env);
+}
 #endif
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 2a61b6bc8d..8078d3cd46 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -652,6 +652,11 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status)
 {
     TCGLabel *null_lab = ctx->null_lab;
 
+    /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
+       For UPDATED, we cannot update on the nullified path.  */
+    assert(status != DISAS_IAQ_N_UPDATED &&
+           status != DISAS_IAQ_N_UPDATED_EXIT);
+
     if (likely(null_lab == NULL)) {
         /* The current insn wasn't conditional or handled the condition
            applied to it without a branch, so the (new) setting of
@@ -673,8 +678,6 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status)
         gen_set_label(null_lab);
         ctx->null_cond = cond_make_n();
     }
-
-    assert(status != DISAS_NORETURN && status != DISAS_IAQ_N_UPDATED);
     if (status == DISAS_NORETURN) {
         status = DISAS_NEXT;
     }
@@ -2143,6 +2146,29 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn,
     /* Exit the TB to recognize new interrupts.  */
     return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT);
 }
+
+static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn,
+                               const DisasInsn *di)
+{
+    unsigned comp = extract32(insn, 5, 4);
+
+    CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
+    nullify_over(ctx);
+
+    if (comp == 5) {
+        gen_helper_rfi_r(cpu_env);
+    } else {
+        gen_helper_rfi(cpu_env);
+    }
+    if (ctx->base.singlestep_enabled) {
+        gen_excp_1(EXCP_DEBUG);
+    } else {
+        tcg_gen_exit_tb(0);
+    }
+
+    /* Exit the TB to recognize new interrupts.  */
+    return nullify_end(ctx, DISAS_NORETURN);
+}
 #endif /* !CONFIG_USER_ONLY */
 
 static const DisasInsn table_system[] = {
@@ -2159,6 +2185,7 @@ static const DisasInsn table_system[] = {
     { 0x00000e60u, 0xfc00ffe0u, trans_rsm },
     { 0x00000d60u, 0xfc00ffe0u, trans_ssm },
     { 0x00001860u, 0xffe0ffffu, trans_mtsm },
+    { 0x00000c00u, 0xfffffe1fu, trans_rfi },
 #endif
 };
 
-- 
2.14.3

  parent reply	other threads:[~2017-12-29  6:32 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-29  6:31 [Qemu-devel] [PATCH 00/38] Add hppa-softmmu Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 01/38] target/hppa: Skeleton support for hppa-softmmu Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 02/38] target/hppa: Define the rest of the PSW Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 03/38] target/hppa: Disable gateway page emulation for system mode Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 04/38] target/hppa: Define hardware exception types Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 05/38] target/hppa: Split address size from register size Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 06/38] target/hppa: Implement mmu_idx from IA privilege level Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 07/38] target/hppa: Implement the system mask instructions Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 08/38] target/hppa: Add space registers Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 09/38] target/hppa: Add control registers Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 10/38] target/hppa: Adjust insn mask for mfctl, w Richard Henderson
2017-12-29  6:31 ` Richard Henderson [this message]
2017-12-29  6:31 ` [Qemu-devel] [PATCH 12/38] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 13/38] target/hppa: Implement unaligned access trap Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 14/38] target/hppa: Use space registers in data operations Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 15/38] target/hppa: Do not set cs_base to iaoq_b Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 16/38] target/hppa: Avoid privilege level decrease during branches Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 17/38] target/hppa: Implement IASQ Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 18/38] target/hppa: Implement tlb_fill Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 19/38] target/hppa: Implement external interrupts Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 20/38] target/hppa: Implement the interval timer Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 21/38] target/hppa: Log unimplemented instructions Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 22/38] target/hppa: Implement I*TLBA and I*TLBP insns Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 23/38] target/hppa: Implement P*TLB and P*TLBE insns Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 24/38] target/hppa: Implement LDWA Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 25/38] target/hppa: Implement LPA Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 26/38] target/hppa: Implement LCI Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 27/38] target/hppa: Implement SYNCDMA insn Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 28/38] target/hppa: Implement a halt instruction Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 29/38] hw/hppa: Implement DINO system board Richard Henderson
2017-12-29  9:45   ` Igor Mammedov
2017-12-29  6:31 ` [Qemu-devel] [PATCH 30/38] target/hppa: Optimize for flat addressing space Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 31/38] target/hppa: Add system registers to gdbstub Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 32/38] target/hppa: Add migration for the cpu Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 33/38] target/hppa: Implement B,GATE insn Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 34/38] target/hppa: Only use EXCP_DTLB_MISS Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 35/38] qom: Add MMU_DEBUG_LOAD Richard Henderson
2017-12-29 16:18   ` Andreas Färber
2017-12-29  6:31 ` [Qemu-devel] [PATCH 36/38] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 37/38] target/hppa: Increase number of temp regs Richard Henderson
2017-12-29  6:31 ` [Qemu-devel] [PATCH 38/38] target/hppa: Fix comment Richard Henderson

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