From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [Qemu-devel] [PATCH 28/38] target/hppa: Implement a halt instruction
Date: Thu, 28 Dec 2017 22:31:35 -0800 [thread overview]
Message-ID: <20171229063145.29167-29-richard.henderson@linaro.org> (raw)
In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org>
Real hardware would use an external device to control the power.
But for the moment let's invent an instruction in reserved space.
Suggested-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 1 +
target/hppa/op_helper.c | 7 +++++++
target/hppa/translate.c | 18 +++++++++++++++++-
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 1e733b7926..6e86c596fe 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -80,6 +80,7 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr)
#ifndef CONFIG_USER_ONLY
+DEF_HELPER_1(shutdown, noreturn, env)
DEF_HELPER_1(rfi, void, env)
DEF_HELPER_1(rfi_r, void, env)
DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr)
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index d270f94e31..88be2ebf24 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -22,6 +22,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
+#include "sysemu/sysemu.h"
#include "qemu/timer.h"
@@ -639,6 +640,12 @@ void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val)
timer_mod(cpu->alarm_timer, timeout);
}
+void HELPER(shutdown)(CPUHPPAState *env)
+{
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+ helper_excp(env, EXCP_HLT);
+}
+
target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
{
target_ulong psw = env->psw;
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 00a8c26afa..68f0b86c72 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2293,6 +2293,14 @@ static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn,
/* Exit the TB to recognize new interrupts. */
return nullify_end(ctx, DISAS_NORETURN);
}
+
+static DisasJumpType gen_hlt(DisasContext *ctx)
+{
+ CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
+ nullify_over(ctx);
+ gen_helper_shutdown(cpu_env);
+ return nullify_end(ctx, DISAS_NORETURN);
+}
#endif /* !CONFIG_USER_ONLY */
static const DisasInsn table_system[] = {
@@ -4510,7 +4518,15 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x15: /* unassigned */
case 0x1D: /* unassigned */
case 0x37: /* unassigned */
- case 0x3F: /* unassigned */
+ break;
+ case 0x3F:
+#ifndef CONFIG_USER_ONLY
+ /* Unassigned, but use as system-halt. */
+ if (insn == 0xffffffff) {
+ return gen_hlt(ctx);
+ }
+#endif
+ break;
default:
break;
}
--
2.14.3
next prev parent reply other threads:[~2017-12-29 6:32 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-29 6:31 [Qemu-devel] [PATCH 00/38] Add hppa-softmmu Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 01/38] target/hppa: Skeleton support for hppa-softmmu Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 02/38] target/hppa: Define the rest of the PSW Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 03/38] target/hppa: Disable gateway page emulation for system mode Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 04/38] target/hppa: Define hardware exception types Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 05/38] target/hppa: Split address size from register size Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 06/38] target/hppa: Implement mmu_idx from IA privilege level Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 07/38] target/hppa: Implement the system mask instructions Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 08/38] target/hppa: Add space registers Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 09/38] target/hppa: Add control registers Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 10/38] target/hppa: Adjust insn mask for mfctl, w Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 11/38] target/hppa: Implement rfi Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 12/38] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 13/38] target/hppa: Implement unaligned access trap Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 14/38] target/hppa: Use space registers in data operations Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 15/38] target/hppa: Do not set cs_base to iaoq_b Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 16/38] target/hppa: Avoid privilege level decrease during branches Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 17/38] target/hppa: Implement IASQ Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 18/38] target/hppa: Implement tlb_fill Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 19/38] target/hppa: Implement external interrupts Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 20/38] target/hppa: Implement the interval timer Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 21/38] target/hppa: Log unimplemented instructions Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 22/38] target/hppa: Implement I*TLBA and I*TLBP insns Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 23/38] target/hppa: Implement P*TLB and P*TLBE insns Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 24/38] target/hppa: Implement LDWA Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 25/38] target/hppa: Implement LPA Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 26/38] target/hppa: Implement LCI Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 27/38] target/hppa: Implement SYNCDMA insn Richard Henderson
2017-12-29 6:31 ` Richard Henderson [this message]
2017-12-29 6:31 ` [Qemu-devel] [PATCH 29/38] hw/hppa: Implement DINO system board Richard Henderson
2017-12-29 9:45 ` Igor Mammedov
2017-12-29 6:31 ` [Qemu-devel] [PATCH 30/38] target/hppa: Optimize for flat addressing space Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 31/38] target/hppa: Add system registers to gdbstub Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 32/38] target/hppa: Add migration for the cpu Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 33/38] target/hppa: Implement B,GATE insn Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 34/38] target/hppa: Only use EXCP_DTLB_MISS Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 35/38] qom: Add MMU_DEBUG_LOAD Richard Henderson
2017-12-29 16:18 ` Andreas Färber
2017-12-29 6:31 ` [Qemu-devel] [PATCH 36/38] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 37/38] target/hppa: Increase number of temp regs Richard Henderson
2017-12-29 6:31 ` [Qemu-devel] [PATCH 38/38] target/hppa: Fix comment Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171229063145.29167-29-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=deller@gmx.de \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).