From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57573) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUyoI-0003rr-Eg for qemu-devel@nongnu.org; Fri, 29 Dec 2017 12:51:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eUyoF-0007QI-DF for qemu-devel@nongnu.org; Fri, 29 Dec 2017 12:51:10 -0500 Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 29 Dec 2017 14:49:18 -0300 Message-Id: <20171229174933.1781-28-f4bug@amsat.org> In-Reply-To: <20171229174933.1781-1-f4bug@amsat.org> References: <20171229174933.1781-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 27/42] hw/arm/exynos4210: implement SDHCI Spec v2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell , Igor Mitsyanko , Krzysztof Kozlowski , Andrey Smirnov Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Crosthwaite Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index e8e1d81e62..0e6acac784 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -75,7 +75,6 @@ #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 /* SD/MMC host controllers */ -#define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 0x00010000 * (n)) @@ -377,8 +376,18 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) BlockBackend *blk; DriveInfo *di; + /* Compatible with: + * - SD Host Controller Specification Version 2.0 + * - SDIO Specification Version 2.0 + * - MMC Specification Version 4.3 + * + * - SDMA + * - ADMA + */ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); - qdev_prop_set_uint32(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); + qdev_prop_set_uint8(dev, "sd-spec-version", 2); + qdev_prop_set_bit(dev, "suspend", true); + qdev_prop_set_bit(dev, "1v8", true); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); -- 2.15.1