[Qemu-devel] [PATCH v3 02/42] sdhci: sort registers comments

["Philippe Mathieu-Daudé" <f4bug@amsat.org>]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/sd/sdhci.h | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 1335373d3c..749cc279ed 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -49,14 +49,20 @@ typedef struct SDHCIState {
     qemu_irq irq;
 
     /* Registers cleared on reset */
+    /* 0x00 */
     uint32_t sdmasysad;    /* SDMA System Address register */
     uint16_t blksize;      /* Host DMA Buff Boundary and Transfer BlkSize Reg */
     uint16_t blkcnt;       /* Blocks count for current transfer */
+    /* 0x08 */
     uint32_t argument;     /* Command Argument Register */
     uint16_t trnmod;       /* Transfer Mode Setting Register */
     uint16_t cmdreg;       /* Command Register */
+    /* 0x10 */
     uint32_t rspreg[4];    /* Response Registers 0-3 */
+    /* 0x20 */
+    /* Buffer Data Port Register - virtual access point to R and W buffers */
     uint32_t prnsts;       /* Present State Register */
+    /* 0x28 */
     uint8_t  hostctl;      /* Host Control Register */
     uint8_t  pwrcon;       /* Power control Register */
     uint8_t  blkgap;       /* Block Gap Control Register */
@@ -64,6 +70,7 @@ typedef struct SDHCIState {
     uint16_t clkcon;       /* Clock control Register */
     uint8_t  timeoutcon;   /* Timeout Control Register */
     uint8_t  admaerr;      /* ADMA Error Status Register */
+    /* 0x30 */
     uint16_t norintsts;    /* Normal Interrupt Status Register */
     uint16_t errintsts;    /* Error Interrupt Status Register */
     uint16_t norintstsen;  /* Normal Interrupt Status Enable Register */
@@ -71,23 +78,25 @@ typedef struct SDHCIState {
     uint16_t norintsigen;  /* Normal Interrupt Signal Enable Register */
     uint16_t errintsigen;  /* Error Interrupt Signal Enable Register */
     uint16_t acmd12errsts; /* Auto CMD12 error status register */
+    /* 0x50 */
+    /* Force Event Auto CMD12 Error Interrupt Reg - write only */
+    /* Force Event Error Interrupt Register- write only */
+    /* 0x58 */
     uint64_t admasysaddr;  /* ADMA System Address Register */
 
     /* Read-only registers */
+    /* 0x40 */
     uint32_t capareg;      /* Capabilities Register */
+    /* 0x48 */
     uint32_t maxcurr;      /* Maximum Current Capabilities Register */
 
     uint8_t  *fifo_buffer; /* SD host i/o FIFO buffer */
     uint32_t buf_maxsz;
     uint16_t data_count;   /* current element in FIFO buffer */
     uint8_t  stopped_state;/* Current SDHC state */
-    bool     pending_insert_quirk;/* Quirk for Raspberry Pi card insert int */
     bool     pending_insert_state;
-    /* Buffer Data Port Register - virtual access point to R and W buffers */
-    /* Software Reset Register - always reads as 0 */
-    /* Force Event Auto CMD12 Error Interrupt Reg - write only */
-    /* Force Event Error Interrupt Register- write only */
-    /* RO Host Controller Version Register always reads as 0x2401 */
+    /* Configurable properties */
+    bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
 } SDHCIState;
 
 #define TYPE_PCI_SDHCI "sdhci-pci"
-- 
2.15.1