From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eWgnq-0002wb-RJ for qemu-devel@nongnu.org; Wed, 03 Jan 2018 06:01:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eWgnq-0005n3-1Q for qemu-devel@nongnu.org; Wed, 03 Jan 2018 06:01:46 -0500 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:43206) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eWgnp-0005mw-TT for qemu-devel@nongnu.org; Wed, 03 Jan 2018 06:01:45 -0500 Received: by mail-qk0-x244.google.com with SMTP id j137so1056071qke.10 for ; Wed, 03 Jan 2018 03:01:45 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 3 Jan 2018 08:01:13 -0300 Message-Id: <20180103110126.29209-5-f4bug@amsat.org> In-Reply-To: <20180103110126.29209-1-f4bug@amsat.org> References: <20180103110126.29209-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v4 04/17] sdhci: refactor same sysbus/pci properties into a common one List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis , Fam Zheng Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, "Edgar E . Iglesias" , Peter Maydell , Andrey Smirnov , Eduardo Habkost Now both sysbus/pci classes inherit of the 'pending-insert-quirk' property, which is a HCI dependent property (regardless if accessed through a MMIO sysbus or a PCI bus). So far only the BCM implementation has to use it. Add sysbus/pci/sdbus comments to have clearer code blocks separation. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 365bc80009..a11469fbca 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1266,13 +1266,17 @@ const VMStateDescription sdhci_vmstate = { /* Capabilities registers provide information on supported features of this * specific host controller implementation */ -static Property sdhci_pci_properties[] = { +static Property sdhci_properties[] = { DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, SDHC_CAPAB_REG_DEFAULT), DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), + DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, + false), DEFINE_PROP_END_OF_LIST(), }; +/* --- qdev PCI --- */ + static void sdhci_pci_realize(PCIDevice *dev, Error **errp) { SDHCIState *s = PCI_SDHCI(dev); @@ -1305,7 +1309,7 @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_SYSTEM_SDHCI; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->vmsd = &sdhci_vmstate; - dc->props = sdhci_pci_properties; + dc->props = sdhci_properties; dc->reset = sdhci_poweron_reset; } @@ -1320,14 +1324,7 @@ static const TypeInfo sdhci_pci_info = { }, }; -static Property sdhci_sysbus_properties[] = { - DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, - SDHC_CAPAB_REG_DEFAULT), - DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), - DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, - false), - DEFINE_PROP_END_OF_LIST(), -}; +/* --- qdev SysBus --- */ static void sdhci_sysbus_init(Object *obj) { @@ -1360,7 +1357,7 @@ static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &sdhci_vmstate; - dc->props = sdhci_sysbus_properties; + dc->props = sdhci_properties; dc->realize = sdhci_sysbus_realize; dc->reset = sdhci_poweron_reset; } @@ -1374,6 +1371,8 @@ static const TypeInfo sdhci_sysbus_info = { .class_init = sdhci_sysbus_class_init, }; +/* --- qdev bus master --- */ + static void sdhci_bus_class_init(ObjectClass *klass, void *data) { SDBusClass *sbc = SD_BUS_CLASS(klass); -- 2.15.1