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Date: Mon, 8 Jan 2018 15:28:50 +0100
From: Christoph Hellwig <hch@lst.de>
Message-ID: <20180108142850.GB10273@lst.de>
References: <1514940265-18093-1-git-send-email-mjc@sifive.com>
	<1514940265-18093-6-git-send-email-mjc@sifive.com>
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In-Reply-To: <1514940265-18093-6-git-send-email-mjc@sifive.com>
Subject: Re: [Qemu-devel] [PATCH v1 05/21] RISC-V CPU Helpers
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To: Michael Clark <mjc@sifive.com>
Cc: qemu-devel@nongnu.org, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>

> +    if (env->priv_ver >= PRIV_VERSION_1_10_0) {
> +        if (get_field(env->satp, SATP_MODE) == VM_1_09_MBARE) {
> +            mode = PRV_M;
> +        }
> +    } else {
> +        if (get_field(env->mstatus, MSTATUS_VM) == VM_1_10_MBARE) {
> +            mode = PRV_M;
> +        }
> +    }

This mixes up VM_1_09_MBARE and VM_1_10_MBARE, but they evaluate to
the same value anyway.

And as Richard said just rely on the mmu_idx from cpu_mmu_index.  I
actually already did the change to remove it in a patch for a new riscv
CSR I developed and can thus confirm it works fine.

> +    case CSR_SPTBR:

This should use CSR_SATP.  In fact even if you want to keep 1.9.1 support
I would highly recommend to remove the CSR_SPTBR define and only use
CSR_SATP in code, with sptbr limited to comments to avoid confusion.