qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Alistair Francis <alistair.francis@xilinx.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Andrey Smirnov <andrew.smirnov@gmail.com>,
	Igor Mitsyanko <i.mitsyanko@gmail.com>
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-devel@nongnu.org,
	"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
	"Sai Pavan Boddu" <saipava@xilinx.com>,
	"Clement Deschamps" <clement.deschamps@antfield.fr>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>,
	"Grégory Estrade" <gregory.estrade@gmail.com>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	"Andrew Baumann" <Andrew.Baumann@microsoft.com>,
	"Prasad J Pandit" <pjp@fedoraproject.org>,
	qemu-arm@nongnu.org, "Eduardo Habkost" <ehabkost@redhat.com>,
	"Peter Crosthwaite" <crosthwaite.peter@gmail.com>
Subject: [Qemu-devel] [PATCH v5 03/31] sdhci: add max-block-length capability (Spec v1)
Date: Mon,  8 Jan 2018 12:42:35 -0300	[thread overview]
Message-ID: <20180108154303.6522-4-f4bug@amsat.org> (raw)
In-Reply-To: <20180108154303.6522-1-f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/sd/sdhci-internal.h |  1 -
 include/hw/sd/sdhci.h  |  1 +
 hw/sd/sdhci.c          | 38 +++++++++++++-------------------------
 3 files changed, 14 insertions(+), 26 deletions(-)

diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 6944fcaf00..0561e6eaf7 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -188,7 +188,6 @@ FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR,    4, 1);
 #define SDHC_CAN_DO_ADMA2              0x00080000
 #define SDHC_CAN_DO_ADMA1              0x00100000
 #define SDHC_64_BIT_BUS_SUPPORT        (1 << 28)
-#define SDHC_CAPAB_BLOCKSIZE(x)        (((x) >> 16) & 0x3)
 FIELD(SDHC_CAPAB, TOCLKFREQ,           0, 6);
 FIELD(SDHC_CAPAB, TOUNIT,              7, 1);
 FIELD(SDHC_CAPAB, BASECLKFREQ,         8, 8);
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 266030dc8d..2703da1d5a 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -103,6 +103,7 @@ typedef struct SDHCIState {
     bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
     uint8_t spec_version;
     struct {
+        uint16_t max_blk_len;
         bool suspend;
         bool high_speed;
         bool sdma;
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index e7dbab2fdc..c78643fe54 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -46,9 +46,6 @@
 #define SDHC_CAPAB_64BITBUS       0ul        /* 64-bit System Bus Support */
 #define SDHC_CAPAB_ADMA1          1ul        /* ADMA1 support */
 #define SDHC_CAPAB_ADMA2          1ul        /* ADMA2 support */
-/* Maximum host controller R/W buffers size
- * Possible values: 512, 1024, 2048 bytes */
-#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
 /* Maximum clock frequency for SDclock in MHz
  * value in range 10-63 MHz, 0 - not defined */
 #define SDHC_CAPAB_BASECLKFREQ    52ul
@@ -62,16 +59,6 @@
 #error Capabilities features can have value 0 or 1 only!
 #endif
 
-#if SDHC_CAPAB_MAXBLOCKLENGTH == 512
-#define MAX_BLOCK_LENGTH 0ul
-#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
-#define MAX_BLOCK_LENGTH 1ul
-#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
-#define MAX_BLOCK_LENGTH 2ul
-#else
-#error Max host controller block size can have value 512, 1024 or 2048 only!
-#endif
-
 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
     SDHC_CAPAB_BASECLKFREQ > 63
 #error SDclock frequency can have value in range 0, 10-63 only!
@@ -83,7 +70,7 @@
 
 #define SDHC_CAPAB_REG_DEFAULT                                 \
    ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_ADMA1 << 20) |   \
-    (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) |      \
+    (SDHC_CAPAB_ADMA2 << 19) |                                 \
     (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
     (SDHC_CAPAB_TOCLKFREQ))
 
@@ -92,9 +79,17 @@
 static void sdhci_init_capareg(SDHCIState *s, Error **errp)
 {
     uint64_t capareg = 0;
+    uint32_t val;
 
     switch (s->spec_version) {
     case 1:
+        val = ctz32(s->cap.max_blk_len >> 9);
+        if (val >= 0b11) {
+            error_setg(errp, "block size can be 512, 1024 or 2048 only");
+            return;
+        }
+        capareg = FIELD_DP64(capareg, SDHC_CAPAB, MAXBLOCKLENGTH, val);
+
         capareg = FIELD_DP64(capareg, SDHC_CAPAB, HIGHSPEED, s->cap.high_speed);
         capareg = FIELD_DP64(capareg, SDHC_CAPAB, SDMA, s->cap.sdma);
         capareg = FIELD_DP64(capareg, SDHC_CAPAB, SUSPRESUME, s->cap.suspend);
@@ -1175,17 +1170,7 @@ static const MemoryRegionOps sdhci_mmio_ops = {
 
 static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
 {
-    switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) {
-    case 0:
-        return 512;
-    case 1:
-        return 1024;
-    case 2:
-        return 2048;
-    default:
-        hw_error("SDHC: unsupported value for maximum block size\n");
-        return 0;
-    }
+    return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH));
 }
 
 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
@@ -1319,6 +1304,9 @@ const VMStateDescription sdhci_vmstate = {
 static Property sdhci_properties[] = {
     DEFINE_PROP_UINT8("sd-spec-version", SDHCIState, spec_version, 2),
 
+    /* Maximum host controller R/W buffers size
+     * Possible values: 512, 1024, 2048 bytes */
+    DEFINE_PROP_UINT16("max-block-length", SDHCIState, cap.max_blk_len, 512),
     /* DMA */
     DEFINE_PROP_BOOL("sdma", SDHCIState, cap.sdma, true),
     /* Suspend/resume support */
-- 
2.15.1

  parent reply	other threads:[~2018-01-08 15:43 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-08 15:42 [Qemu-devel] [PATCH v5 00/31] SDHCI: make it abstract, add inherited devices, add qtests Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 01/31] sdhci: add a spec_version property Philippe Mathieu-Daudé
2018-01-08 21:41   ` Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 02/31] sdhci: add basic Spec v1 capabilities Philippe Mathieu-Daudé
2018-01-08 22:00   ` Alistair Francis
2018-01-08 22:33     ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-01-08 15:42 ` Philippe Mathieu-Daudé [this message]
2018-01-08 22:20   ` [Qemu-devel] [PATCH v5 03/31] sdhci: add max-block-length capability (Spec v1) Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 04/31] sdhci: add clock capabilities " Philippe Mathieu-Daudé
2018-01-08 22:22   ` Alistair Francis
2018-01-08 22:35     ` Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 05/31] sdhci: add DMA and 64-bit capabilities (Spec v2) Philippe Mathieu-Daudé
2018-01-09 21:53   ` Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 07/31] sdhci: Fix 64-bit ADMA2 Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 08/31] hw/sd: clean/reorder the Makefile adding few comments Philippe Mathieu-Daudé
2018-01-08 21:53   ` Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 09/31] sdhci: add a common class Philippe Mathieu-Daudé
2018-01-09 21:54   ` Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 10/31] sdhci: add a Designware/Samsung host controller Philippe Mathieu-Daudé
2018-01-09 23:14   ` Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 11/31] hw/arm/exynos4210: use the "samsung, exynos4210-dw-mshc" device Philippe Mathieu-Daudé
2018-01-09 23:18   ` Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 12/31] sdhci: add the generic Arasan SDHCI 4.9a PHY controller Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 13/31] hw/arm/xilinx_zynq: use the "arasan, sdhci-4.9a" device Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 14/31] sdhci: add qtest to check the SD Spec version Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 15/31] sdhci: check Spec v2 capabilities qtest Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 16/31] sdhci: add v3 capabilities Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 17/31] sdhci: rename the hostctl1 register Philippe Mathieu-Daudé
2018-01-08 21:54   ` Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 18/31] sdhci: add the Broadcom BCM2835 SDHCI controller Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 19/31] hw/arm/bcm2835_peripherals: use the "brcm, bcm2835-sdhci" device Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 20/31] sdhci: add the Freescale controller for i.MX Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 21/31] hw/arm/fsl-imx6: use the "fsl, imx6q-usdhc" controller Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 22/31] sdhci: add the generic Arasan SDHCI 8.9a PHY Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 23/31] hw/arm/xilinx_zynqmp: use the "arasan, sdhci-8.9a" device Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 24/31] sdhci: let the SYSBUS_SDHCI type be abstract Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 25/31] sdhci: check Spec v3 capabilities qtest Philippe Mathieu-Daudé
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 26/31] sdhci: remove the deprecated 'capareg' property Philippe Mathieu-Daudé
2018-01-09 22:00   ` Alistair Francis
2018-01-08 15:42 ` [Qemu-devel] [PATCH v5 27/31] sdhci: add check_capab_readonly() qtest Philippe Mathieu-Daudé
2018-01-08 15:43 ` [Qemu-devel] [PATCH v5 28/31] sdhci: add a check_capab_baseclock() qtest Philippe Mathieu-Daudé
2018-01-08 15:43 ` [Qemu-devel] [PATCH v5 29/31] sdhci: add a check_capab_sdma() qtest Philippe Mathieu-Daudé
2018-01-08 15:43 ` [Qemu-devel] [PATCH v5 30/31] sdhci: add a check_capab_v3() qtest Philippe Mathieu-Daudé
2018-01-08 15:43 ` [Qemu-devel] [PATCH v5 31/31] sdhci: add Spec v4.2 register definitions Philippe Mathieu-Daudé
2018-01-18 18:21   ` Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180108154303.6522-4-f4bug@amsat.org \
    --to=f4bug@amsat.org \
    --cc=Andrew.Baumann@microsoft.com \
    --cc=alistair.francis@xilinx.com \
    --cc=andrew.smirnov@gmail.com \
    --cc=clement.deschamps@antfield.fr \
    --cc=crosthwaite.peter@gmail.com \
    --cc=edgar.iglesias@xilinx.com \
    --cc=ehabkost@redhat.com \
    --cc=gregory.estrade@gmail.com \
    --cc=i.mitsyanko@gmail.com \
    --cc=jcd@tribudubois.net \
    --cc=krzk@kernel.org \
    --cc=peter.maydell@linaro.org \
    --cc=pjp@fedoraproject.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=saipava@xilinx.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).