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From: Eduardo Habkost <ehabkost@redhat.com>
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2)
Date: Mon, 15 Jan 2018 10:27:13 -0200	[thread overview]
Message-ID: <20180115122713.GL6646@localhost.localdomain> (raw)
In-Reply-To: <20180109154519.25634-1-ehabkost@redhat.com>

On Tue, Jan 09, 2018 at 01:45:12PM -0200, Eduardo Habkost wrote:
> This series adds support for the new IA32_SPEC_CTRL MSR on Intel
> CPU models.  The new MSR and the spec-ctrl CPUID bit
> (CPUID[EAX=7,ECX=0].EDX[bit 26]) were introduced by a recent
> Intel microcode updated and can be used by OSes to mitigate
> CVE-2017-5715.
> 
> It also adds a new EPYC-IBPB CPU model that includes
> CPUID[0x80000008].EBX[bit 12] (IBPB).  That patch is a RFC
> because I couldn't find any detailed info on the new CPUID bit
> and the IA32_PRED_CMD MSR.
> 
> Additionally, the last patch on this series changes the new
> Westmere-IBRS, SandyBridge-IBRS and IvyBridge-IBRS to include the
> PCID feature, because PCID helps to reduce the performance impact
> of KPTI on the guest.  The patch is also a RFC because we need to
> confirm if all Westmere (and newer) CPUs out there have PCID
> available.
> 
> References:
> * https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
> * Google Security Blog on Meltdown/Spectre mitigations:
>   https://security.googleblog.com/2018/01/more-details-about-mitigations-for-cpu_4.html
> * Kernel patches to make use of the new MSRs:
>   https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1578798.html
> * KVM kernel patches for the new CPUID bits and MSRs:
>   https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1580363.html
> * Patches adding PCID to the existing CPU models:
>   https://patchew.org/QEMU/20180108205052.24385-1-vincent@bernat.im
>   https://patchew.org/QEMU/20180109070112.30806-1-vincent@bernat.im

Intel docs for the new CPUID flags and MSRs were finally
published:
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf

-- 
Eduardo

      parent reply	other threads:[~2018-01-15 12:27 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-09 15:45 [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2) Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 1/7] i386: Change X86CPUDefinition::model_id to const char* Eduardo Habkost
2018-01-09 17:47   ` [Qemu-devel] [PATCH] fixup! " Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 2/7] i386: Add support for SPEC_CTRL MSR Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit Eduardo Habkost
2018-01-13  3:04   ` Gonglei (Arei)
2018-01-15 12:23     ` Eduardo Habkost
2018-01-16 14:50       ` Gonglei (Arei)
2018-01-09 15:45 ` [Qemu-devel] [PATCH 4/7] i386: Add FEAT_8000_0008_EBX CPUID feature word Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 5/7] i386: Add new -IBRS versions of Intel CPU models Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 6/7] [RFC] i386: Add EPYC-IBPB CPU model Eduardo Habkost
2018-01-09 15:45 ` [Qemu-devel] [PATCH 7/7] [RFC] i386: Add PCID to {Westmere, SandyBridge, IvyBridge}-IBRS Eduardo Habkost
2018-01-09 16:01 ` [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2) no-reply
2018-01-12 19:50 ` Eduardo Habkost
2018-01-15 12:27 ` Eduardo Habkost [this message]

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