* [Qemu-devel] [PATCH v9 01/26] tcg: Allow multiple word entries into the constant pool
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 02/26] tcg: Add types and basic operations for host vectors Richard Henderson
` (27 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
This will be required for storing vector constants.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-pool.inc.c | 115 +++++++++++++++++++++++++++++++++++++++++++----------
1 file changed, 93 insertions(+), 22 deletions(-)
diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c
index 8a85131405..0f76e7bee3 100644
--- a/tcg/tcg-pool.inc.c
+++ b/tcg/tcg-pool.inc.c
@@ -22,39 +22,110 @@
typedef struct TCGLabelPoolData {
struct TCGLabelPoolData *next;
- tcg_target_ulong data;
tcg_insn_unit *label;
- intptr_t addend;
- int type;
+ int addend : 32;
+ int rtype : 16;
+ int nlong : 16;
+ tcg_target_ulong data[];
} TCGLabelPoolData;
-static void new_pool_label(TCGContext *s, tcg_target_ulong data, int type,
- tcg_insn_unit *label, intptr_t addend)
+static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype,
+ tcg_insn_unit *label, int addend)
{
- TCGLabelPoolData *n = tcg_malloc(sizeof(*n));
- TCGLabelPoolData *i, **pp;
+ TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData)
+ + sizeof(tcg_target_ulong) * nlong);
- n->data = data;
n->label = label;
- n->type = type;
n->addend = addend;
+ n->rtype = rtype;
+ n->nlong = nlong;
+ return n;
+}
+
+static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n)
+{
+ TCGLabelPoolData *i, **pp;
+ int nlong = n->nlong;
/* Insertion sort on the pool. */
- for (pp = &s->pool_labels; (i = *pp) && i->data < data; pp = &i->next) {
- continue;
+ for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) {
+ if (nlong > i->nlong) {
+ break;
+ }
+ if (nlong < i->nlong) {
+ continue;
+ }
+ if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) {
+ break;
+ }
}
n->next = *pp;
*pp = n;
}
+/* The "usual" for generic integer code. */
+static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype,
+ tcg_insn_unit *label, int addend)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend);
+ n->data[0] = d;
+ new_pool_insert(s, n);
+}
+
+/* For v64 or v128, depending on the host. */
+static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label,
+ int addend, tcg_target_ulong d0,
+ tcg_target_ulong d1)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ new_pool_insert(s, n);
+}
+
+/* For v128 or v256, depending on the host. */
+static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label,
+ int addend, tcg_target_ulong d0,
+ tcg_target_ulong d1, tcg_target_ulong d2,
+ tcg_target_ulong d3)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ n->data[2] = d2;
+ n->data[3] = d3;
+ new_pool_insert(s, n);
+}
+
+/* For v256, for 32-bit host. */
+static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
+ int addend, tcg_target_ulong d0,
+ tcg_target_ulong d1, tcg_target_ulong d2,
+ tcg_target_ulong d3, tcg_target_ulong d4,
+ tcg_target_ulong d5, tcg_target_ulong d6,
+ tcg_target_ulong d7)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ n->data[2] = d2;
+ n->data[3] = d3;
+ n->data[4] = d4;
+ n->data[5] = d5;
+ n->data[6] = d6;
+ n->data[7] = d7;
+ new_pool_insert(s, n);
+}
+
/* To be provided by cpu/tcg-target.inc.c. */
static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
static bool tcg_out_pool_finalize(TCGContext *s)
{
TCGLabelPoolData *p = s->pool_labels;
- tcg_target_ulong d, *a;
+ TCGLabelPoolData *l = NULL;
+ void *a;
if (p == NULL) {
return true;
@@ -62,24 +133,24 @@ static bool tcg_out_pool_finalize(TCGContext *s)
/* ??? Round up to qemu_icache_linesize, but then do not round
again when allocating the next TranslationBlock structure. */
- a = (void *)ROUND_UP((uintptr_t)s->code_ptr, sizeof(tcg_target_ulong));
+ a = (void *)ROUND_UP((uintptr_t)s->code_ptr,
+ sizeof(tcg_target_ulong) * p->nlong);
tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr);
s->data_gen_ptr = a;
- /* Ensure the first comparison fails. */
- d = p->data + 1;
-
for (; p != NULL; p = p->next) {
- if (p->data != d) {
- d = p->data;
- if (unlikely((void *)a > s->code_gen_highwater)) {
+ size_t size = sizeof(tcg_target_ulong) * p->nlong;
+ if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
+ if (unlikely(a > s->code_gen_highwater)) {
return false;
}
- *a++ = d;
+ memcpy(a, p->data, size);
+ a += size;
+ l = p;
}
- patch_reloc(p->label, p->type, (intptr_t)(a - 1), p->addend);
+ patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend);
}
- s->code_ptr = (void *)a;
+ s->code_ptr = a;
return true;
}
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 02/26] tcg: Add types and basic operations for host vectors
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 01/26] tcg: Allow multiple word entries into the constant pool Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 03/26] tcg: Standardize integral arguments to expanders Richard Henderson
` (26 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Nothing uses or enables them yet.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Makefile.target | 4 +-
tcg/tcg-op.h | 30 +++++
tcg/tcg-opc.h | 26 ++++
tcg/tcg.h | 56 +++++++++
tcg/tcg-op-vec.c | 362 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg.c | 100 ++++++++++++++-
tcg/README | 58 +++++++++
7 files changed, 630 insertions(+), 6 deletions(-)
create mode 100644 tcg/tcg-op-vec.c
diff --git a/Makefile.target b/Makefile.target
index f9a9da7e7c..7f30a1e725 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -93,8 +93,8 @@ all: $(PROGS) stap
# cpu emulator library
obj-y += exec.o
obj-y += accel/
-obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o
-obj-$(CONFIG_TCG) += tcg/tcg-common.o
+obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o
+obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o
obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o
obj-y += fpu/softfloat.o
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index ca07b32b65..9b0560e4d3 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -35,6 +35,10 @@ void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
+void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
+void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
+void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
+
static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
{
tcg_gen_op1(opc, tcgv_i32_arg(a1));
@@ -903,6 +907,30 @@ void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
+void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
+void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
+void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
+void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
+void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
+void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
+void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
+void tcg_gen_movi_v64(TCGv_vec, uint64_t);
+void tcg_gen_movi_v128(TCGv_vec, uint64_t, uint64_t);
+void tcg_gen_movi_v256(TCGv_vec, uint64_t, uint64_t, uint64_t, uint64_t);
+void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+
+void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
+void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
+void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
+
#if TARGET_LONG_BITS == 64
#define tcg_gen_movi_tl tcg_gen_movi_i64
#define tcg_gen_mov_tl tcg_gen_mov_i64
@@ -1001,6 +1029,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
+#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
#else
#define tcg_gen_movi_tl tcg_gen_movi_i32
#define tcg_gen_mov_tl tcg_gen_mov_i32
@@ -1098,6 +1127,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
+#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
#endif
#if UINTPTR_MAX == UINT32_MAX
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 956fb1e9f3..4e62eda14b 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -204,8 +204,34 @@ DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
+/* Host vector support. */
+
+#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
+
+DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
+DEF(movi_vec, 1, 0, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) /* vecl defines const args */
+DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
+
+DEF(dup_vec, 1, 1, 0, IMPLVEC)
+DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
+
+DEF(ld_vec, 1, 1, 1, IMPLVEC)
+DEF(st_vec, 0, 2, 1, IMPLVEC)
+
+DEF(add_vec, 1, 2, 0, IMPLVEC)
+DEF(sub_vec, 1, 2, 0, IMPLVEC)
+DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
+
+DEF(and_vec, 1, 2, 0, IMPLVEC)
+DEF(or_vec, 1, 2, 0, IMPLVEC)
+DEF(xor_vec, 1, 2, 0, IMPLVEC)
+DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
+DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
+DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+
#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL
#undef IMPL64
+#undef IMPLVEC
#undef DEF
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 2ce497cebf..dce483b0ee 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -170,6 +170,27 @@ typedef uint64_t TCGRegSet;
# error "Missing unsigned widening multiply"
#endif
+#if !defined(TCG_TARGET_HAS_v64) \
+ && !defined(TCG_TARGET_HAS_v128) \
+ && !defined(TCG_TARGET_HAS_v256)
+#define TCG_TARGET_MAYBE_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_orc_vec 0
+#else
+#define TCG_TARGET_MAYBE_vec 1
+#endif
+#ifndef TCG_TARGET_HAS_v64
+#define TCG_TARGET_HAS_v64 0
+#endif
+#ifndef TCG_TARGET_HAS_v128
+#define TCG_TARGET_HAS_v128 0
+#endif
+#ifndef TCG_TARGET_HAS_v256
+#define TCG_TARGET_HAS_v256 0
+#endif
+
#ifndef TARGET_INSN_START_EXTRA_WORDS
# define TARGET_INSN_START_WORDS 1
#else
@@ -246,6 +267,11 @@ typedef struct TCGPool {
typedef enum TCGType {
TCG_TYPE_I32,
TCG_TYPE_I64,
+
+ TCG_TYPE_V64,
+ TCG_TYPE_V128,
+ TCG_TYPE_V256,
+
TCG_TYPE_COUNT, /* number of different types */
/* An alias for the size of the host register. */
@@ -396,6 +422,8 @@ typedef tcg_target_ulong TCGArg;
* TCGv_i32 : 32 bit integer type
* TCGv_i64 : 64 bit integer type
* TCGv_ptr : a host pointer type
+ * TCGv_vec : a host vector type; the exact size is not exposed
+ to the CPU front-end code.
* TCGv : an integer type the same size as target_ulong
(an alias for either TCGv_i32 or TCGv_i64)
The compiler's type checking will complain if you mix them
@@ -418,6 +446,7 @@ typedef tcg_target_ulong TCGArg;
typedef struct TCGv_i32_d *TCGv_i32;
typedef struct TCGv_i64_d *TCGv_i64;
typedef struct TCGv_ptr_d *TCGv_ptr;
+typedef struct TCGv_vec_d *TCGv_vec;
typedef TCGv_ptr TCGv_env;
#if TARGET_LONG_BITS == 32
#define TCGv TCGv_i32
@@ -589,6 +618,9 @@ typedef struct TCGOp {
#define TCGOP_CALLI(X) (X)->param1
#define TCGOP_CALLO(X) (X)->param2
+#define TCGOP_VECL(X) (X)->param1
+#define TCGOP_VECE(X) (X)->param2
+
/* Make sure operands fit in the bitfields above. */
QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
@@ -726,6 +758,11 @@ static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
return tcgv_i32_temp((TCGv_i32)v);
}
+static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
+{
+ return tcgv_i32_temp((TCGv_i32)v);
+}
+
static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
{
return temp_arg(tcgv_i32_temp(v));
@@ -741,6 +778,11 @@ static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
return temp_arg(tcgv_ptr_temp(v));
}
+static inline TCGArg tcgv_vec_arg(TCGv_vec v)
+{
+ return temp_arg(tcgv_vec_temp(v));
+}
+
static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
{
(void)temp_idx(t); /* trigger embedded assert */
@@ -757,6 +799,11 @@ static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
return (TCGv_ptr)temp_tcgv_i32(t);
}
+static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
+{
+ return (TCGv_vec)temp_tcgv_i32(t);
+}
+
#if TCG_TARGET_REG_BITS == 32
static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
{
@@ -832,9 +879,12 @@ TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
+TCGv_vec tcg_temp_new_vec(TCGType type);
+TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
void tcg_temp_free_i32(TCGv_i32 arg);
void tcg_temp_free_i64(TCGv_i64 arg);
+void tcg_temp_free_vec(TCGv_vec arg);
static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
const char *name)
@@ -916,6 +966,8 @@ enum {
/* Instruction is optional and not implemented by the host, or insn
is generic and should not be implemened by the host. */
TCG_OPF_NOT_PRESENT = 0x10,
+ /* Instruction operands are vectors. */
+ TCG_OPF_VECTOR = 0x20,
};
typedef struct TCGOpDef {
@@ -981,6 +1033,10 @@ TCGv_i32 tcg_const_i32(int32_t val);
TCGv_i64 tcg_const_i64(int64_t val);
TCGv_i32 tcg_const_local_i32(int32_t val);
TCGv_i64 tcg_const_local_i64(int64_t val);
+TCGv_vec tcg_const_zeros_vec(TCGType);
+TCGv_vec tcg_const_ones_vec(TCGType);
+TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
+TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
TCGLabel *gen_new_label(void);
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
new file mode 100644
index 0000000000..dc04c11860
--- /dev/null
+++ b/tcg/tcg-op-vec.c
@@ -0,0 +1,362 @@
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "tcg.h"
+#include "tcg-op.h"
+#include "tcg-mo.h"
+
+/* Reduce the number of ifdefs below. This assumes that all uses of
+ TCGV_HIGH and TCGV_LOW are properly protected by a conditional that
+ the compiler can eliminate. */
+#if TCG_TARGET_REG_BITS == 64
+extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64);
+extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
+#define TCGV_LOW TCGV_LOW_link_error
+#define TCGV_HIGH TCGV_HIGH_link_error
+#endif
+
+void vec_gen_2(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a)
+{
+ TCGOp *op = tcg_emit_op(opc);
+ TCGOP_VECL(op) = type - TCG_TYPE_V64;
+ TCGOP_VECE(op) = vece;
+ op->args[0] = r;
+ op->args[1] = a;
+}
+
+void vec_gen_3(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg r, TCGArg a, TCGArg b)
+{
+ TCGOp *op = tcg_emit_op(opc);
+ TCGOP_VECL(op) = type - TCG_TYPE_V64;
+ TCGOP_VECE(op) = vece;
+ op->args[0] = r;
+ op->args[1] = a;
+ op->args[2] = b;
+}
+
+void vec_gen_4(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg r, TCGArg a, TCGArg b, TCGArg c)
+{
+ TCGOp *op = tcg_emit_op(opc);
+ TCGOP_VECL(op) = type - TCG_TYPE_V64;
+ TCGOP_VECE(op) = vece;
+ op->args[0] = r;
+ op->args[1] = a;
+ op->args[2] = b;
+ op->args[3] = c;
+}
+
+static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGType type = rt->base_type;
+
+ tcg_debug_assert(at->base_type == type);
+ vec_gen_2(opc, type, vece, temp_arg(rt), temp_arg(at));
+}
+
+static void vec_gen_op3(TCGOpcode opc, unsigned vece,
+ TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGTemp *bt = tcgv_vec_temp(b);
+ TCGType type = rt->base_type;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(bt->base_type == type);
+ vec_gen_3(opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt));
+}
+
+void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
+{
+ if (r != a) {
+ vec_gen_op2(INDEX_op_mov_vec, 0, r, a);
+ }
+}
+
+#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
+
+static void tcg_gen_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
+}
+
+TCGv_vec tcg_const_zeros_vec(TCGType type)
+{
+ TCGv_vec ret = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(ret, MO_REG, 0);
+ return ret;
+}
+
+TCGv_vec tcg_const_ones_vec(TCGType type)
+{
+ TCGv_vec ret = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(ret, MO_REG, -1);
+ return ret;
+}
+
+TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec m)
+{
+ TCGTemp *t = tcgv_vec_temp(m);
+ return tcg_const_zeros_vec(t->base_type);
+}
+
+TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
+{
+ TCGTemp *t = tcgv_vec_temp(m);
+ return tcg_const_ones_vec(t->base_type);
+}
+
+void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
+{
+ if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
+ tcg_gen_dupi_vec(r, MO_32, a);
+ } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
+ tcg_gen_dupi_vec(r, MO_64, a);
+ } else {
+ TCGv_i64 c = tcg_const_i64(a);
+ tcg_gen_dup_i64_vec(MO_64, r, c);
+ tcg_temp_free_i64(c);
+ }
+}
+
+void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)
+{
+ tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
+}
+
+void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)
+{
+ tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
+}
+
+void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
+{
+ tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
+}
+
+void tcg_gen_movi_v64(TCGv_vec r, uint64_t a)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGArg ri = temp_arg(rt);
+
+ tcg_debug_assert(rt->base_type == TCG_TYPE_V64);
+ if (TCG_TARGET_REG_BITS == 64) {
+ vec_gen_2(INDEX_op_movi_vec, TCG_TYPE_V64, 0, ri, a);
+ } else {
+ vec_gen_3(INDEX_op_movi_vec, TCG_TYPE_V64, 0, ri, a, a >> 32);
+ }
+}
+
+void tcg_gen_movi_v128(TCGv_vec r, uint64_t a, uint64_t b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGArg ri = temp_arg(rt);
+
+ tcg_debug_assert(rt->base_type == TCG_TYPE_V128);
+ if (a == b) {
+ tcg_gen_dup64i_vec(r, a);
+ } else if (TCG_TARGET_REG_BITS == 64) {
+ vec_gen_3(INDEX_op_movi_vec, TCG_TYPE_V128, 0, ri, a, b);
+ } else {
+ TCGOp *op = tcg_emit_op(INDEX_op_movi_vec);
+ TCGOP_VECL(op) = TCG_TYPE_V128 - TCG_TYPE_V64;
+ op->args[0] = ri;
+ op->args[1] = a;
+ op->args[2] = a >> 32;
+ op->args[3] = b;
+ op->args[4] = b >> 32;
+ }
+}
+
+void tcg_gen_movi_v256(TCGv_vec r, uint64_t a, uint64_t b,
+ uint64_t c, uint64_t d)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGTemp *rt = arg_temp(ri);
+
+ tcg_debug_assert(rt->base_type == TCG_TYPE_V256);
+ if (a == b && a == c && a == d) {
+ tcg_gen_dup64i_vec(r, a);
+ } else {
+ TCGOp *op = tcg_emit_op(INDEX_op_movi_vec);
+ TCGOP_VECL(op) = TCG_TYPE_V256 - TCG_TYPE_V64;
+ op->args[0] = ri;
+ if (TCG_TARGET_REG_BITS == 64) {
+ op->args[1] = a;
+ op->args[2] = b;
+ op->args[3] = c;
+ op->args[4] = d;
+ } else {
+ op->args[1] = a;
+ op->args[2] = a >> 32;
+ op->args[3] = b;
+ op->args[4] = b >> 32;
+ op->args[5] = c;
+ op->args[6] = c >> 32;
+ op->args[7] = d;
+ op->args[8] = d >> 32;
+ }
+ }
+}
+
+void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGTemp *rt = arg_temp(ri);
+ TCGType type = rt->base_type;
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ TCGArg ai = tcgv_i64_arg(a);
+ vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai);
+ } else if (vece == MO_64) {
+ TCGArg al = tcgv_i32_arg(TCGV_LOW(a));
+ TCGArg ah = tcgv_i32_arg(TCGV_HIGH(a));
+ vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah);
+ } else {
+ TCGArg ai = tcgv_i32_arg(TCGV_LOW(a));
+ vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai);
+ }
+}
+
+void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TCGv_i32 a)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGArg ai = tcgv_i32_arg(a);
+ TCGTemp *rt = arg_temp(ri);
+ TCGType type = rt->base_type;
+
+ vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);
+}
+
+static void vec_gen_ldst(TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGArg bi = tcgv_ptr_arg(b);
+ TCGTemp *rt = arg_temp(ri);
+ TCGType type = rt->base_type;
+
+ vec_gen_3(opc, type, 0, ri, bi, o);
+}
+
+void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr b, TCGArg o)
+{
+ vec_gen_ldst(INDEX_op_ld_vec, r, b, o);
+}
+
+void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr b, TCGArg o)
+{
+ vec_gen_ldst(INDEX_op_st_vec, r, b, o);
+}
+
+void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o, TCGType low_type)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGArg bi = tcgv_ptr_arg(b);
+ TCGTemp *rt = arg_temp(ri);
+ TCGType type = rt->base_type;
+
+ tcg_debug_assert(low_type >= TCG_TYPE_V64);
+ tcg_debug_assert(low_type <= type);
+ vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o);
+}
+
+void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_add_vec, vece, r, a, b);
+}
+
+void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_sub_vec, vece, r, a, b);
+}
+
+void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_and_vec, 0, r, a, b);
+}
+
+void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_or_vec, 0, r, a, b);
+}
+
+void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_xor_vec, 0, r, a, b);
+}
+
+void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ if (TCG_TARGET_HAS_andc_vec) {
+ vec_gen_op3(INDEX_op_andc_vec, 0, r, a, b);
+ } else {
+ TCGv_vec t = tcg_temp_new_vec_matching(r);
+ tcg_gen_not_vec(0, t, b);
+ tcg_gen_and_vec(0, r, a, t);
+ tcg_temp_free_vec(t);
+ }
+}
+
+void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ if (TCG_TARGET_HAS_orc_vec) {
+ vec_gen_op3(INDEX_op_orc_vec, 0, r, a, b);
+ } else {
+ TCGv_vec t = tcg_temp_new_vec_matching(r);
+ tcg_gen_not_vec(0, t, b);
+ tcg_gen_or_vec(0, r, a, t);
+ tcg_temp_free_vec(t);
+ }
+}
+
+void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ if (TCG_TARGET_HAS_not_vec) {
+ vec_gen_op2(INDEX_op_not_vec, 0, r, a);
+ } else {
+ TCGv_vec t = tcg_const_ones_vec_matching(r);
+ tcg_gen_xor_vec(0, r, a, t);
+ tcg_temp_free_vec(t);
+ }
+}
+
+void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ if (TCG_TARGET_HAS_neg_vec) {
+ vec_gen_op2(INDEX_op_neg_vec, vece, r, a);
+ } else {
+ TCGv_vec t = tcg_const_zeros_vec_matching(r);
+ tcg_gen_sub_vec(vece, r, t, a);
+ tcg_temp_free_vec(t);
+ }
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 93caa0be93..16b8faf66f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -106,6 +106,18 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg);
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args);
+#if TCG_TARGET_MAYBE_vec
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
+ unsigned vece, const TCGArg *args,
+ const int *const_args);
+#else
+static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
+ unsigned vece, const TCGArg *args,
+ const int *const_args)
+{
+ g_assert_not_reached();
+}
+#endif
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
intptr_t arg2);
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
@@ -146,8 +158,7 @@ struct tcg_region_state {
};
static struct tcg_region_state region;
-
-static TCGRegSet tcg_target_available_regs[2];
+static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT];
static TCGRegSet tcg_target_call_clobber_regs;
#if TCG_TARGET_INSN_UNIT_SIZE == 1
@@ -1026,6 +1037,41 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
return temp_tcgv_i64(t);
}
+TCGv_vec tcg_temp_new_vec(TCGType type)
+{
+ TCGTemp *t;
+
+#ifdef CONFIG_DEBUG_TCG
+ switch (type) {
+ case TCG_TYPE_V64:
+ assert(TCG_TARGET_HAS_v64);
+ break;
+ case TCG_TYPE_V128:
+ assert(TCG_TARGET_HAS_v128);
+ break;
+ case TCG_TYPE_V256:
+ assert(TCG_TARGET_HAS_v256);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+#endif
+
+ t = tcg_temp_new_internal(type, 0);
+ return temp_tcgv_vec(t);
+}
+
+/* Create a new temp of the same type as an existing temp. */
+TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match)
+{
+ TCGTemp *t = tcgv_vec_temp(match);
+
+ tcg_debug_assert(t->temp_allocated != 0);
+
+ t = tcg_temp_new_internal(t->base_type, 0);
+ return temp_tcgv_vec(t);
+}
+
static void tcg_temp_free_internal(TCGTemp *ts)
{
TCGContext *s = tcg_ctx;
@@ -1057,6 +1103,11 @@ void tcg_temp_free_i64(TCGv_i64 arg)
tcg_temp_free_internal(tcgv_i64_temp(arg));
}
+void tcg_temp_free_vec(TCGv_vec arg)
+{
+ tcg_temp_free_internal(tcgv_vec_temp(arg));
+}
+
TCGv_i32 tcg_const_i32(int32_t val)
{
TCGv_i32 t0;
@@ -1114,6 +1165,9 @@ int tcg_check_temp_count(void)
Test the runtime variable that controls each opcode. */
bool tcg_op_supported(TCGOpcode op)
{
+ const bool have_vec
+ = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256;
+
switch (op) {
case INDEX_op_discard:
case INDEX_op_set_label:
@@ -1327,6 +1381,29 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_mulsh_i64:
return TCG_TARGET_HAS_mulsh_i64;
+ case INDEX_op_mov_vec:
+ case INDEX_op_movi_vec:
+ case INDEX_op_dup_vec:
+ case INDEX_op_dupi_vec:
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ return have_vec;
+ case INDEX_op_dup2_vec:
+ return have_vec && TCG_TARGET_REG_BITS == 32;
+ case INDEX_op_not_vec:
+ return have_vec && TCG_TARGET_HAS_not_vec;
+ case INDEX_op_neg_vec:
+ return have_vec && TCG_TARGET_HAS_neg_vec;
+ case INDEX_op_andc_vec:
+ return have_vec && TCG_TARGET_HAS_andc_vec;
+ case INDEX_op_orc_vec:
+ return have_vec && TCG_TARGET_HAS_orc_vec;
+
case NB_OPS:
break;
}
@@ -1661,6 +1738,14 @@ void tcg_dump_ops(TCGContext *s)
nb_iargs = def->nb_iargs;
nb_cargs = def->nb_cargs;
+ if (c == INDEX_op_movi_vec) {
+ nb_cargs = (64 / TCG_TARGET_REG_BITS) << TCGOP_VECL(op);
+ }
+ if (def->flags & TCG_OPF_VECTOR) {
+ col += qemu_log("v%d,e%d,", 64 << TCGOP_VECL(op),
+ 8 << TCGOP_VECE(op));
+ }
+
k = 0;
for (i = 0; i < nb_oargs; i++) {
if (k != 0) {
@@ -2890,8 +2975,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
/* emit instruction */
- tcg_out_op(s, op->opc, new_args, const_args);
-
+ if (def->flags & TCG_OPF_VECTOR) {
+ tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
+ new_args, const_args);
+ } else {
+ tcg_out_op(s, op->opc, new_args, const_args);
+ }
+
/* move the outputs in the correct register if needed */
for(i = 0; i < nb_oargs; i++) {
ts = arg_temp(op->args[i]);
@@ -3239,10 +3329,12 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
switch (opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
+ case INDEX_op_mov_vec:
tcg_reg_alloc_mov(s, op);
break;
case INDEX_op_movi_i32:
case INDEX_op_movi_i64:
+ case INDEX_op_dupi_vec:
tcg_reg_alloc_movi(s, op);
break;
case INDEX_op_insn_start:
diff --git a/tcg/README b/tcg/README
index 03bfb6acd4..e14990fb9b 100644
--- a/tcg/README
+++ b/tcg/README
@@ -503,6 +503,64 @@ of the memory access.
For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
64-bit memory access specified in flags.
+********* Host vector operations
+
+All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE.
+The former specifies the length of the vector in log2 64-bit units; the
+later specifies the length of the element (if applicable) in log2 8-bit units.
+E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
+
+* mov_vec v0, v1
+* ld_vec v0, t1
+* st_vec v0, t1
+
+ Move, load and store.
+
+* movi_vec v0, a, b, ...
+
+ Move with constant data. There are arguments to hold the entire
+ vector value, stored little-endian. Note that the way MAX_OPC_PARAM
+ is sized for 64- and 32-bit hosts, there are enough slots for v256,
+ but not a future v512.
+
+ Prefer dupi_vec when possible.
+
+* dup_vec v0, r1
+
+ Duplicate the low N bits of R1 into VECL/VECE copies across V0.
+
+* dupi_vec v0, c
+
+ Similarly, for a constant.
+ Smaller values will be replicated to host register size by the expanders.
+
+* dup2_vec v0, r1, r2
+
+ Duplicate r2:r1 into VECL/64 copies across V0. This opcode is
+ only present for 32-bit hosts.
+
+* add_vec v0, v1, v2
+
+ v0 = v1 + v2, in elements across the vector.
+
+* sub_vec v0, v1, v2
+
+ Similarly, v0 = v1 - v2.
+
+* neg_vec v0, v1
+
+ Similarly, v0 = -v1.
+
+* and_vec v0, v1, v2
+* or_vec v0, v1, v2
+* xor_vec v0, v1, v2
+* andc_vec v0, v1, v2
+* orc_vec v0, v1, v2
+* not_vec v0, v1
+
+ Similarly, logical operations with and without compliment.
+ Note that VECE is unused.
+
*********
Note 1: Some shortcuts are defined when the last operand is known to be
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 03/26] tcg: Standardize integral arguments to expanders
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 01/26] tcg: Allow multiple word entries into the constant pool Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 02/26] tcg: Add types and basic operations for host vectors Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 04/26] tcg: Add generic vector expanders Richard Henderson
` (25 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Some functions use intN_t arguments, some use uintN_t, some just
used "unsigned". To aid putting function pointers in tables, we
need consistency.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.h | 16 ++++++++--------
tcg/tcg-op.c | 42 +++++++++++++++++++++---------------------
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 9b0560e4d3..df2eabaa67 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -269,12 +269,12 @@ void tcg_gen_mb(TCGBar);
void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
+void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
-void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
-void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
-void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
+void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
+void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
+void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
@@ -458,12 +458,12 @@ static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
+void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
-void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
-void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
-void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
+void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
+void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
+void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 0c509bfe46..3467787323 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -140,7 +140,7 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
}
}
-void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
+void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
TCGv_i32 t0;
/* Some cases can be optimized here. */
@@ -148,17 +148,17 @@ void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
case 0:
tcg_gen_movi_i32(ret, 0);
return;
- case 0xffffffffu:
+ case -1:
tcg_gen_mov_i32(ret, arg1);
return;
- case 0xffu:
+ case 0xff:
/* Don't recurse with tcg_gen_ext8u_i32. */
if (TCG_TARGET_HAS_ext8u_i32) {
tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
return;
}
break;
- case 0xffffu:
+ case 0xffff:
if (TCG_TARGET_HAS_ext16u_i32) {
tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
return;
@@ -199,9 +199,9 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
}
}
-void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
+void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
- tcg_debug_assert(arg2 < 32);
+ tcg_debug_assert(arg2 >= 0 && arg2 < 32);
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
@@ -211,9 +211,9 @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
}
}
-void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
+void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
- tcg_debug_assert(arg2 < 32);
+ tcg_debug_assert(arg2 >= 0 && arg2 < 32);
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
@@ -223,9 +223,9 @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
}
}
-void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2)
+void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
- tcg_debug_assert(arg2 < 32);
+ tcg_debug_assert(arg2 >= 0 && arg2 < 32);
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
@@ -1201,7 +1201,7 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
}
}
-void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
+void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
{
TCGv_i64 t0;
@@ -1216,23 +1216,23 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
case 0:
tcg_gen_movi_i64(ret, 0);
return;
- case 0xffffffffffffffffull:
+ case -1:
tcg_gen_mov_i64(ret, arg1);
return;
- case 0xffull:
+ case 0xff:
/* Don't recurse with tcg_gen_ext8u_i64. */
if (TCG_TARGET_HAS_ext8u_i64) {
tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
return;
}
break;
- case 0xffffu:
+ case 0xffff:
if (TCG_TARGET_HAS_ext16u_i64) {
tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
return;
}
break;
- case 0xffffffffull:
+ case 0xffffffffu:
if (TCG_TARGET_HAS_ext32u_i64) {
tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
return;
@@ -1332,9 +1332,9 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
}
}
-void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
+void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
{
- tcg_debug_assert(arg2 < 64);
+ tcg_debug_assert(arg2 >= 0 && arg2 < 64);
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
} else if (arg2 == 0) {
@@ -1346,9 +1346,9 @@ void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
}
}
-void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
+void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
{
- tcg_debug_assert(arg2 < 64);
+ tcg_debug_assert(arg2 >= 0 && arg2 < 64);
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
} else if (arg2 == 0) {
@@ -1360,9 +1360,9 @@ void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
}
}
-void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2)
+void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
{
- tcg_debug_assert(arg2 < 64);
+ tcg_debug_assert(arg2 >= 0 && arg2 < 64);
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
} else if (arg2 == 0) {
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 04/26] tcg: Add generic vector expanders
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (2 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 03/26] tcg: Standardize integral arguments to expanders Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 05/26] tcg: Add generic vector ops for interleave Richard Henderson
` (24 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Makefile.target | 2 +-
accel/tcg/tcg-runtime.h | 29 +
tcg/tcg-gvec-desc.h | 49 ++
tcg/tcg-op-gvec.h | 198 +++++++
tcg/tcg-op.h | 1 +
tcg/tcg-opc.h | 6 +
tcg/tcg.h | 18 +
accel/tcg/tcg-runtime-gvec.c | 295 ++++++++++
tcg/tcg-op-gvec.c | 1295 ++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 36 +-
tcg/tcg.c | 13 +-
accel/tcg/Makefile.objs | 2 +-
12 files changed, 1931 insertions(+), 13 deletions(-)
create mode 100644 tcg/tcg-gvec-desc.h
create mode 100644 tcg/tcg-op-gvec.h
create mode 100644 accel/tcg/tcg-runtime-gvec.c
create mode 100644 tcg/tcg-op-gvec.c
diff --git a/Makefile.target b/Makefile.target
index 7f30a1e725..6549481096 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -93,7 +93,7 @@ all: $(PROGS) stap
# cpu emulator library
obj-y += exec.o
obj-y += accel/
-obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o
+obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o
obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o
obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 1df17d0ba9..76ee41ce58 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -134,3 +134,32 @@ GEN_ATOMIC_HELPERS(xor_fetch)
GEN_ATOMIC_HELPERS(xchg)
#undef GEN_ATOMIC_HELPERS
+
+DEF_HELPER_FLAGS_3(gvec_mov, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_dup8, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup16, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup32, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup64, TCG_CALL_NO_RWG, void, ptr, i32, i64)
+
+DEF_HELPER_FLAGS_4(gvec_add8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_sub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/tcg-gvec-desc.h b/tcg/tcg-gvec-desc.h
new file mode 100644
index 0000000000..8ba9a8168d
--- /dev/null
+++ b/tcg/tcg-gvec-desc.h
@@ -0,0 +1,49 @@
+/*
+ * Generic vector operation descriptor
+ *
+ * Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
+#define SIMD_OPRSZ_SHIFT 0
+#define SIMD_OPRSZ_BITS 5
+
+#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
+#define SIMD_MAXSZ_BITS 5
+
+#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
+
+/* Create a descriptor from components. */
+uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
+
+/* Extract the operation size from a descriptor. */
+static inline intptr_t simd_oprsz(uint32_t desc)
+{
+ return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
+}
+
+/* Extract the max vector size from a descriptor. */
+static inline intptr_t simd_maxsz(uint32_t desc)
+{
+ return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
+}
+
+/* Extract the operation-specific data from a descriptor. */
+static inline int32_t simd_data(uint32_t desc)
+{
+ return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);
+}
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
new file mode 100644
index 0000000000..57285ec293
--- /dev/null
+++ b/tcg/tcg-op-gvec.h
@@ -0,0 +1,198 @@
+/*
+ * Generic vector operation expansion
+ *
+ * Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * "Generic" vectors. All operands are given as offsets from ENV,
+ * and therefore cannot also be allocated via tcg_global_mem_new_*.
+ * OPRSZ is the byte size of the vector upon which the operation is performed.
+ * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
+ *
+ * All sizes must be 8 or any multiple of 16.
+ * When OPRSZ is 8, the alignment may be 8, otherwise must be 16.
+ * Operands may completely, but not partially, overlap.
+ */
+
+/* Expand a call to a gvec-style helper, with pointers to two vector
+ operands, and a descriptor (see tcg-gvec-desc.h). */
+typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2 *fn);
+
+/* Similarly, passing an extra pointer (e.g. env or float_status). */
+typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_2_ptr *fn);
+
+/* Similarly, with three vector operands. */
+typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_3 *fn);
+
+/* Similarly, with four vector operands. */
+typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_4 *fn);
+
+/* Similarly, with five vector operands. */
+typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t xofs, uint32_t oprsz,
+ uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn);
+
+typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_3_ptr *fn);
+
+typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
+ uint32_t maxsz, int32_t data,
+ gen_helper_gvec_4_ptr *fn);
+
+/* Expand a gvec operation. Either inline or out-of-line depending on
+ the actual vector size and the operations supported by the host. */
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_2 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ int32_t data;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+} GVecGen2;
+
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_3 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ int32_t data;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+ /* Load dest as a 3rd source operand. */
+ bool load_dest;
+} GVecGen3;
+
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_4 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ int32_t data;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+} GVecGen4;
+
+void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
+void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
+void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
+
+/* Expand a specific vector operation. */
+
+void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+
+void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+
+void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+
+void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t s, uint32_t m);
+void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
+ uint32_t m, TCGv_i32);
+void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
+ uint32_t m, TCGv_i64);
+
+void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
+void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
+void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
+void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
+
+/*
+ * 64-bit vector operations. Use these when the register has been allocated
+ * with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
+ * OPRSZ = MAXSZ = 8.
+ */
+
+void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a);
+void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a);
+void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a);
+
+void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+
+void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index df2eabaa67..09fec5693f 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -914,6 +914,7 @@ void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
+void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
void tcg_gen_movi_v64(TCGv_vec, uint64_t);
void tcg_gen_movi_v128(TCGv_vec, uint64_t, uint64_t);
void tcg_gen_movi_v256(TCGv_vec, uint64_t, uint64_t, uint64_t, uint64_t);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 4e62eda14b..b4e16cfbc3 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -229,6 +229,12 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
+
+#if TCG_TARGET_MAYBE_vec
+#include "tcg-target.opc.h"
+#endif
+
#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL
diff --git a/tcg/tcg.h b/tcg/tcg.h
index dce483b0ee..5560e6439a 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -1207,6 +1207,24 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
void tcg_register_jit(void *buf, size_t buf_size);
+#if TCG_TARGET_MAYBE_vec
+/* Return zero if the tuple (opc, type, vece) is unsupportable;
+ return > 0 if it is directly supportable;
+ return < 0 if we must call tcg_expand_vec_op. */
+int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
+#else
+static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
+{
+ return 0;
+}
+#endif
+
+/* Expand the tuple (opc, type, vece) on the given arguments. */
+void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
+
+/* Replicate a constant C accoring to the log2 of the element size. */
+uint64_t dup_const(unsigned vece, uint64_t c);
+
/*
* Memory helpers that will be used by TCG generated code.
*/
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
new file mode 100644
index 0000000000..cd1ce12b7e
--- /dev/null
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -0,0 +1,295 @@
+/*
+ * Generic vectorized operation runtime
+ *
+ * Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "tcg-gvec-desc.h"
+
+
+/* Virtually all hosts support 16-byte vectors. Those that don't can emulate
+ them via GCC's generic vector extension. This turns out to be simpler and
+ more reliable than getting the compiler to autovectorize.
+
+ In tcg-op-gvec.c, we asserted that both the size and alignment
+ of the data are multiples of 16. */
+
+typedef uint8_t vec8 __attribute__((vector_size(16)));
+typedef uint16_t vec16 __attribute__((vector_size(16)));
+typedef uint32_t vec32 __attribute__((vector_size(16)));
+typedef uint64_t vec64 __attribute__((vector_size(16)));
+
+static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
+{
+ intptr_t maxsz = simd_maxsz(desc);
+ intptr_t i;
+
+ if (unlikely(maxsz > oprsz)) {
+ for (i = oprsz; i < maxsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = 0;
+ }
+ }
+}
+
+void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = -*(vec8 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg16)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = -*(vec16 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg32)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = -*(vec32 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg64)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = -*(vec64 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mov)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+
+ memcpy(d, a, oprsz);
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup64)(void *d, uint32_t desc, uint64_t c)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ if (c == 0) {
+ oprsz = 0;
+ } else {
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = c;
+ }
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup32)(void *d, uint32_t desc, uint32_t c)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ if (c == 0) {
+ oprsz = 0;
+ } else {
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = c;
+ }
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup16)(void *d, uint32_t desc, uint32_t c)
+{
+ HELPER(gvec_dup32)(d, desc, 0x00010001 * (c & 0xffff));
+}
+
+void HELPER(gvec_dup8)(void *d, uint32_t desc, uint32_t c)
+{
+ HELPER(gvec_dup32)(d, desc, 0x01010101 * (c & 0xff));
+}
+
+void HELPER(gvec_not)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = ~*(vec64 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_and)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_or)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_xor)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_andc)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
new file mode 100644
index 0000000000..206ae16b19
--- /dev/null
+++ b/tcg/tcg-op-gvec.c
@@ -0,0 +1,1295 @@
+/*
+ * Generic vector operation expansion
+ *
+ * Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "tcg.h"
+#include "tcg-op.h"
+#include "tcg-op-gvec.h"
+#include "tcg-gvec-desc.h"
+
+#define REP8(x) ((x) * 0x0101010101010101ull)
+#define REP16(x) ((x) * 0x0001000100010001ull)
+
+#define MAX_UNROLL 4
+
+/* Verify vector size and alignment rules. OFS should be the OR of all
+ of the operand offsets so that we can check them all at once. */
+static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
+{
+ uint32_t align = maxsz > 16 || oprsz >= 16 ? 15 : 7;
+ tcg_debug_assert(oprsz > 0);
+ tcg_debug_assert(oprsz <= maxsz);
+ tcg_debug_assert((oprsz & align) == 0);
+ tcg_debug_assert((maxsz & align) == 0);
+ tcg_debug_assert((ofs & align) == 0);
+}
+
+/* Verify vector overlap rules for two operands. */
+static void check_overlap_2(uint32_t d, uint32_t a, uint32_t s)
+{
+ tcg_debug_assert(d == a || d + s <= a || a + s <= d);
+}
+
+/* Verify vector overlap rules for three operands. */
+static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s)
+{
+ check_overlap_2(d, a, s);
+ check_overlap_2(d, b, s);
+ check_overlap_2(a, b, s);
+}
+
+/* Verify vector overlap rules for four operands. */
+static void check_overlap_4(uint32_t d, uint32_t a, uint32_t b,
+ uint32_t c, uint32_t s)
+{
+ check_overlap_2(d, a, s);
+ check_overlap_2(d, b, s);
+ check_overlap_2(d, c, s);
+ check_overlap_2(a, b, s);
+ check_overlap_2(a, c, s);
+ check_overlap_2(b, c, s);
+}
+
+/* Create a descriptor from components. */
+uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
+{
+ uint32_t desc = 0;
+
+ assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
+ assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
+ assert(data == sextract32(data, 0, SIMD_DATA_BITS));
+
+ oprsz = (oprsz / 8) - 1;
+ maxsz = (maxsz / 8) - 1;
+ desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
+ desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
+ desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
+
+ return desc;
+}
+
+/* Generate a call to a gvec-style helper with two vector operands. */
+void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2 *fn)
+{
+ TCGv_ptr a0, a1;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+
+ fn(a0, a1, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands. */
+void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_3 *fn)
+{
+ TCGv_ptr a0, a1, a2;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+ a2 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
+
+ fn(a0, a1, a2, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_ptr(a2);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with four vector operands. */
+void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_4 *fn)
+{
+ TCGv_ptr a0, a1, a2, a3;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+ a2 = tcg_temp_new_ptr();
+ a3 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
+
+ fn(a0, a1, a2, a3, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_ptr(a2);
+ tcg_temp_free_ptr(a3);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with five vector operands. */
+void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t xofs, uint32_t oprsz,
+ uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn)
+{
+ TCGv_ptr a0, a1, a2, a3, a4;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+ a2 = tcg_temp_new_ptr();
+ a3 = tcg_temp_new_ptr();
+ a4 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
+ tcg_gen_addi_ptr(a4, cpu_env, xofs);
+
+ fn(a0, a1, a2, a3, a4, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_ptr(a2);
+ tcg_temp_free_ptr(a3);
+ tcg_temp_free_ptr(a4);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands
+ and an extra pointer operand. */
+void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_2_ptr *fn)
+{
+ TCGv_ptr a0, a1;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+
+ fn(a0, a1, ptr, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands
+ and an extra pointer operand. */
+void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_3_ptr *fn)
+{
+ TCGv_ptr a0, a1, a2;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+ a2 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
+
+ fn(a0, a1, a2, ptr, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_ptr(a2);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with four vector operands
+ and an extra pointer operand. */
+void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
+ uint32_t maxsz, int32_t data,
+ gen_helper_gvec_4_ptr *fn)
+{
+ TCGv_ptr a0, a1, a2, a3;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+ a2 = tcg_temp_new_ptr();
+ a3 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
+ tcg_gen_addi_ptr(a3, cpu_env, cofs);
+
+ fn(a0, a1, a2, a3, ptr, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_ptr(a2);
+ tcg_temp_free_ptr(a3);
+ tcg_temp_free_i32(desc);
+}
+
+/* Return true if we want to implement something of OPRSZ bytes
+ in units of LNSZ. This limits the expansion of inline code. */
+static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
+{
+ uint32_t lnct = oprsz / lnsz;
+ return lnct >= 1 && lnct <= MAX_UNROLL;
+}
+
+static void expand_clr(uint32_t dofs, uint32_t maxsz);
+
+/* Duplicate C as per VECE. */
+uint64_t dup_const(unsigned vece, uint64_t c)
+{
+ switch (vece) {
+ case MO_8:
+ return 0x0101010101010101ull * (c & 0xff);
+ case MO_16:
+ return 0x0001000100010001ull * (c & 0xffff);
+ case MO_32:
+ return deposit64(c, 32, 32, c);
+ case MO_64:
+ return c;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+/* Duplicate IN into OUT as per VECE. */
+static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)
+{
+ switch (vece) {
+ case MO_8:
+ tcg_gen_ext8u_i32(out, in);
+ tcg_gen_muli_i32(out, out, 0x01010101);
+ break;
+ case MO_16:
+ tcg_gen_deposit_i32(out, in, in, 16, 16);
+ break;
+ case MO_32:
+ tcg_gen_mov_i32(out, in);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)
+{
+ switch (vece) {
+ case MO_8:
+ tcg_gen_ext8u_i64(out, in);
+ tcg_gen_muli_i64(out, out, 0x0101010101010101ull);
+ break;
+ case MO_16:
+ tcg_gen_ext16u_i64(out, in);
+ tcg_gen_muli_i64(out, out, 0x0001000100010001ull);
+ break;
+ case MO_32:
+ tcg_gen_deposit_i64(out, in, in, 32, 32);
+ break;
+ case MO_64:
+ tcg_gen_mov_i64(out, in);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+/* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C.
+ * Only one of IN_32 or IN_64 may be set;
+ * IN_C is used if IN_32 and IN_64 are unset.
+ */
+static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i32 in_32, TCGv_i64 in_64,
+ uint64_t in_c)
+{
+ TCGType type;
+ TCGv_i64 t_64;
+ TCGv_i32 t_32, t_desc;
+ TCGv_ptr t_ptr;
+ uint32_t i;
+
+ assert(vece <= (in_32 ? MO_32 : MO_64));
+ assert(in_32 == NULL || in_64 == NULL);
+
+ /* If we're storing 0, expand oprsz to maxsz. */
+ if (in_32 == NULL && in_64 == NULL) {
+ in_c = dup_const(vece, in_c);
+ if (in_c == 0) {
+ oprsz = maxsz;
+ }
+ }
+
+ type = 0;
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ type = TCG_TYPE_V256;
+ } else if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ type = TCG_TYPE_V128;
+ } else if (TCG_TARGET_HAS_v64 && check_size_impl(oprsz, 8)) {
+ type = TCG_TYPE_V64;
+ }
+
+ /* Implement inline with a vector type, if possible. */
+ if (type != 0) {
+ TCGv_vec t_vec = tcg_temp_new_vec(type);
+
+ if (in_32) {
+ tcg_gen_dup_i32_vec(vece, t_vec, in_32);
+ } else if (in_64) {
+ tcg_gen_dup_i64_vec(vece, t_vec, in_64);
+ } else {
+ switch (vece) {
+ case MO_8:
+ tcg_gen_dup8i_vec(t_vec, in_c);
+ break;
+ case MO_16:
+ tcg_gen_dup16i_vec(t_vec, in_c);
+ break;
+ case MO_32:
+ tcg_gen_dup32i_vec(t_vec, in_c);
+ break;
+ default:
+ tcg_gen_dup64i_vec(t_vec, in_c);
+ break;
+ }
+ }
+
+ i = 0;
+ if (TCG_TARGET_HAS_v256) {
+ for (; i + 32 <= oprsz; i += 32) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256);
+ }
+ }
+ if (TCG_TARGET_HAS_v128) {
+ for (; i + 16 <= oprsz; i += 16) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128);
+ }
+ }
+ if (TCG_TARGET_HAS_v64) {
+ for (; i < oprsz; i += 8) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
+ }
+ }
+ tcg_temp_free_vec(t_vec);
+ goto done;
+ }
+
+ /* Otherwise, inline with an integer type, unless "large". */
+ if (check_size_impl(oprsz, TCG_TARGET_REG_BITS / 8)) {
+ t_64 = NULL;
+ t_32 = NULL;
+
+ if (in_32) {
+ /* We are given a 32-bit variable input. For a 64-bit host,
+ use a 64-bit operation unless the 32-bit operation would
+ be simple enough. */
+ if (TCG_TARGET_REG_BITS == 64
+ && (vece != MO_32 || !check_size_impl(oprsz, 4))) {
+ t_64 = tcg_temp_new_i64();
+ tcg_gen_extu_i32_i64(t_64, in_32);
+ gen_dup_i64(vece, t_64, t_64);
+ } else {
+ t_32 = tcg_temp_new_i32();
+ gen_dup_i32(vece, t_32, in_32);
+ }
+ } else if (in_64) {
+ /* We are given a 64-bit variable input. */
+ t_64 = tcg_temp_new_i64();
+ gen_dup_i64(vece, t_64, in_64);
+ } else {
+ /* We are given a constant input. */
+ /* For 64-bit hosts, use 64-bit constants for "simple" constants
+ or when we'd need too many 32-bit stores, or when a 64-bit
+ constant is really required. */
+ if (vece == MO_64
+ || (TCG_TARGET_REG_BITS == 64
+ && (in_c == 0 || in_c == -1
+ || !check_size_impl(oprsz, 4)))) {
+ t_64 = tcg_const_i64(in_c);
+ } else {
+ t_32 = tcg_const_i32(in_c);
+ }
+ }
+
+ /* Implement inline if we picked an implementation size above. */
+ if (t_32) {
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_st_i32(t_32, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t_32);
+ goto done;
+ }
+ if (t_64) {
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_st_i64(t_64, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t_64);
+ goto done;
+ }
+ }
+
+ /* Otherwise implement out of line. */
+ t_ptr = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);
+ t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
+
+ if (vece == MO_64) {
+ if (in_64) {
+ gen_helper_gvec_dup64(t_ptr, t_desc, in_64);
+ } else {
+ t_64 = tcg_const_i64(in_c);
+ gen_helper_gvec_dup64(t_ptr, t_desc, t_64);
+ tcg_temp_free_i64(t_64);
+ }
+ } else {
+ typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32);
+ static dup_fn * const fns[3] = {
+ gen_helper_gvec_dup8,
+ gen_helper_gvec_dup16,
+ gen_helper_gvec_dup32
+ };
+
+ if (in_32) {
+ fns[vece](t_ptr, t_desc, in_32);
+ } else {
+ t_32 = tcg_temp_new_i32();
+ if (in_64) {
+ tcg_gen_extrl_i64_i32(t_32, in_64);
+ } else if (vece == MO_8) {
+ tcg_gen_movi_i32(t_32, in_c & 0xff);
+ } else if (vece == MO_16) {
+ tcg_gen_movi_i32(t_32, in_c & 0xffff);
+ } else {
+ tcg_gen_movi_i32(t_32, in_c);
+ }
+ fns[vece](t_ptr, t_desc, t_32);
+ tcg_temp_free_i32(t_32);
+ }
+ }
+
+ tcg_temp_free_ptr(t_ptr);
+ tcg_temp_free_i32(t_desc);
+ return;
+
+ done:
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+/* Likewise, but with zero. */
+static void expand_clr(uint32_t dofs, uint32_t maxsz)
+{
+ do_dup(MO_8, dofs, maxsz, maxsz, NULL, NULL, 0);
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using i32 elements. */
+static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ void (*fni)(TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ fni(t0, t0);
+ tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
+static void expand_3_i32(uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, bool load_dest,
+ void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i32(t2, cpu_env, dofs + i);
+ }
+ fni(t2, t0, t1);
+ tcg_gen_st_i32(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
+static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz,
+ void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t1, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t2, cpu_env, bofs + i);
+ tcg_gen_ld_i32(t3, cpu_env, cofs + i);
+ fni(t0, t1, t2, t3);
+ tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t0);
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
+static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ void (*fni)(TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ fni(t0, t0);
+ tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
+static void expand_3_i64(uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, bool load_dest,
+ void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i64(t2, cpu_env, dofs + i);
+ }
+ fni(t2, t0, t1);
+ tcg_gen_st_i64(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
+static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz,
+ void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t1, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t2, cpu_env, bofs + i);
+ tcg_gen_ld_i64(t3, cpu_env, cofs + i);
+ fni(t0, t1, t2, t3);
+ tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t3);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t0);
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
+static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t tysz, TCGType type,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ fni(vece, t0, t0);
+ tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
+static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz,
+ uint32_t tysz, TCGType type, bool load_dest,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_vec(t2, cpu_env, dofs + i);
+ }
+ fni(vece, t2, t0, t1);
+ tcg_gen_st_vec(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t0);
+}
+
+/* Expand OPSZ bytes worth of four-operand operations using host vectors. */
+static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t cofs, uint32_t oprsz,
+ uint32_t tysz, TCGType type,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec,
+ TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+ TCGv_vec t3 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t1, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t2, cpu_env, bofs + i);
+ tcg_gen_ld_vec(t3, cpu_env, cofs + i);
+ fni(vece, t0, t1, t2, t3);
+ tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t0);
+}
+
+/* Expand a vector two-operand operation. */
+void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs);
+ check_overlap_2(dofs, aofs, maxsz);
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+ /* ??? For maxsz > oprsz, the host may be able to use an opr-sized
+ operation, zeroing the balance of the register. We can then
+ use a max-sized store to implement the clearing without an extra
+ store operation. This is true for aarch64 and x86_64 hosts. */
+
+ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_2_vec(g->vece, dofs, aofs, done, 32, TCG_TYPE_V256, g->fniv);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
+ expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv);
+ } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && g->fniv && check_size_impl(oprsz, 8)
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
+ expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv);
+ } else if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_2_i64(dofs, aofs, oprsz, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_2_i32(dofs, aofs, oprsz, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);
+ return;
+ }
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+/* Expand a vector three-operand operation. */
+void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, maxsz);
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+
+ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_3_vec(g->vece, dofs, aofs, bofs, done, 32, TCG_TYPE_V256,
+ g->load_dest, g->fniv);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
+ expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
+ g->load_dest, g->fniv);
+ } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && g->fniv && check_size_impl(oprsz, 8)
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
+ expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
+ g->load_dest, g->fniv);
+ } else if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_3_i64(dofs, aofs, bofs, oprsz, g->load_dest, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_3_i32(dofs, aofs, bofs, oprsz, g->load_dest, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, g->data, g->fno);
+ }
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+/* Expand a vector four-operand operation. */
+void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
+ check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+
+ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_4_vec(g->vece, dofs, aofs, bofs, cofs, done,
+ 32, TCG_TYPE_V256, g->fniv);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
+ expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
+ 16, TCG_TYPE_V128, g->fniv);
+ } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && g->fniv && check_size_impl(oprsz, 8)
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
+ expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
+ 8, TCG_TYPE_V64, g->fniv);
+ } else if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_4_i64(dofs, aofs, bofs, cofs, oprsz, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_4_i32(dofs, aofs, bofs, cofs, oprsz, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,
+ oprsz, maxsz, g->data, g->fno);
+ return;
+ }
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+/*
+ * Expand specific vector operations.
+ */
+
+static void vec_mov2(unsigned vece, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_mov_vec(a, b);
+}
+
+void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2 g = {
+ .fni8 = tcg_gen_mov_i64,
+ .fniv = vec_mov2,
+ .fno = gen_helper_gvec_mov,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ if (dofs != aofs) {
+ tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g);
+ } else {
+ check_size_align(oprsz, maxsz, dofs);
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+ }
+}
+
+void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i32 in)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ tcg_debug_assert(vece <= MO_32);
+ do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0);
+}
+
+void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i64 in)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ tcg_debug_assert(vece <= MO_64);
+ do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);
+}
+
+void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ if (vece <= MO_32) {
+ TCGv_i32 in = tcg_temp_new_i32();
+ switch (vece) {
+ case MO_8:
+ tcg_gen_ld8u_i32(in, cpu_env, aofs);
+ break;
+ case MO_16:
+ tcg_gen_ld16u_i32(in, cpu_env, aofs);
+ break;
+ case MO_32:
+ tcg_gen_ld_i32(in, cpu_env, aofs);
+ break;
+ }
+ tcg_gen_gvec_dup_i32(vece, dofs, oprsz, maxsz, in);
+ tcg_temp_free_i32(in);
+ } else if (vece == MO_64) {
+ TCGv_i64 in = tcg_temp_new_i64();
+ tcg_gen_ld_i64(in, cpu_env, aofs);
+ tcg_gen_gvec_dup_i64(MO_64, dofs, oprsz, maxsz, in);
+ tcg_temp_free_i64(in);
+ } else {
+ /* 128-bit duplicate. */
+ /* ??? Dup to 256-bit vector. */
+ int i;
+
+ tcg_debug_assert(vece == 4);
+ tcg_debug_assert(oprsz >= 16);
+ if (TCG_TARGET_HAS_v128) {
+ TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128);
+
+ tcg_gen_ld_vec(in, cpu_env, aofs);
+ for (i = 0; i < oprsz; i += 16) {
+ tcg_gen_st_vec(in, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(in);
+ } else {
+ TCGv_i64 in0 = tcg_temp_new_i64();
+ TCGv_i64 in1 = tcg_temp_new_i64();
+
+ tcg_gen_ld_i64(in0, cpu_env, aofs);
+ tcg_gen_ld_i64(in1, cpu_env, aofs + 8);
+ for (i = 0; i < oprsz; i += 16) {
+ tcg_gen_st_i64(in0, cpu_env, dofs + i);
+ tcg_gen_st_i64(in1, cpu_env, dofs + i + 8);
+ }
+ tcg_temp_free_i64(in0);
+ tcg_temp_free_i64(in1);
+ }
+ }
+}
+
+void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint64_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
+void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint32_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
+void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint16_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
+void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint8_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
+void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2 g = {
+ .fni8 = tcg_gen_not_i64,
+ .fniv = tcg_gen_not_vec,
+ .fno = gen_helper_gvec_not,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g);
+}
+
+/* Perform a vector addition using normal addition and a mask. The mask
+ should be the sign bit of each lane. This 6-operation form is more
+ efficient than separate additions when there are 4 or more lanes in
+ the 64-bit operation. */
+static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_andc_i64(t1, a, m);
+ tcg_gen_andc_i64(t2, b, m);
+ tcg_gen_xor_i64(t3, a, b);
+ tcg_gen_add_i64(d, t1, t2);
+ tcg_gen_and_i64(t3, t3, m);
+ tcg_gen_xor_i64(d, d, t3);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP8(0x80));
+ gen_addv_mask(d, a, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP16(0x8000));
+ gen_addv_mask(d, a, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(t1, a, ~0xffffffffull);
+ tcg_gen_add_i64(t2, a, b);
+ tcg_gen_add_i64(t1, t1, b);
+ tcg_gen_deposit_i64(d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = tcg_gen_vec_add8_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add8,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_add16_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add16,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_add_i32,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add32,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_add_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add64,
+ .opc = INDEX_op_add_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+/* Perform a vector subtraction using normal subtraction and a mask.
+ Compare gen_addv_mask above. */
+static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_or_i64(t1, a, m);
+ tcg_gen_andc_i64(t2, b, m);
+ tcg_gen_eqv_i64(t3, a, b);
+ tcg_gen_sub_i64(d, t1, t2);
+ tcg_gen_and_i64(t3, t3, m);
+ tcg_gen_xor_i64(d, d, t3);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP8(0x80));
+ gen_subv_mask(d, a, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP16(0x8000));
+ gen_subv_mask(d, a, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(t1, b, ~0xffffffffull);
+ tcg_gen_sub_i64(t2, a, b);
+ tcg_gen_sub_i64(t1, a, t1);
+ tcg_gen_deposit_i64(d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = tcg_gen_vec_sub8_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub8,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_sub16_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub16,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_sub_i32,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub32,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_sub_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub64,
+ .opc = INDEX_op_sub_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+/* Perform a vector negation using normal negation and a mask.
+ Compare gen_subv_mask above. */
+static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_andc_i64(t3, m, b);
+ tcg_gen_andc_i64(t2, b, m);
+ tcg_gen_sub_i64(d, m, t2);
+ tcg_gen_xor_i64(d, d, t3);
+
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP8(0x80));
+ gen_negv_mask(d, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP16(0x8000));
+ gen_negv_mask(d, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(t1, b, ~0xffffffffull);
+ tcg_gen_neg_i64(t2, b);
+ tcg_gen_neg_i64(t1, t1);
+ tcg_gen_deposit_i64(d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2 g[4] = {
+ { .fni8 = tcg_gen_vec_neg8_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg8,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_neg16_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg16,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_neg_i32,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg32,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_neg_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg64,
+ .opc = INDEX_op_neg_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]);
+}
+
+void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_and_i64,
+ .fniv = tcg_gen_and_vec,
+ .fno = gen_helper_gvec_and,
+ .opc = INDEX_op_and_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_or_i64,
+ .fniv = tcg_gen_or_vec,
+ .fno = gen_helper_gvec_or,
+ .opc = INDEX_op_or_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_xor_i64,
+ .fniv = tcg_gen_xor_vec,
+ .fno = gen_helper_gvec_xor,
+ .opc = INDEX_op_xor_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_andc_i64,
+ .fniv = tcg_gen_andc_vec,
+ .fno = gen_helper_gvec_andc,
+ .opc = INDEX_op_andc_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_orc_i64,
+ .fniv = tcg_gen_orc_vec,
+ .fno = gen_helper_gvec_orc,
+ .opc = INDEX_op_orc_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
+}
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index dc04c11860..5cfe4af6bd 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -104,7 +104,7 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
-static void tcg_gen_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
+static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
{
TCGTemp *rt = tcgv_vec_temp(r);
vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
@@ -113,14 +113,14 @@ static void tcg_gen_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
TCGv_vec tcg_const_zeros_vec(TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(ret, MO_REG, 0);
+ do_dupi_vec(ret, MO_REG, 0);
return ret;
}
TCGv_vec tcg_const_ones_vec(TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(ret, MO_REG, -1);
+ do_dupi_vec(ret, MO_REG, -1);
return ret;
}
@@ -139,9 +139,9 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
{
if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
- tcg_gen_dupi_vec(r, MO_32, a);
+ do_dupi_vec(r, MO_32, a);
} else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
- tcg_gen_dupi_vec(r, MO_64, a);
+ do_dupi_vec(r, MO_64, a);
} else {
TCGv_i64 c = tcg_const_i64(a);
tcg_gen_dup_i64_vec(MO_64, r, c);
@@ -151,17 +151,37 @@ void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
+ do_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
}
void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
+ do_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
}
void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
+ do_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
+}
+
+void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
+{
+ switch (vece) {
+ case MO_8:
+ tcg_gen_dup8i_vec(r, a);
+ break;
+ case MO_16:
+ tcg_gen_dup16i_vec(r, a);
+ break;
+ case MO_32:
+ tcg_gen_dup32i_vec(r, a);
+ break;
+ case MO_64:
+ tcg_gen_dup64i_vec(r, a);
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
void tcg_gen_movi_v64(TCGv_vec r, uint64_t a)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 16b8faf66f..b4f8938fb0 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1404,10 +1404,10 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
- case NB_OPS:
- break;
+ default:
+ tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
+ return true;
}
- g_assert_not_reached();
}
/* Note: we convert the 64 bit args to 32 bit and do some alignment
@@ -3737,3 +3737,10 @@ void tcg_register_jit(void *buf, size_t buf_size)
{
}
#endif /* ELF_HOST_MACHINE */
+
+#if !TCG_TARGET_MAYBE_vec
+void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...)
+{
+ g_assert_not_reached();
+}
+#endif
diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs
index 228cd84fa4..d381a02f34 100644
--- a/accel/tcg/Makefile.objs
+++ b/accel/tcg/Makefile.objs
@@ -1,6 +1,6 @@
obj-$(CONFIG_SOFTMMU) += tcg-all.o
obj-$(CONFIG_SOFTMMU) += cputlb.o
-obj-y += tcg-runtime.o
+obj-y += tcg-runtime.o tcg-runtime-gvec.o
obj-y += cpu-exec.o cpu-exec-common.o translate-all.o
obj-y += translator.o
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 05/26] tcg: Add generic vector ops for interleave
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (3 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 04/26] tcg: Add generic vector expanders Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 06/26] tcg: Add generic vector ops for constant shifts Richard Henderson
` (23 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Includes zip, unzip, and transform.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 15 +++
tcg/tcg-op-gvec.h | 13 ++
tcg/tcg-op.h | 6 +
tcg/tcg-opc.h | 7 +
tcg/tcg.h | 3 +
accel/tcg/tcg-runtime-gvec.c | 78 ++++++++++++
tcg/tcg-op-gvec.c | 297 +++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 55 ++++++++
tcg/tcg.c | 9 ++
tcg/README | 40 ++++++
10 files changed, 523 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 76ee41ce58..c6de749134 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -163,3 +163,18 @@ DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_zip8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_zip16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_zip32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_zip64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_uzp8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_uzp16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_uzp32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_uzp64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_trn8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_trn16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_trn32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_trn64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 57285ec293..f4afcd258e 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -179,6 +179,19 @@ void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
+void tcg_gen_gvec_zipl(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_ziph(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_uzpe(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_uzpo(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_trne(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+
/*
* 64-bit vector operations. Use these when the register has been allocated
* with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 09fec5693f..87be11a90d 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -927,6 +927,12 @@ void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_zipl_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_ziph_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_uzpe_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_uzpo_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_trne_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index b4e16cfbc3..c911d62442 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -229,6 +229,13 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+DEF(zipl_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_zip_vec))
+DEF(ziph_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_zip_vec))
+DEF(uzpe_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
+DEF(uzpo_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
+DEF(trne_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
+DEF(trno_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
+
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#if TCG_TARGET_MAYBE_vec
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 5560e6439a..bccdaa5eca 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -178,6 +178,9 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_zip_vec 0
+#define TCG_TARGET_HAS_uzp_vec 0
+#define TCG_TARGET_HAS_trn_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index cd1ce12b7e..628df811b2 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -293,3 +293,81 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
}
clear_high(d, oprsz, desc);
}
+
+/* The size of the alloca in the following is currently bounded to 2k. */
+
+#define DO_ZIP(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t oprsz_2 = oprsz / 2; \
+ intptr_t i; \
+ /* We produce output faster than we consume input. \
+ Therefore we must be mindful of possible overlap. */ \
+ if (unlikely((a - d) < (uintptr_t)oprsz)) { \
+ void *a_new = alloca(oprsz_2); \
+ memcpy(a_new, a, oprsz_2); \
+ a = a_new; \
+ } \
+ if (unlikely((b - d) < (uintptr_t)oprsz)) { \
+ void *b_new = alloca(oprsz_2); \
+ memcpy(b_new, b, oprsz_2); \
+ b = b_new; \
+ } \
+ for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
+ *(TYPE *)(d + 2 * i + 0) = *(TYPE *)(a + i); \
+ *(TYPE *)(d + 2 * i + sizeof(TYPE)) = *(TYPE *)(b + i); \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+DO_ZIP(gvec_zip8, uint8_t)
+DO_ZIP(gvec_zip16, uint16_t)
+DO_ZIP(gvec_zip32, uint32_t)
+DO_ZIP(gvec_zip64, uint64_t)
+
+#define DO_UZP(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t oprsz_2 = oprsz / 2; \
+ intptr_t odd_ofs = simd_data(desc); \
+ intptr_t i; \
+ if (unlikely((b - d) < (uintptr_t)oprsz)) { \
+ void *b_new = alloca(oprsz); \
+ memcpy(b_new, b, oprsz); \
+ b = b_new; \
+ } \
+ for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
+ *(TYPE *)(d + i) = *(TYPE *)(a + 2 * i + odd_ofs); \
+ } \
+ for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
+ *(TYPE *)(d + oprsz_2 + i) = *(TYPE *)(b + 2 * i + odd_ofs); \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+DO_UZP(gvec_uzp8, uint8_t)
+DO_UZP(gvec_uzp16, uint16_t)
+DO_UZP(gvec_uzp32, uint32_t)
+DO_UZP(gvec_uzp64, uint64_t)
+
+#define DO_TRN(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t odd_ofs = simd_data(desc); \
+ intptr_t i; \
+ for (i = 0; i < oprsz; i += 2 * sizeof(TYPE)) { \
+ TYPE ae = *(TYPE *)(a + i + odd_ofs); \
+ TYPE be = *(TYPE *)(b + i + odd_ofs); \
+ *(TYPE *)(d + i + 0) = ae; \
+ *(TYPE *)(d + i + sizeof(TYPE)) = be; \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+DO_TRN(gvec_trn8, uint8_t)
+DO_TRN(gvec_trn16, uint16_t)
+DO_TRN(gvec_trn32, uint32_t)
+DO_TRN(gvec_trn64, uint64_t)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 206ae16b19..18f5da2c8b 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1293,3 +1293,300 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
};
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
+
+static void do_zip(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz,
+ bool high)
+{
+ static gen_helper_gvec_3 * const zip_fns[4] = {
+ gen_helper_gvec_zip8,
+ gen_helper_gvec_zip16,
+ gen_helper_gvec_zip32,
+ gen_helper_gvec_zip64,
+ };
+
+ TCGType type;
+ uint32_t step, i, n;
+ TCGOpcode zip_op;
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, oprsz);
+ tcg_debug_assert(vece <= MO_64);
+
+ zip_op = high ? INDEX_op_ziph_vec : INDEX_op_zipl_vec;
+
+ /* Since these operations don't operate in lock-step lanes,
+ we must care for overlap. */
+ if (TCG_TARGET_HAS_v256 && oprsz % 32 == 0 && oprsz / 32 <= 8
+ && tcg_can_emit_vec_op(zip_op, TCG_TYPE_V256, vece)) {
+ type = TCG_TYPE_V256;
+ step = 32;
+ n = oprsz / 32;
+ } else if (TCG_TARGET_HAS_v128 && oprsz % 16 == 0 && oprsz / 16 <= 8
+ && tcg_can_emit_vec_op(zip_op, TCG_TYPE_V128, vece)) {
+ type = TCG_TYPE_V128;
+ step = 16;
+ n = oprsz / 16;
+ } else if (TCG_TARGET_HAS_v64 && oprsz % 8 == 0 && oprsz / 8 <= 8
+ && tcg_can_emit_vec_op(zip_op, TCG_TYPE_V64, vece)) {
+ type = TCG_TYPE_V64;
+ step = 8;
+ n = oprsz / 8;
+ } else {
+ if (high) {
+ aofs += oprsz / 2;
+ bofs += oprsz / 2;
+ }
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, zip_fns[vece]);
+ return;
+ }
+
+ if (n == 1) {
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+
+ tcg_gen_ld_vec(t1, cpu_env, aofs);
+ tcg_gen_ld_vec(t2, cpu_env, bofs);
+ if (high) {
+ tcg_gen_ziph_vec(vece, t1, t1, t2);
+ } else {
+ tcg_gen_zipl_vec(vece, t1, t1, t2);
+ }
+ tcg_gen_st_vec(t1, cpu_env, dofs);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ } else {
+ TCGv_vec ta[4], tb[4], tmp;
+
+ if (high) {
+ aofs += oprsz / 2;
+ bofs += oprsz / 2;
+ }
+
+ for (i = 0; i < (n / 2 + n % 2); ++i) {
+ ta[i] = tcg_temp_new_vec(type);
+ tb[i] = tcg_temp_new_vec(type);
+ tcg_gen_ld_vec(ta[i], cpu_env, aofs + i * step);
+ tcg_gen_ld_vec(tb[i], cpu_env, bofs + i * step);
+ }
+
+ tmp = tcg_temp_new_vec(type);
+ for (i = 0; i < n; ++i) {
+ if (i & 1) {
+ tcg_gen_ziph_vec(vece, tmp, ta[i / 2], tb[i / 2]);
+ } else {
+ tcg_gen_zipl_vec(vece, tmp, ta[i / 2], tb[i / 2]);
+ }
+ tcg_gen_st_vec(tmp, cpu_env, dofs + i * step);
+ }
+ tcg_temp_free_vec(tmp);
+
+ for (i = 0; i < (n / 2 + n % 2); ++i) {
+ tcg_temp_free_vec(ta[i]);
+ tcg_temp_free_vec(tb[i]);
+ }
+ }
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+void tcg_gen_gvec_zipl(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ do_zip(vece, dofs, aofs, bofs, oprsz, maxsz, false);
+}
+
+void tcg_gen_gvec_ziph(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ do_zip(vece, dofs, aofs, bofs, oprsz, maxsz, true);
+}
+
+static void do_uzp(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz, bool odd)
+{
+ static gen_helper_gvec_3 * const uzp_fns[4] = {
+ gen_helper_gvec_uzp8,
+ gen_helper_gvec_uzp16,
+ gen_helper_gvec_uzp32,
+ gen_helper_gvec_uzp64,
+ };
+
+ TCGType type;
+ uint32_t step, i, n;
+ TCGv_vec t[8];
+ TCGOpcode uzp_op;
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, oprsz);
+ tcg_debug_assert(vece <= MO_64);
+
+ uzp_op = odd ? INDEX_op_uzpo_vec : INDEX_op_uzpe_vec;
+
+ /* Since these operations don't operate in lock-step lanes,
+ we must care for overlap. */
+ if (TCG_TARGET_HAS_v256 && oprsz % 32 == 0 && oprsz / 32 <= 4
+ && tcg_can_emit_vec_op(uzp_op, TCG_TYPE_V256, vece)) {
+ type = TCG_TYPE_V256;
+ step = 32;
+ n = oprsz / 32;
+ } else if (TCG_TARGET_HAS_v128 && oprsz % 16 == 0 && oprsz / 16 <= 4
+ && tcg_can_emit_vec_op(uzp_op, TCG_TYPE_V128, vece)) {
+ type = TCG_TYPE_V128;
+ step = 16;
+ n = oprsz / 16;
+ } else if (TCG_TARGET_HAS_v64 && oprsz % 8 == 0 && oprsz / 8 <= 4
+ && tcg_can_emit_vec_op(uzp_op, TCG_TYPE_V64, vece)) {
+ type = TCG_TYPE_V64;
+ step = 8;
+ n = oprsz / 8;
+ } else {
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz,
+ (1 << vece) * odd, uzp_fns[vece]);
+ return;
+ }
+
+ for (i = 0; i < n; ++i) {
+ t[i] = tcg_temp_new_vec(type);
+ tcg_gen_ld_vec(t[i], cpu_env, aofs + i * step);
+ }
+ for (i = 0; i < n; ++i) {
+ t[n + i] = tcg_temp_new_vec(type);
+ tcg_gen_ld_vec(t[n + i], cpu_env, bofs + i * step);
+ }
+ for (i = 0; i < n; ++i) {
+ if (odd) {
+ tcg_gen_uzpo_vec(vece, t[2 * i], t[2 * i], t[2 * i + 1]);
+ } else {
+ tcg_gen_uzpe_vec(vece, t[2 * i], t[2 * i], t[2 * i + 1]);
+ }
+ tcg_gen_st_vec(t[2 * i], cpu_env, dofs + i * step);
+ tcg_temp_free_vec(t[2 * i]);
+ tcg_temp_free_vec(t[2 * i + 1]);
+ }
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+void tcg_gen_gvec_uzpe(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ do_uzp(vece, dofs, aofs, bofs, oprsz, maxsz, false);
+}
+
+void tcg_gen_gvec_uzpo(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ do_uzp(vece, dofs, aofs, bofs, oprsz, maxsz, true);
+}
+
+static void gen_trne8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ uint64_t m = 0x00ff00ff00ff00ffull;
+ tcg_gen_andi_i64(a, a, m);
+ tcg_gen_andi_i64(b, b, m);
+ tcg_gen_shli_i64(b, b, 8);
+ tcg_gen_or_i64(d, a, b);
+}
+
+static void gen_trne16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ uint64_t m = 0x0000ffff0000ffffull;
+ tcg_gen_andi_i64(a, a, m);
+ tcg_gen_andi_i64(b, b, m);
+ tcg_gen_shli_i64(b, b, 16);
+ tcg_gen_or_i64(d, a, b);
+}
+
+static void gen_trne32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_deposit_i64(d, a, b, 32, 32);
+}
+
+void tcg_gen_gvec_trne(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = gen_trne8_i64,
+ .fniv = tcg_gen_trne_vec,
+ .fno = gen_helper_gvec_trn8,
+ .opc = INDEX_op_trne_vec,
+ .vece = MO_8 },
+ { .fni8 = gen_trne16_i64,
+ .fniv = tcg_gen_trne_vec,
+ .fno = gen_helper_gvec_trn16,
+ .opc = INDEX_op_trne_vec,
+ .vece = MO_16 },
+ { .fni8 = gen_trne32_i64,
+ .fniv = tcg_gen_trne_vec,
+ .fno = gen_helper_gvec_trn32,
+ .opc = INDEX_op_trne_vec,
+ .vece = MO_32 },
+ { .fniv = tcg_gen_trne_vec,
+ .fno = gen_helper_gvec_trn64,
+ .opc = INDEX_op_trne_vec,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+static void gen_trno8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ uint64_t m = 0xff00ff00ff00ff00ull;
+ tcg_gen_andi_i64(a, a, m);
+ tcg_gen_andi_i64(b, b, m);
+ tcg_gen_shri_i64(a, a, 8);
+ tcg_gen_or_i64(d, a, b);
+}
+
+static void gen_trno16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ uint64_t m = 0xffff0000ffff0000ull;
+ tcg_gen_andi_i64(a, a, m);
+ tcg_gen_andi_i64(b, b, m);
+ tcg_gen_shri_i64(a, a, 16);
+ tcg_gen_or_i64(d, a, b);
+}
+
+static void gen_trno32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_shri_i64(a, a, 32);
+ tcg_gen_deposit_i64(d, b, a, 0, 32);
+}
+
+void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = gen_trno8_i64,
+ .fniv = tcg_gen_trno_vec,
+ .fno = gen_helper_gvec_trn8,
+ .opc = INDEX_op_trno_vec,
+ .data = 1,
+ .vece = MO_8 },
+ { .fni8 = gen_trno16_i64,
+ .fniv = tcg_gen_trno_vec,
+ .fno = gen_helper_gvec_trn16,
+ .opc = INDEX_op_trno_vec,
+ .data = 2,
+ .vece = MO_16 },
+ { .fni8 = gen_trno32_i64,
+ .fniv = tcg_gen_trno_vec,
+ .fno = gen_helper_gvec_trn32,
+ .opc = INDEX_op_trno_vec,
+ .data = 4,
+ .vece = MO_32 },
+ { .fniv = tcg_gen_trno_vec,
+ .fno = gen_helper_gvec_trn64,
+ .opc = INDEX_op_trno_vec,
+ .data = 8,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 5cfe4af6bd..a5d0ff89c3 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -380,3 +380,58 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
tcg_temp_free_vec(t);
}
}
+
+static void do_interleave(TCGOpcode opc, unsigned vece,
+ TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGTemp *bt = tcgv_vec_temp(b);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGArg bi = temp_arg(bt);
+ TCGType type = rt->base_type;
+ unsigned vecl = type - TCG_TYPE_V64;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(bt->base_type == type);
+ tcg_debug_assert((8 << vece) <= (32 << vecl));
+ can = tcg_can_emit_vec_op(opc, type, vece);
+ if (can > 0) {
+ vec_gen_3(opc, type, vece, ri, ai, bi);
+ } else {
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(opc, type, vece, ri, ai, bi);
+ }
+}
+
+void tcg_gen_zipl_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_zipl_vec, vece, r, a, b);
+}
+
+void tcg_gen_ziph_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_ziph_vec, vece, r, a, b);
+}
+
+void tcg_gen_uzpe_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_uzpe_vec, vece, r, a, b);
+}
+
+void tcg_gen_uzpo_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_uzpo_vec, vece, r, a, b);
+}
+
+void tcg_gen_trne_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_trne_vec, vece, r, a, b);
+}
+
+void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_trno_vec, vece, r, a, b);
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index b4f8938fb0..33e3c03cbc 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1403,6 +1403,15 @@ bool tcg_op_supported(TCGOpcode op)
return have_vec && TCG_TARGET_HAS_andc_vec;
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
+ case INDEX_op_zipl_vec:
+ case INDEX_op_ziph_vec:
+ return have_vec && TCG_TARGET_HAS_zip_vec;
+ case INDEX_op_uzpe_vec:
+ case INDEX_op_uzpo_vec:
+ return have_vec && TCG_TARGET_HAS_uzp_vec;
+ case INDEX_op_trne_vec:
+ case INDEX_op_trno_vec:
+ return have_vec && TCG_TARGET_HAS_trn_vec;
default:
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
diff --git a/tcg/README b/tcg/README
index e14990fb9b..8ab8d3ab7e 100644
--- a/tcg/README
+++ b/tcg/README
@@ -561,6 +561,46 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
Similarly, logical operations with and without compliment.
Note that VECE is unused.
+* zipl_vec v0, v1, v2
+* ziph_vec v0, v1, v2
+
+ "Zip" two vectors together, either the low half of v1/v2 or the high half.
+ The name comes from ARM ARM; the equivalent function in Intel terminology
+ is the less scrutable "punpck". The effect is
+
+ part = ("high" ? VECL/VECE/2 : 0);
+ for (i = 0; i < VECL/VECE/2; ++i) {
+ v0[2i + 0] = v1[i + part];
+ v0[2i + 1] = v2[i + part];
+ }
+
+* uzpe_vec v0, v1, v2
+* uzpo_vec v0, v1, v2
+
+ "Unzip" two vectors, either the even elements or the odd elements.
+ If v1 and v2 are the result of zipl and ziph, this performs the
+ inverse operation. The effect is
+
+ part = ("odd" ? 1 : 0)
+ for (i = 0; i < VECL/VECE/2; ++i) {
+ v0[i] = v1[2i + part];
+ }
+ for (i = 0; i < VECL/VECE/2; ++i) {
+ v0[i + VECL/VECE/2] = v1[2i + part];
+ }
+
+* trne_vec v0, v1, v2
+* trno_vec v1, v1, v2
+
+ "Transpose" two vectors, either the even elements or the odd elements.
+ The effect is
+
+ part = ("odd" ? 1 : 0)
+ for (i = 0; i < VECL/VECE/2; ++i) {
+ v0[2i + 0] = v1[2i + part];
+ v0[2i + 1] = v2[2i + part];
+ }
+
*********
Note 1: Some shortcuts are defined when the last operand is known to be
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 06/26] tcg: Add generic vector ops for constant shifts
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (4 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 05/26] tcg: Add generic vector ops for interleave Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 07/26] tcg: Add generic vector ops for comparisons Richard Henderson
` (22 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Opcodes are added for scalar and vector shifts, but considering the
varied semantics of these do not expose them to the front ends. Do
go ahead and provide them in case they are needed for backend expansion.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 15 +++
tcg/tcg-op-gvec.h | 35 ++++++
tcg/tcg-op.h | 5 +
tcg/tcg-opc.h | 12 ++
tcg/tcg.h | 3 +
accel/tcg/tcg-runtime-gvec.c | 149 ++++++++++++++++++++++++
tcg/tcg-op-gvec.c | 272 +++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 45 +++++++
tcg/tcg.c | 12 ++
tcg/README | 29 +++++
10 files changed, 577 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index c6de749134..cb05a755b8 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -164,6 +164,21 @@ DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_shr8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shr16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shr32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shr64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_sar8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(gvec_zip8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_zip16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_zip32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index f4afcd258e..08f9c5556c 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -95,6 +95,25 @@ typedef struct {
bool prefer_i64;
} GVecGen2;
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGv_i64, TCGv_i64, int64_t);
+ void (*fni4)(TCGv_i32, TCGv_i32, int32_t);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_2 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+ /* Load dest as a 3rd source operand. */
+ bool load_dest;
+} GVecGen2i;
+
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
@@ -137,6 +156,8 @@ typedef struct {
void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
+void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ uint32_t maxsz, int64_t c, const GVecGen2i *);
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
@@ -179,6 +200,13 @@ void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
+void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, unsigned shift);
+void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, unsigned shift);
+void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, unsigned shift);
+
void tcg_gen_gvec_zipl(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_ziph(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -209,3 +237,10 @@ void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+
+void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
+void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
+void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
+void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
+void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
+void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 87be11a90d..c002523bea 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -927,6 +927,11 @@ void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+
+void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
+void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
+void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
+
void tcg_gen_zipl_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_ziph_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_uzpe_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index c911d62442..a085fc077b 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -229,6 +229,18 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
+DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
+DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
+
+DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
+DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
+DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
+
+DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
+DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
+DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
+
DEF(zipl_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_zip_vec))
DEF(ziph_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_zip_vec))
DEF(uzpe_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
diff --git a/tcg/tcg.h b/tcg/tcg.h
index bccdaa5eca..49ee07b02e 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -178,6 +178,9 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_zip_vec 0
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 628df811b2..fba62f1192 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -36,6 +36,11 @@ typedef uint16_t vec16 __attribute__((vector_size(16)));
typedef uint32_t vec32 __attribute__((vector_size(16)));
typedef uint64_t vec64 __attribute__((vector_size(16)));
+typedef int8_t svec8 __attribute__((vector_size(16)));
+typedef int16_t svec16 __attribute__((vector_size(16)));
+typedef int32_t svec32 __attribute__((vector_size(16)));
+typedef int64_t svec64 __attribute__((vector_size(16)));
+
static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
{
intptr_t maxsz = simd_maxsz(desc);
@@ -294,6 +299,150 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_shl8i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shl16i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) << shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shl32i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) << shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shl64i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) << shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shr8i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shr16i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shr32i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shr64i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sar8i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(svec8 *)(d + i) = *(svec8 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sar16i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(svec16 *)(d + i) = *(svec16 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sar32i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(svec32 *)(d + i) = *(svec32 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(svec64 *)(d + i) = *(svec64 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
/* The size of the alloca in the following is currently bounded to 2k. */
#define DO_ZIP(NAME, TYPE) \
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 18f5da2c8b..4210b6787a 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -534,6 +534,26 @@ static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
tcg_temp_free_i32(t0);
}
+static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ int32_t c, bool load_dest,
+ void (*fni)(TCGv_i32, TCGv_i32, int32_t))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i32(t1, cpu_env, dofs + i);
+ }
+ fni(t1, t0, c);
+ tcg_gen_st_i32(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
static void expand_3_i32(uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, bool load_dest,
@@ -597,6 +617,26 @@ static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
tcg_temp_free_i64(t0);
}
+static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ int64_t c, bool load_dest,
+ void (*fni)(TCGv_i64, TCGv_i64, int64_t))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i64(t1, cpu_env, dofs + i);
+ }
+ fni(t1, t0, c);
+ tcg_gen_st_i64(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
static void expand_3_i64(uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, bool load_dest,
@@ -661,6 +701,29 @@ static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_temp_free_vec(t0);
}
+/* Expand OPSZ bytes worth of two-vector operands and an immediate operand
+ using host vectors. */
+static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t tysz, TCGType type,
+ int64_t c, bool load_dest,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec, int64_t))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ if (load_dest) {
+ tcg_gen_ld_vec(t1, cpu_env, dofs + i);
+ }
+ fni(vece, t1, t0, c);
+ tcg_gen_st_vec(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t0);
+ tcg_temp_free_vec(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz,
@@ -760,6 +823,51 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
}
}
+void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ uint32_t maxsz, int64_t c, const GVecGen2i *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs);
+ check_overlap_2(dofs, aofs, maxsz);
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+
+ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_2i_vec(g->vece, dofs, aofs, done, 32, TCG_TYPE_V256,
+ c, g->load_dest, g->fniv);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
+ expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
+ c, g->load_dest, g->fniv);
+ } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && g->fniv && check_size_impl(oprsz, 8)
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
+ expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
+ c, g->load_dest, g->fniv);
+ } else if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_2i_i64(dofs, aofs, oprsz, c, g->load_dest, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4);
+ } else {
+ tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno);
+ return;
+ }
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
/* Expand a vector three-operand operation. */
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
@@ -1294,6 +1402,170 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
+void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+{
+ uint64_t mask = ((0xff << c) & 0xff) * (-1ull / 0xff);
+ tcg_gen_shli_i64(d, a, c);
+ tcg_gen_andi_i64(d, d, mask);
+}
+
+void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+{
+ uint64_t mask = ((0xffff << c) & 0xffff) * (-1ull / 0xffff);
+ tcg_gen_shli_i64(d, a, c);
+ tcg_gen_andi_i64(d, d, mask);
+}
+
+void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, unsigned shift)
+{
+ static const GVecGen2i g[4] = {
+ { .fni8 = tcg_gen_vec_shl8i_i64,
+ .fniv = tcg_gen_shli_vec,
+ .fno = gen_helper_gvec_shl8i,
+ .opc = INDEX_op_shli_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_shl16i_i64,
+ .fniv = tcg_gen_shli_vec,
+ .fno = gen_helper_gvec_shl16i,
+ .opc = INDEX_op_shli_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_shli_i32,
+ .fniv = tcg_gen_shli_vec,
+ .fno = gen_helper_gvec_shl32i,
+ .opc = INDEX_op_shli_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_shli_i64,
+ .fniv = tcg_gen_shli_vec,
+ .fno = gen_helper_gvec_shl64i,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_debug_assert(shift < (8 << vece));
+ if (shift == 0) {
+ tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
+ } else {
+ tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
+ }
+}
+
+void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+{
+ uint64_t mask = (0xff >> c) * (-1ull / 0xff);
+ tcg_gen_shri_i64(d, a, c);
+ tcg_gen_andi_i64(d, d, mask);
+}
+
+void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+{
+ uint64_t mask = (0xffff >> c) * (-1ull / 0xffff);
+ tcg_gen_shri_i64(d, a, c);
+ tcg_gen_andi_i64(d, d, mask);
+}
+
+void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, unsigned shift)
+{
+ static const GVecGen2i g[4] = {
+ { .fni8 = tcg_gen_vec_shr8i_i64,
+ .fniv = tcg_gen_shri_vec,
+ .fno = gen_helper_gvec_shr8i,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_shr16i_i64,
+ .fniv = tcg_gen_shri_vec,
+ .fno = gen_helper_gvec_shr16i,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_shri_i32,
+ .fniv = tcg_gen_shri_vec,
+ .fno = gen_helper_gvec_shr32i,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_shri_i64,
+ .fniv = tcg_gen_shri_vec,
+ .fno = gen_helper_gvec_shr64i,
+ .opc = INDEX_op_shri_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_debug_assert(shift < (8 << vece));
+ if (shift == 0) {
+ tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
+ } else {
+ tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
+ }
+}
+
+void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+{
+ uint64_t s_mask = (0x80 >> c) * (-1ull / 0xff);
+ uint64_t c_mask = (0xff >> c) * (-1ull / 0xff);
+ TCGv_i64 s = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(d, a, c);
+ tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */
+ tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */
+ tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */
+ tcg_gen_or_i64(d, d, s); /* include sign extension */
+ tcg_temp_free_i64(s);
+}
+
+void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
+{
+ uint64_t s_mask = (0x8000 >> c) * (-1ull / 0xffff);
+ uint64_t c_mask = (0xffff >> c) * (-1ull / 0xffff);
+ TCGv_i64 s = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(d, a, c);
+ tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */
+ tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */
+ tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */
+ tcg_gen_or_i64(d, d, s); /* include sign extension */
+ tcg_temp_free_i64(s);
+}
+
+void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, unsigned shift)
+{
+ static const GVecGen2i g[4] = {
+ { .fni8 = tcg_gen_vec_sar8i_i64,
+ .fniv = tcg_gen_sari_vec,
+ .fno = gen_helper_gvec_sar8i,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_sar16i_i64,
+ .fniv = tcg_gen_sari_vec,
+ .fno = gen_helper_gvec_sar16i,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_sari_i32,
+ .fniv = tcg_gen_sari_vec,
+ .fno = gen_helper_gvec_sar32i,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_sari_i64,
+ .fniv = tcg_gen_sari_vec,
+ .fno = gen_helper_gvec_sar64i,
+ .opc = INDEX_op_sari_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_debug_assert(shift < (8 << vece));
+ if (shift == 0) {
+ tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz);
+ } else {
+ tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]);
+ }
+}
+
static void do_zip(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz,
bool high)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index a5d0ff89c3..b54d3de19f 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -381,6 +381,51 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
}
}
+static void do_shifti(TCGOpcode opc, unsigned vece,
+ TCGv_vec r, TCGv_vec a, int64_t i)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGType type = rt->base_type;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(i >= 0 && i < (8 << vece));
+
+ if (i == 0) {
+ tcg_gen_mov_vec(r, a);
+ return;
+ }
+
+ can = tcg_can_emit_vec_op(opc, type, vece);
+ if (can > 0) {
+ vec_gen_3(opc, type, vece, ri, ai, i);
+ } else {
+ /* We leave the choice of expansion via scalar or vector shift
+ to the target. Often, but not always, dupi can feed a vector
+ shift easier than a scalar. */
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(opc, type, vece, ri, ai, i);
+ }
+}
+
+void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
+{
+ do_shifti(INDEX_op_shli_vec, vece, r, a, i);
+}
+
+void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
+{
+ do_shifti(INDEX_op_shri_vec, vece, r, a, i);
+}
+
+void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
+{
+ do_shifti(INDEX_op_sari_vec, vece, r, a, i);
+}
+
static void do_interleave(TCGOpcode opc, unsigned vece,
TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 33e3c03cbc..f82d6e80b0 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1403,6 +1403,18 @@ bool tcg_op_supported(TCGOpcode op)
return have_vec && TCG_TARGET_HAS_andc_vec;
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ return have_vec && TCG_TARGET_HAS_shi_vec;
+ case INDEX_op_shls_vec:
+ case INDEX_op_shrs_vec:
+ case INDEX_op_sars_vec:
+ return have_vec && TCG_TARGET_HAS_shs_vec;
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ return have_vec && TCG_TARGET_HAS_shv_vec;
case INDEX_op_zipl_vec:
case INDEX_op_ziph_vec:
return have_vec && TCG_TARGET_HAS_zip_vec;
diff --git a/tcg/README b/tcg/README
index 8ab8d3ab7e..75db47922d 100644
--- a/tcg/README
+++ b/tcg/README
@@ -561,6 +561,35 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
Similarly, logical operations with and without compliment.
Note that VECE is unused.
+* shli_vec v0, v1, i2
+* shls_vec v0, v1, s2
+
+ Shift all elements from v1 by a scalar i2/s2. I.e.
+
+ for (i = 0; i < VECL/VECE; ++i) {
+ v0[i] = v1[i] << s2;
+ }
+
+* shri_vec v0, v1, i2
+* sari_vec v0, v1, i2
+* shrs_vec v0, v1, s2
+* sars_vec v0, v1, s2
+
+ Similarly for logical and arithmetic right shift.
+
+* shlv_vec v0, v1, v2
+
+ Shift elements from v1 by elements from v2. I.e.
+
+ for (i = 0; i < VECL/VECE; ++i) {
+ v0[i] = v1[i] << v2[i];
+ }
+
+* shrv_vec v0, v1, v2
+* sarv_vec v0, v1, v2
+
+ Similarly for logical and arithmetic right shift.
+
* zipl_vec v0, v1, v2
* ziph_vec v0, v1, v2
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 07/26] tcg: Add generic vector ops for comparisons
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (5 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 06/26] tcg: Add generic vector ops for constant shifts Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 08/26] tcg: Add generic vector ops for multiplication Richard Henderson
` (21 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 30 +++++++++
tcg/tcg-op-gvec.h | 4 ++
tcg/tcg-op.h | 3 +
tcg/tcg-opc.h | 2 +
tcg/tcg.h | 1 +
accel/tcg/tcg-runtime-gvec.c | 24 +++++++
tcg/tcg-op-gvec.c | 147 +++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 23 +++++++
tcg/tcg.c | 2 +
tcg/README | 4 ++
10 files changed, 240 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index cb05a755b8..28abf30d76 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -193,3 +193,33 @@ DEF_HELPER_FLAGS_4(gvec_trn8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_eq64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_ne8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ne16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ne32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ne64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_lt8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_lt16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_lt32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_lt64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_le8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_le16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_le32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_le64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_ltu8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ltu16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ltu32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ltu64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_leu8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_leu16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_leu32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_leu64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 08f9c5556c..f17b34d896 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -220,6 +220,10 @@ void tcg_gen_gvec_trne(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
+ uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz);
+
/*
* 64-bit vector operations. Use these when the register has been allocated
* with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index c002523bea..777db6ad59 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -939,6 +939,9 @@ void tcg_gen_uzpo_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_trne_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
+ TCGv_vec a, TCGv_vec b);
+
void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index a085fc077b..d3fa014507 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -248,6 +248,8 @@ DEF(uzpo_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
DEF(trne_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
DEF(trno_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
+DEF(cmp_vec, 1, 2, 1, IMPLVEC)
+
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#if TCG_TARGET_MAYBE_vec
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 49ee07b02e..b3c94f59f3 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -184,6 +184,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_zip_vec 0
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
+#define TCG_TARGET_HAS_cmp_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index fba62f1192..e0cde3216f 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -520,3 +520,27 @@ DO_TRN(gvec_trn8, uint8_t)
DO_TRN(gvec_trn16, uint16_t)
DO_TRN(gvec_trn32, uint32_t)
DO_TRN(gvec_trn64, uint64_t)
+
+#define DO_CMP1(NAME, TYPE, OP) \
+void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t i; \
+ for (i = 0; i < oprsz; i += sizeof(vec64)) { \
+ *(TYPE *)(d + i) = *(TYPE *)(a + i) OP *(TYPE *)(b + i); \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+#define DO_CMP2(SZ) \
+ DO_CMP1(gvec_eq##SZ, vec##SZ, ==) \
+ DO_CMP1(gvec_ne##SZ, vec##SZ, !=) \
+ DO_CMP1(gvec_lt##SZ, svec##SZ, <) \
+ DO_CMP1(gvec_le##SZ, svec##SZ, <=) \
+ DO_CMP1(gvec_ltu##SZ, vec##SZ, <) \
+ DO_CMP1(gvec_leu##SZ, vec##SZ, <=)
+
+DO_CMP2(8)
+DO_CMP2(16)
+DO_CMP2(32)
+DO_CMP2(64)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 4210b6787a..6b93f67133 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1862,3 +1862,150 @@ void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_debug_assert(vece <= MO_64);
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
}
+
+/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
+static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, TCGCond cond)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ tcg_gen_setcond_i32(cond, t0, t0, t1);
+ tcg_gen_neg_i32(t0, t0);
+ tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t0);
+}
+
+static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, TCGCond cond)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ tcg_gen_setcond_i64(cond, t0, t0, t1);
+ tcg_gen_neg_i64(t0, t0);
+ tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t0);
+}
+
+static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t tysz,
+ TCGType type, TCGCond cond)
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ tcg_gen_cmp_vec(cond, vece, t0, t0, t1);
+ tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t0);
+}
+
+void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
+ uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static gen_helper_gvec_3 * const eq_fn[4] = {
+ gen_helper_gvec_eq8, gen_helper_gvec_eq16,
+ gen_helper_gvec_eq32, gen_helper_gvec_eq64
+ };
+ static gen_helper_gvec_3 * const ne_fn[4] = {
+ gen_helper_gvec_ne8, gen_helper_gvec_ne16,
+ gen_helper_gvec_ne32, gen_helper_gvec_ne64
+ };
+ static gen_helper_gvec_3 * const lt_fn[4] = {
+ gen_helper_gvec_lt8, gen_helper_gvec_lt16,
+ gen_helper_gvec_lt32, gen_helper_gvec_lt64
+ };
+ static gen_helper_gvec_3 * const le_fn[4] = {
+ gen_helper_gvec_le8, gen_helper_gvec_le16,
+ gen_helper_gvec_le32, gen_helper_gvec_le64
+ };
+ static gen_helper_gvec_3 * const ltu_fn[4] = {
+ gen_helper_gvec_ltu8, gen_helper_gvec_ltu16,
+ gen_helper_gvec_ltu32, gen_helper_gvec_ltu64
+ };
+ static gen_helper_gvec_3 * const leu_fn[4] = {
+ gen_helper_gvec_leu8, gen_helper_gvec_leu16,
+ gen_helper_gvec_leu32, gen_helper_gvec_leu64
+ };
+ static gen_helper_gvec_3 * const * const fns[16] = {
+ [TCG_COND_EQ] = eq_fn,
+ [TCG_COND_NE] = ne_fn,
+ [TCG_COND_LT] = lt_fn,
+ [TCG_COND_LE] = le_fn,
+ [TCG_COND_LTU] = ltu_fn,
+ [TCG_COND_LEU] = leu_fn,
+ };
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, maxsz);
+
+ if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) {
+ do_dup(MO_8, dofs, oprsz, maxsz,
+ NULL, NULL, -(cond == TCG_COND_ALWAYS));
+ return;
+ }
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)
+ && tcg_can_emit_vec_op(INDEX_op_cmp_vec, TCG_TYPE_V256, vece)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_cmp_vec(vece, dofs, aofs, bofs, done, 32, TCG_TYPE_V256, cond);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)
+ && tcg_can_emit_vec_op(INDEX_op_cmp_vec, TCG_TYPE_V128, vece)) {
+ expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, cond);
+ } else if (TCG_TARGET_HAS_v64
+ && check_size_impl(oprsz, 8)
+ && (TCG_TARGET_REG_BITS == 32 || vece != MO_64)
+ && tcg_can_emit_vec_op(INDEX_op_cmp_vec, TCG_TYPE_V64, vece)) {
+ expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, cond);
+ } else if (vece == MO_64 && check_size_impl(oprsz, 8)) {
+ expand_cmp_i64(dofs, aofs, bofs, oprsz, cond);
+ } else if (vece == MO_32 && check_size_impl(oprsz, 4)) {
+ expand_cmp_i32(dofs, aofs, bofs, oprsz, cond);
+ } else {
+ gen_helper_gvec_3 * const *fn = fns[cond];
+
+ if (fn == NULL) {
+ uint32_t tmp;
+ tmp = aofs, aofs = bofs, bofs = tmp;
+ cond = tcg_swap_cond(cond);
+ fn = fns[cond];
+ assert(fn != NULL);
+ }
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]);
+ return;
+ }
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index b54d3de19f..b3f0ec324a 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -480,3 +480,26 @@ void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
do_interleave(INDEX_op_trno_vec, vece, r, a, b);
}
+
+void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
+ TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGTemp *bt = tcgv_vec_temp(b);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGArg bi = temp_arg(bt);
+ TCGType type = rt->base_type;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(bt->base_type == type);
+ can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
+ if (can > 0) {
+ vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
+ } else {
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
+ }
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f82d6e80b0..a85547a6d2 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1392,6 +1392,7 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
+ case INDEX_op_cmp_vec:
return have_vec;
case INDEX_op_dup2_vec:
return have_vec && TCG_TARGET_REG_BITS == 32;
@@ -1791,6 +1792,7 @@ void tcg_dump_ops(TCGContext *s)
case INDEX_op_brcond_i64:
case INDEX_op_setcond_i64:
case INDEX_op_movcond_i64:
+ case INDEX_op_cmp_vec:
if (op->args[k] < ARRAY_SIZE(cond_name)
&& cond_name[op->args[k]]) {
col += qemu_log(",%s", cond_name[op->args[k++]]);
diff --git a/tcg/README b/tcg/README
index 75db47922d..18b6bbd8f1 100644
--- a/tcg/README
+++ b/tcg/README
@@ -630,6 +630,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
v0[2i + 1] = v2[2i + part];
}
+* cmp_vec v0, v1, v2, cond
+
+ Compare vectors by element, storing -1 for true and 0 for false.
+
*********
Note 1: Some shortcuts are defined when the last operand is known to be
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 08/26] tcg: Add generic vector ops for multiplication
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (6 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 07/26] tcg: Add generic vector ops for comparisons Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 09/26] tcg: Add generic vector ops for extension Richard Henderson
` (20 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 5 +++++
tcg/tcg-op-gvec.h | 2 ++
tcg/tcg-op.h | 1 +
tcg/tcg-opc.h | 1 +
tcg/tcg.h | 1 +
accel/tcg/tcg-runtime-gvec.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-gvec.c | 29 +++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 22 ++++++++++++++++++++++
tcg/tcg.c | 2 ++
tcg/README | 4 ++++
10 files changed, 111 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 28abf30d76..c4a2e6b215 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -152,6 +152,11 @@ DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_mul8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_mul16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_mul32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_mul64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index f17b34d896..28ec0f260c 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -176,6 +176,8 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 777db6ad59..f967790cd9 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -920,6 +920,7 @@ void tcg_gen_movi_v128(TCGv_vec, uint64_t, uint64_t);
void tcg_gen_movi_v256(TCGv_vec, uint64_t, uint64_t, uint64_t, uint64_t);
void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index d3fa014507..b21a30273c 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -220,6 +220,7 @@ DEF(st_vec, 0, 2, 1, IMPLVEC)
DEF(add_vec, 1, 2, 0, IMPLVEC)
DEF(sub_vec, 1, 2, 0, IMPLVEC)
+DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
DEF(and_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index b3c94f59f3..9ae7465d1e 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -185,6 +185,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_mul_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index e0cde3216f..9406ccd769 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -141,6 +141,50 @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_mul8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) * *(vec8 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mul16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) * *(vec16 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mul32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) * *(vec32 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) * *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 6b93f67133..3695847e16 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1262,6 +1262,35 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
}
+void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fniv = tcg_gen_mul_vec,
+ .fno = gen_helper_gvec_mul8,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_8 },
+ { .fniv = tcg_gen_mul_vec,
+ .fno = gen_helper_gvec_mul16,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_mul_i32,
+ .fniv = tcg_gen_mul_vec,
+ .fno = gen_helper_gvec_mul32,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_mul_i64,
+ .fniv = tcg_gen_mul_vec,
+ .fno = gen_helper_gvec_mul64,
+ .opc = INDEX_op_mul_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
/* Perform a vector negation using normal negation and a mask.
Compare gen_subv_mask above. */
static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index b3f0ec324a..9038cc6c84 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -503,3 +503,25 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
}
}
+
+void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGTemp *bt = tcgv_vec_temp(b);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGArg bi = temp_arg(bt);
+ TCGType type = rt->base_type;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(bt->base_type == type);
+ can = tcg_can_emit_vec_op(INDEX_op_mul_vec, type, vece);
+ if (can > 0) {
+ vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi);
+ } else {
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(INDEX_op_mul_vec, type, vece, ri, ai, bi);
+ }
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index a85547a6d2..5608391dca 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1404,6 +1404,8 @@ bool tcg_op_supported(TCGOpcode op)
return have_vec && TCG_TARGET_HAS_andc_vec;
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
+ case INDEX_op_mul_vec:
+ return have_vec && TCG_TARGET_HAS_mul_vec;
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
diff --git a/tcg/README b/tcg/README
index 18b6bbd8f1..17695ff7f6 100644
--- a/tcg/README
+++ b/tcg/README
@@ -547,6 +547,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
Similarly, v0 = v1 - v2.
+* mul_vec v0, v1, v2
+
+ Similarly, v0 = v1 * v2.
+
* neg_vec v0, v1
Similarly, v0 = -v1.
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 09/26] tcg: Add generic vector ops for extension
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (7 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 08/26] tcg: Add generic vector ops for multiplication Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 10/26] tcg: Add generic helpers for saturating arithmetic Richard Henderson
` (19 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 8 +++
tcg/tcg-op-gvec.h | 9 +++
tcg/tcg-op.h | 5 ++
tcg/tcg-opc.h | 5 ++
tcg/tcg.h | 2 +
accel/tcg/tcg-runtime-gvec.c | 26 +++++++++
tcg/tcg-op-gvec.c | 130 +++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 39 +++++++++++++
tcg/tcg.c | 6 ++
tcg/README | 13 +++++
10 files changed, 243 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index c4a2e6b215..d1b3542946 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -199,6 +199,14 @@ DEF_HELPER_FLAGS_4(gvec_trn16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_extu8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_extu16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_extu32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_exts8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_exts16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_exts32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 28ec0f260c..f716c53be0 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -222,6 +222,15 @@ void tcg_gen_gvec_trne(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_extul(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_extuh(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_extsl(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_extsh(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
+
void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index f967790cd9..28a5cbe47a 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -940,6 +940,11 @@ void tcg_gen_uzpo_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_trne_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_extul_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_extuh_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_extsl_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_extsh_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+
void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
TCGv_vec a, TCGv_vec b);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index b21a30273c..3dfd872a0f 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -249,6 +249,11 @@ DEF(uzpo_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
DEF(trne_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
DEF(trno_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
+DEF(extul_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_extl_vec))
+DEF(extuh_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_exth_vec))
+DEF(extsl_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_extl_vec))
+DEF(extsh_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_exth_vec))
+
DEF(cmp_vec, 1, 2, 1, IMPLVEC)
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 9ae7465d1e..f870a3f582 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -186,6 +186,8 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_trn_vec 0
#define TCG_TARGET_HAS_cmp_vec 0
#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_extl_vec 0
+#define TCG_TARGET_HAS_exth_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 9406ccd769..ff26be0744 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -588,3 +588,29 @@ DO_CMP2(8)
DO_CMP2(16)
DO_CMP2(32)
DO_CMP2(64)
+
+#define DO_EXT(NAME, TYPE1, TYPE2) \
+void HELPER(NAME)(void *d, void *a, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t oprsz_2 = oprsz / 2; \
+ intptr_t i; \
+ /* We produce output faster than we consume input. \
+ Therefore we must be mindful of possible overlap. */ \
+ if (unlikely((a - d) < (uintptr_t)oprsz)) { \
+ void *a_new = alloca(oprsz_2); \
+ memcpy(a_new, a, oprsz_2); \
+ a = a_new; \
+ } \
+ for (i = 0; i < oprsz_2; i += sizeof(TYPE1)) { \
+ *(TYPE2 *)(d + 2 * i) = *(TYPE1 *)(a + i); \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+DO_EXT(gvec_extu8, uint8_t, uint16_t)
+DO_EXT(gvec_extu16, uint16_t, uint32_t)
+DO_EXT(gvec_extu32, uint32_t, uint64_t)
+DO_EXT(gvec_exts8, int8_t, int16_t)
+DO_EXT(gvec_exts16, int16_t, int32_t)
+DO_EXT(gvec_exts32, int32_t, int64_t)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 3695847e16..2c117a35f1 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -2038,3 +2038,133 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
expand_clr(dofs + oprsz, maxsz - oprsz);
}
}
+
+static void do_ext(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, bool high, bool is_sign)
+{
+ static gen_helper_gvec_2 * const extu_fn[3] = {
+ gen_helper_gvec_extu8, gen_helper_gvec_extu16, gen_helper_gvec_extu32
+ };
+ static gen_helper_gvec_2 * const exts_fn[3] = {
+ gen_helper_gvec_exts8, gen_helper_gvec_exts16, gen_helper_gvec_exts32
+ };
+
+ TCGType type;
+ uint32_t step, i, n;
+ TCGOpcode opc;
+
+ check_size_align(oprsz, maxsz, dofs | aofs);
+ check_overlap_2(dofs, aofs, oprsz);
+ tcg_debug_assert(vece < MO_64);
+
+ opc = is_sign ? (high ? INDEX_op_extsh_vec : INDEX_op_extsl_vec)
+ : (high ? INDEX_op_extuh_vec : INDEX_op_extul_vec);
+
+ /* Since these operations don't operate in lock-step lanes,
+ we must care for overlap. */
+ if (TCG_TARGET_HAS_v256 && oprsz % 32 == 0 && oprsz / 32 <= 8
+ && tcg_can_emit_vec_op(opc, TCG_TYPE_V256, vece)) {
+ type = TCG_TYPE_V256;
+ step = 32;
+ n = oprsz / 32;
+ } else if (TCG_TARGET_HAS_v128 && oprsz % 16 == 0 && oprsz / 16 <= 8
+ && tcg_can_emit_vec_op(opc, TCG_TYPE_V128, vece)) {
+ type = TCG_TYPE_V128;
+ step = 16;
+ n = oprsz / 16;
+ } else if (TCG_TARGET_HAS_v64 && oprsz % 8 == 0 && oprsz / 8 <= 8
+ && tcg_can_emit_vec_op(opc, TCG_TYPE_V64, vece)) {
+ type = TCG_TYPE_V64;
+ step = 8;
+ n = oprsz / 8;
+ } else {
+ if (high) {
+ aofs += oprsz / 2;
+ }
+ tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, 0,
+ is_sign ? exts_fn[vece] : extu_fn[vece]);
+ return;
+ }
+
+ if (n == 1) {
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+
+ tcg_gen_ld_vec(t1, cpu_env, aofs);
+ if (high) {
+ if (is_sign) {
+ tcg_gen_extsh_vec(vece, t1, t1);
+ } else {
+ tcg_gen_extuh_vec(vece, t1, t1);
+ }
+ } else {
+ if (is_sign) {
+ tcg_gen_extsl_vec(vece, t1, t1);
+ } else {
+ tcg_gen_extul_vec(vece, t1, t1);
+ }
+ }
+ tcg_gen_st_vec(t1, cpu_env, dofs);
+ tcg_temp_free_vec(t1);
+ } else {
+ TCGv_vec ta[4], tmp;
+
+ if (high) {
+ aofs += oprsz / 2;
+ }
+
+ for (i = 0; i < (n / 2 + n % 2); ++i) {
+ ta[i] = tcg_temp_new_vec(type);
+ tcg_gen_ld_vec(ta[i], cpu_env, aofs + i * step);
+ }
+
+ tmp = tcg_temp_new_vec(type);
+ for (i = 0; i < n; ++i) {
+ if (i & 1) {
+ if (is_sign) {
+ tcg_gen_extsh_vec(vece, tmp, ta[i / 2]);
+ } else {
+ tcg_gen_extuh_vec(vece, tmp, ta[i / 2]);
+ }
+ } else {
+ if (is_sign) {
+ tcg_gen_extsl_vec(vece, tmp, ta[i / 2]);
+ } else {
+ tcg_gen_extul_vec(vece, tmp, ta[i / 2]);
+ }
+ }
+ tcg_gen_st_vec(tmp, cpu_env, dofs + i * step);
+ }
+ tcg_temp_free_vec(tmp);
+
+ for (i = 0; i < (n / 2 + n % 2); ++i) {
+ tcg_temp_free_vec(ta[i]);
+ }
+ }
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
+void tcg_gen_gvec_extul(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ do_ext(vece, dofs, aofs, oprsz, maxsz, false, false);
+}
+
+void tcg_gen_gvec_extuh(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ do_ext(vece, dofs, aofs, oprsz, maxsz, true, false);
+}
+
+void tcg_gen_gvec_extsl(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ do_ext(vece, dofs, aofs, oprsz, maxsz, false, true);
+}
+
+void tcg_gen_gvec_extsh(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ do_ext(vece, dofs, aofs, oprsz, maxsz, true, true);
+}
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 9038cc6c84..a73d094ddb 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -525,3 +525,42 @@ void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
tcg_expand_vec_op(INDEX_op_mul_vec, type, vece, ri, ai, bi);
}
}
+
+static void do_ext(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGType type = rt->base_type;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ can = tcg_can_emit_vec_op(opc, type, vece);
+ if (can > 0) {
+ vec_gen_2(opc, type, vece, ri, ai);
+ } else {
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(opc, type, vece, ri, ai);
+ }
+}
+
+void tcg_gen_extul_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ do_ext(INDEX_op_extul_vec, vece, r, a);
+}
+
+void tcg_gen_extuh_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ do_ext(INDEX_op_extuh_vec, vece, r, a);
+}
+
+void tcg_gen_extsl_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ do_ext(INDEX_op_extsl_vec, vece, r, a);
+}
+
+void tcg_gen_extsh_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ do_ext(INDEX_op_extsh_vec, vece, r, a);
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5608391dca..8c0ee0a9db 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1427,6 +1427,12 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_trne_vec:
case INDEX_op_trno_vec:
return have_vec && TCG_TARGET_HAS_trn_vec;
+ case INDEX_op_extul_vec:
+ case INDEX_op_extsl_vec:
+ return have_vec && TCG_TARGET_HAS_extl_vec;
+ case INDEX_op_extuh_vec:
+ case INDEX_op_extsh_vec:
+ return have_vec && TCG_TARGET_HAS_exth_vec;
default:
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
diff --git a/tcg/README b/tcg/README
index 17695ff7f6..56c70764bc 100644
--- a/tcg/README
+++ b/tcg/README
@@ -634,6 +634,19 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
v0[2i + 1] = v2[2i + part];
}
+* extul_vec v0, v1
+
+ Extend unsigned the low VECL/VECE/2 elements of v1 into v0.
+
+* extuh_vec v0, v1
+
+ Similarly for the high VECL/VECE/2 elements.
+
+* extsl_vec v0, v1
+* extsh_vec v0, v1
+
+ Similarly with signed extension.
+
* cmp_vec v0, v1, v2, cond
Compare vectors by element, storing -1 for true and 0 for false.
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 10/26] tcg: Add generic helpers for saturating arithmetic
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (8 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 09/26] tcg: Add generic vector ops for extension Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 11/26] tcg: Loosen vec_gen_op* typecheck rules Richard Henderson
` (18 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
No vector ops as yet. SSE only has direct support for 8- and 16-bit
saturation; handling 32- and 64-bit saturation is much more expensive.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 20 ++++
tcg/tcg-op-gvec.h | 10 ++
accel/tcg/tcg-runtime-gvec.c | 268 +++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-gvec.c | 92 +++++++++++++++
4 files changed, 390 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index d1b3542946..ec187a094b 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -157,6 +157,26 @@ DEF_HELPER_FLAGS_4(gvec_mul16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ssadd8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ssadd16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ssadd32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ssadd64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_sssub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sssub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sssub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sssub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_usadd8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_usadd16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_usadd32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_usadd64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_ussub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ussub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ussub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ussub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index f716c53be0..98fdab22f6 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -179,6 +179,16 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+/* Saturated arithmetic. */
+void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+
void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index ff26be0744..e84c900670 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -614,3 +614,271 @@ DO_EXT(gvec_extu32, uint32_t, uint64_t)
DO_EXT(gvec_exts8, int8_t, int16_t)
DO_EXT(gvec_exts16, int16_t, int32_t)
DO_EXT(gvec_exts32, int32_t, int64_t)
+
+void HELPER(gvec_ssadd8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(int8_t)) {
+ int r = *(int8_t *)(a + i) + *(int8_t *)(b + i);
+ if (r > INT8_MAX) {
+ r = INT8_MAX;
+ } else if (r < INT8_MIN) {
+ r = INT8_MIN;
+ }
+ *(int8_t *)(d + i) = r;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_ssadd16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(int16_t)) {
+ int r = *(int16_t *)(a + i) + *(int16_t *)(b + i);
+ if (r > INT16_MAX) {
+ r = INT16_MAX;
+ } else if (r < INT16_MIN) {
+ r = INT16_MIN;
+ }
+ *(int16_t *)(d + i) = r;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_ssadd32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(int32_t)) {
+ int32_t ai = *(int32_t *)(a + i);
+ int32_t bi = *(int32_t *)(b + i);
+ int32_t di = ai + bi;
+ if (((di ^ ai) &~ (ai ^ bi)) < 0) {
+ /* Signed overflow. */
+ di = (di < 0 ? INT32_MAX : INT32_MIN);
+ }
+ *(int32_t *)(d + i) = di;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_ssadd64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(int64_t)) {
+ int64_t ai = *(int64_t *)(a + i);
+ int64_t bi = *(int64_t *)(b + i);
+ int64_t di = ai + bi;
+ if (((di ^ ai) &~ (ai ^ bi)) < 0) {
+ /* Signed overflow. */
+ di = (di < 0 ? INT64_MAX : INT64_MIN);
+ }
+ *(int64_t *)(d + i) = di;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sssub8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ int r = *(int8_t *)(a + i) - *(int8_t *)(b + i);
+ if (r > INT8_MAX) {
+ r = INT8_MAX;
+ } else if (r < INT8_MIN) {
+ r = INT8_MIN;
+ }
+ *(uint8_t *)(d + i) = r;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sssub16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(int16_t)) {
+ int r = *(int16_t *)(a + i) - *(int16_t *)(b + i);
+ if (r > INT16_MAX) {
+ r = INT16_MAX;
+ } else if (r < INT16_MIN) {
+ r = INT16_MIN;
+ }
+ *(int16_t *)(d + i) = r;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sssub32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(int32_t)) {
+ int32_t ai = *(int32_t *)(a + i);
+ int32_t bi = *(int32_t *)(b + i);
+ int32_t di = ai - bi;
+ if (((di ^ ai) & (ai ^ bi)) < 0) {
+ /* Signed overflow. */
+ di = (di < 0 ? INT32_MAX : INT32_MIN);
+ }
+ *(int32_t *)(d + i) = di;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sssub64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(int64_t)) {
+ int64_t ai = *(int64_t *)(a + i);
+ int64_t bi = *(int64_t *)(b + i);
+ int64_t di = ai - bi;
+ if (((di ^ ai) & (ai ^ bi)) < 0) {
+ /* Signed overflow. */
+ di = (di < 0 ? INT64_MAX : INT64_MIN);
+ }
+ *(int64_t *)(d + i) = di;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_usadd8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ unsigned r = *(uint8_t *)(a + i) + *(uint8_t *)(b + i);
+ if (r > UINT8_MAX) {
+ r = UINT8_MAX;
+ }
+ *(uint8_t *)(d + i) = r;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_usadd16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ unsigned r = *(uint16_t *)(a + i) + *(uint16_t *)(b + i);
+ if (r > UINT16_MAX) {
+ r = UINT16_MAX;
+ }
+ *(uint16_t *)(d + i) = r;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_usadd32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ uint32_t ai = *(uint32_t *)(a + i);
+ uint32_t bi = *(uint32_t *)(b + i);
+ uint32_t di = ai + bi;
+ if (di < ai) {
+ di = UINT32_MAX;
+ }
+ *(uint32_t *)(d + i) = di;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_usadd64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ uint64_t ai = *(uint64_t *)(a + i);
+ uint64_t bi = *(uint64_t *)(b + i);
+ uint64_t di = ai + bi;
+ if (di < ai) {
+ di = UINT64_MAX;
+ }
+ *(uint64_t *)(d + i) = di;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_ussub8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ int r = *(uint8_t *)(a + i) - *(uint8_t *)(b + i);
+ if (r < 0) {
+ r = 0;
+ }
+ *(uint8_t *)(d + i) = r;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_ussub16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ int r = *(uint16_t *)(a + i) - *(uint16_t *)(b + i);
+ if (r < 0) {
+ r = 0;
+ }
+ *(uint16_t *)(d + i) = r;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_ussub32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ uint32_t ai = *(uint32_t *)(a + i);
+ uint32_t bi = *(uint32_t *)(b + i);
+ uint32_t di = ai - bi;
+ if (ai < bi) {
+ di = 0;
+ }
+ *(uint32_t *)(d + i) = di;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_ussub64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ uint64_t ai = *(uint64_t *)(a + i);
+ uint64_t bi = *(uint64_t *)(b + i);
+ uint64_t di = ai - bi;
+ if (ai < bi) {
+ di = 0;
+ }
+ *(uint64_t *)(d + i) = di;
+ }
+ clear_high(d, oprsz, desc);
+}
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 2c117a35f1..d65a5b1b82 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1291,6 +1291,98 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
}
+void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_ssadd8, .vece = MO_8 },
+ { .fno = gen_helper_gvec_ssadd16, .vece = MO_16 },
+ { .fno = gen_helper_gvec_ssadd32, .vece = MO_32 },
+ { .fno = gen_helper_gvec_ssadd64, .vece = MO_64 }
+ };
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_sssub8, .vece = MO_8 },
+ { .fno = gen_helper_gvec_sssub16, .vece = MO_16 },
+ { .fno = gen_helper_gvec_sssub32, .vece = MO_32 },
+ { .fno = gen_helper_gvec_sssub64, .vece = MO_64 }
+ };
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+static void tcg_gen_vec_usadd32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 max = tcg_const_i32(-1);
+ tcg_gen_add_i32(d, a, b);
+ tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d);
+ tcg_temp_free_i32(max);
+}
+
+static void tcg_gen_vec_usadd32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 max = tcg_const_i64(-1);
+ tcg_gen_add_i64(d, a, b);
+ tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d);
+ tcg_temp_free_i64(max);
+}
+
+void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_usadd8, .vece = MO_8 },
+ { .fno = gen_helper_gvec_usadd16, .vece = MO_16 },
+ { .fni4 = tcg_gen_vec_usadd32_i32,
+ .fno = gen_helper_gvec_usadd32,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_vec_usadd32_i64,
+ .fno = gen_helper_gvec_usadd64,
+ .vece = MO_64 }
+ };
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
+static void tcg_gen_vec_ussub32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 min = tcg_const_i32(0);
+ tcg_gen_sub_i32(d, a, b);
+ tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d);
+ tcg_temp_free_i32(min);
+}
+
+static void tcg_gen_vec_ussub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 min = tcg_const_i64(0);
+ tcg_gen_sub_i64(d, a, b);
+ tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d);
+ tcg_temp_free_i64(min);
+}
+
+void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_ussub8, .vece = MO_8 },
+ { .fno = gen_helper_gvec_ussub16, .vece = MO_16 },
+ { .fni4 = tcg_gen_vec_ussub32_i32,
+ .fno = gen_helper_gvec_ussub32,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_vec_ussub32_i64,
+ .fno = gen_helper_gvec_ussub64,
+ .vece = MO_64 }
+ };
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
+}
+
/* Perform a vector negation using normal negation and a mask.
Compare gen_subv_mask above. */
static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 11/26] tcg: Loosen vec_gen_op* typecheck rules
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (9 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 10/26] tcg: Add generic helpers for saturating arithmetic Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 12/26] tcg: Add generic vector helpers with a scalar immediate operand Richard Henderson
` (17 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
For ARM SVE with VQ=3, we want to be able to dup a scalar
into a v256, use that, and then perform a second operation
with the v256 punned to a v128.
Allow operands to a vector operation be wider than necessary
for the output.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op-vec.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index a73d094ddb..ad9a45b653 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -78,7 +78,7 @@ static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
TCGTemp *at = tcgv_vec_temp(a);
TCGType type = rt->base_type;
- tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(at->base_type >= type);
vec_gen_2(opc, type, vece, temp_arg(rt), temp_arg(at));
}
@@ -90,8 +90,8 @@ static void vec_gen_op3(TCGOpcode opc, unsigned vece,
TCGTemp *bt = tcgv_vec_temp(b);
TCGType type = rt->base_type;
- tcg_debug_assert(at->base_type == type);
- tcg_debug_assert(bt->base_type == type);
+ tcg_debug_assert(at->base_type >= type);
+ tcg_debug_assert(bt->base_type >= type);
vec_gen_3(opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt));
}
@@ -257,14 +257,14 @@ void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
if (TCG_TARGET_REG_BITS == 64) {
TCGArg ai = tcgv_i64_arg(a);
- vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai);
+ vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);
} else if (vece == MO_64) {
TCGArg al = tcgv_i32_arg(TCGV_LOW(a));
TCGArg ah = tcgv_i32_arg(TCGV_HIGH(a));
vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah);
} else {
TCGArg ai = tcgv_i32_arg(TCGV_LOW(a));
- vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai);
+ vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);
}
}
@@ -493,8 +493,8 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
TCGType type = rt->base_type;
int can;
- tcg_debug_assert(at->base_type == type);
- tcg_debug_assert(bt->base_type == type);
+ tcg_debug_assert(at->base_type >= type);
+ tcg_debug_assert(bt->base_type >= type);
can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
if (can > 0) {
vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
@@ -515,8 +515,8 @@ void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
TCGType type = rt->base_type;
int can;
- tcg_debug_assert(at->base_type == type);
- tcg_debug_assert(bt->base_type == type);
+ tcg_debug_assert(at->base_type >= type);
+ tcg_debug_assert(bt->base_type >= type);
can = tcg_can_emit_vec_op(INDEX_op_mul_vec, type, vece);
if (can > 0) {
vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi);
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 12/26] tcg: Add generic vector helpers with a scalar immediate operand
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (10 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 11/26] tcg: Loosen vec_gen_op* typecheck rules Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 13/26] tcg: Add generic vector helpers with a scalar variable operand Richard Henderson
` (16 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
We already have immediate shifts. Add addition, multiplication,
and logical operations with an immediate. Subtraction can thus
be done with negation of the constant.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 14 ++++
tcg/tcg-op-gvec.h | 22 ++++-
accel/tcg/tcg-runtime-gvec.c | 132 ++++++++++++++++++++++++++++++
tcg/tcg-op-gvec.c | 186 ++++++++++++++++++++++++++++++++++++++++++-
4 files changed, 352 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index ec187a094b..30bb10f9f1 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -147,6 +147,11 @@ DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_add32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_add64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_adds8, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_adds16, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_adds32, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_adds64, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
DEF_HELPER_FLAGS_4(gvec_sub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@@ -157,6 +162,11 @@ DEF_HELPER_FLAGS_4(gvec_mul16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_muls8, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_muls16, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_muls32, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_muls64, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
DEF_HELPER_FLAGS_4(gvec_ssadd8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_ssadd16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_ssadd32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@@ -189,6 +199,10 @@ DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_andi, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_xori, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_ori, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
DEF_HELPER_FLAGS_3(gvec_shl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_shl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_shl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 98fdab22f6..1fbb94a0cd 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -35,6 +35,12 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz, int32_t data,
gen_helper_gvec_2 *fn);
+/* Similarly, passing an extra data value. */
+typedef void gen_helper_gvec_2i(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32);
+void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2i *fn);
+
/* Similarly, passing an extra pointer (e.g. env or float_status). */
typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
@@ -102,8 +108,10 @@ typedef struct {
void (*fni4)(TCGv_i32, TCGv_i32, int32_t);
/* Expand inline with a host vector type. */
void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t);
- /* Expand out-of-line helper w/descriptor. */
+ /* Expand out-of-line helper w/descriptor, data in descriptor. */
gen_helper_gvec_2 *fno;
+ /* Expand out-of-line helper w/descriptor, data as argument. */
+ gen_helper_gvec_2i *fnoi;
/* The opcode, if any, to which this corresponds. */
TCGOpcode opc;
/* The vector element size, if applicable. */
@@ -179,6 +187,11 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz);
+
/* Saturated arithmetic. */
void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
@@ -200,6 +213,13 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz);
+
void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t s, uint32_t m);
void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index e84c900670..378658124f 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -97,6 +97,54 @@ void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec8 vecb = (vec8){ b, b, b, b, b, b, b, b, b, b, b, b, b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) + vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec16 vecb = (vec16){ b, b, b, b, b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) + vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec32 vecb = (vec32){ b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) + vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_adds64)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec64 vecb = (vec64){ b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) + vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
@@ -185,6 +233,54 @@ void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec8 vecb = (vec8){ b, b, b, b, b, b, b, b, b, b, b, b, b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) * vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec16 vecb = (vec16){ b, b, b, b, b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) * vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec32 vecb = (vec32){ b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) * vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_muls64)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec64 vecb = (vec64){ b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) * vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
@@ -343,6 +439,42 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_andi)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec64 vecb = (vec64){ b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) & vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_xori)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec64 vecb = (vec64){ b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_ori)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec64 vecb = (vec64){ b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) | vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
void HELPER(gvec_shl8i)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index d65a5b1b82..59570cc17e 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -106,6 +106,28 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
tcg_temp_free_i32(desc);
}
+/* Generate a call to a gvec-style helper with two vector operands
+ and one scalar operand. */
+void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2i *fn)
+{
+ TCGv_ptr a0, a1;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+
+ fn(a0, a1, c, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_i32(desc);
+}
+
/* Generate a call to a gvec-style helper with three vector operands. */
void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, int32_t data,
@@ -859,7 +881,13 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4);
} else {
- tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno);
+ if (g->fno) {
+ tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno);
+ } else {
+ TCGv_i64 tcg_c = tcg_const_i64(c);
+ tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz, maxsz, c, g->fnoi);
+ tcg_temp_free_i64(tcg_c);
+ }
return;
}
@@ -1183,6 +1211,59 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
}
+static void tcg_gen_vec_addi8_i64(TCGv_i64 d, TCGv_i64 a, int64_t b)
+{
+ TCGv_i64 t = tcg_const_i64((b & 0xff) * (-1ull / 0xff));
+ tcg_gen_vec_add8_i64(d, a, t);
+ tcg_temp_free_i64(t);
+}
+
+static void tcg_gen_vec_addi16_i64(TCGv_i64 d, TCGv_i64 a, int64_t b)
+{
+ TCGv_i64 t = tcg_const_i64((b & 0xffff) * (-1ull / 0xffff));
+ tcg_gen_vec_add16_i64(d, a, t);
+ tcg_temp_free_i64(t);
+}
+
+static void tcg_gen_addi_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t b)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ tcg_gen_dupi_vec(vece, t, b);
+ tcg_gen_add_vec(vece, d, a, t);
+ tcg_temp_free_vec(t);
+}
+
+void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2i g[4] = {
+ { .fni8 = tcg_gen_vec_addi8_i64,
+ .fniv = tcg_gen_addi_vec,
+ .fnoi = gen_helper_gvec_adds8,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_addi16_i64,
+ .fniv = tcg_gen_addi_vec,
+ .fnoi = gen_helper_gvec_adds16,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_addi_i32,
+ .fniv = tcg_gen_addi_vec,
+ .fnoi = gen_helper_gvec_adds32,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_addi_i64,
+ .fniv = tcg_gen_addi_vec,
+ .fnoi = gen_helper_gvec_adds64,
+ .opc = INDEX_op_add_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, c, &g[vece]);
+}
+
/* Perform a vector subtraction using normal subtraction and a mask.
Compare gen_addv_mask above. */
static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
@@ -1291,6 +1372,43 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
}
+static void tcg_gen_muli_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t b)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ tcg_gen_dupi_vec(vece, t, b);
+ tcg_gen_mul_vec(vece, d, a, t);
+ tcg_temp_free_vec(t);
+}
+
+void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2i g[4] = {
+ { .fniv = tcg_gen_muli_vec,
+ .fnoi = gen_helper_gvec_muls8,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_8 },
+ { .fniv = tcg_gen_muli_vec,
+ .fnoi = gen_helper_gvec_muls16,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_muli_i32,
+ .fniv = tcg_gen_muli_vec,
+ .fnoi = gen_helper_gvec_muls32,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_muli_i64,
+ .fniv = tcg_gen_muli_vec,
+ .fnoi = gen_helper_gvec_muls64,
+ .opc = INDEX_op_mul_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, c, &g[vece]);
+}
+
void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
{
@@ -1523,6 +1641,72 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
+static void tcg_gen_andi_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t b)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ tcg_gen_dupi_vec(vece, t, b);
+ tcg_gen_and_vec(vece, d, a, t);
+ tcg_temp_free_vec(t);
+}
+
+void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2i g = {
+ .fni8 = tcg_gen_andi_i64,
+ .fniv = tcg_gen_andi_vec,
+ .fnoi = gen_helper_gvec_andi,
+ .opc = INDEX_op_and_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64
+ };
+ tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, c, &g);
+}
+
+static void tcg_gen_xori_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t b)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ tcg_gen_dupi_vec(vece, t, b);
+ tcg_gen_xor_vec(vece, d, a, t);
+ tcg_temp_free_vec(t);
+}
+
+void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2i g = {
+ .fni8 = tcg_gen_xori_i64,
+ .fniv = tcg_gen_xori_vec,
+ .fnoi = gen_helper_gvec_xori,
+ .opc = INDEX_op_xor_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64
+ };
+ tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, c, &g);
+}
+
+static void tcg_gen_ori_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t b)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ tcg_gen_dupi_vec(vece, t, b);
+ tcg_gen_or_vec(vece, d, a, t);
+ tcg_temp_free_vec(t);
+}
+
+void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,
+ int64_t c, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2i g = {
+ .fni8 = tcg_gen_ori_i64,
+ .fniv = tcg_gen_ori_vec,
+ .fnoi = gen_helper_gvec_ori,
+ .opc = INDEX_op_or_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64
+ };
+ tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, c, &g);
+}
+
void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
{
uint64_t mask = ((0xff << c) & 0xff) * (-1ull / 0xff);
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 13/26] tcg: Add generic vector helpers with a scalar variable operand
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (11 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 12/26] tcg: Add generic vector helpers with a scalar immediate operand Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 14/26] tcg/optimize: Handle vector opcodes during optimize Richard Henderson
` (15 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Use dup to convert the scalar to a third vector.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 5 ++
tcg/tcg-op-gvec.h | 28 ++++++
accel/tcg/tcg-runtime-gvec.c | 48 ++++++++++
tcg/tcg-op-gvec.c | 207 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 288 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 30bb10f9f1..65d0c2ec3b 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -157,6 +157,11 @@ DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_subs8, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_subs16, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_subs32, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_subs64, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
DEF_HELPER_FLAGS_4(gvec_mul8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_mul32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 1fbb94a0cd..0e8ba3d305 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -122,6 +122,27 @@ typedef struct {
bool load_dest;
} GVecGen2i;
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_2i *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ uint32_t data;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+ /* Load scalar as 1st source operand. */
+ bool scalar_first;
+} GVecGen2s;
+
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
@@ -166,6 +187,8 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t maxsz, int64_t c, const GVecGen2i *);
+void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i64 c, const GVecGen2s *);
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
@@ -192,6 +215,11 @@ void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i64 c, uint32_t oprsz, uint32_t maxsz);
+
/* Saturated arithmetic. */
void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 378658124f..ec8695dd66 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -189,6 +189,54 @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec8 vecb = (vec8){ b, b, b, b, b, b, b, b, b, b, b, b, b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) - vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec16 vecb = (vec16){ b, b, b, b, b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) - vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec32 vecb = (vec32){ b, b, b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) - vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_subs64)(void *d, void *a, uint64_t b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ vec64 vecb = (vec64){ b, b };
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) - vecb;
+ }
+ clear_high(d, oprsz, desc);
+}
+
void HELPER(gvec_mul8)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 59570cc17e..7b854841d0 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -576,6 +576,27 @@ static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
tcg_temp_free_i32(t1);
}
+static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ TCGv_i32 c, bool scalar_first,
+ void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ if (scalar_first) {
+ fni(t1, c, t0);
+ } else {
+ fni(t1, t0, c);
+ }
+ tcg_gen_st_i32(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
static void expand_3_i32(uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, bool load_dest,
@@ -659,6 +680,27 @@ static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
tcg_temp_free_i64(t1);
}
+static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ TCGv_i64 c, bool scalar_first,
+ void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ if (scalar_first) {
+ fni(t1, c, t0);
+ } else {
+ fni(t1, t0, c);
+ }
+ tcg_gen_st_i64(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
static void expand_3_i64(uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, bool load_dest,
@@ -746,6 +788,28 @@ static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_temp_free_vec(t1);
}
+static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t tysz, TCGType type,
+ TCGv_vec c, bool scalar_first,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ if (scalar_first) {
+ fni(vece, t1, c, t0);
+ } else {
+ fni(vece, t1, t0, c);
+ }
+ tcg_gen_st_vec(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t0);
+ tcg_temp_free_vec(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz,
@@ -845,6 +909,7 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
}
}
+/* Expand a vector operation with two vectors and an immediate. */
void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t maxsz, int64_t c, const GVecGen2i *g)
{
@@ -896,6 +961,86 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
}
}
+/* Expand a vector operation with two vectors and a scalar. */
+void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g)
+{
+ TCGType type;
+
+ check_size_align(oprsz, maxsz, dofs | aofs);
+ check_overlap_2(dofs, aofs, maxsz);
+
+ type = 0;
+ if (g->fniv) {
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ type = TCG_TYPE_V256;
+ } else if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ type = TCG_TYPE_V128;
+ } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && check_size_impl(oprsz, 8)) {
+ type = TCG_TYPE_V64;
+ }
+ }
+ if (type != 0) {
+ TCGv_vec t_vec = tcg_temp_new_vec(type);
+ uint32_t done;
+
+ tcg_gen_dup_i64_vec(g->vece, t_vec, c);
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+ switch (type) {
+ case TCG_TYPE_V256:
+ done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_2s_vec(g->vece, dofs, aofs, done, 32, TCG_TYPE_V256,
+ t_vec, g->scalar_first, g->fniv);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ if (oprsz == 0) {
+ break;
+ }
+ /* fallthru */
+
+ case TCG_TYPE_V128:
+ expand_2s_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
+ t_vec, g->scalar_first, g->fniv);
+ break;
+
+ case TCG_TYPE_V64:
+ expand_2s_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
+ t_vec, g->scalar_first, g->fniv);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_vec(t_vec);
+ } else if (g->fni8 && check_size_impl(oprsz, 8)) {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+
+ gen_dup_i64(g->vece, t64, c);
+ expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8);
+ tcg_temp_free_i64(t64);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ TCGv_i32 t32 = tcg_temp_new_i32();
+
+ tcg_gen_extrl_i64_i32(t32, c);
+ gen_dup_i32(g->vece, t32, t32);
+ expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4);
+ tcg_temp_free_i32(t32);
+ } else {
+ tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, 0, g->fno);
+ return;
+ }
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
/* Expand a vector three-operand operation. */
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
@@ -1264,6 +1409,68 @@ void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, c, &g[vece]);
}
+void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2s g[4] = {
+ { .fni8 = tcg_gen_vec_add8_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_adds8,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_add16_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_adds16,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_add_i32,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_adds32,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_add_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_adds64,
+ .opc = INDEX_op_add_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);
+}
+
+void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen2s g[4] = {
+ { .fni8 = tcg_gen_vec_sub8_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_subs8,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_sub16_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_subs16,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_sub_i32,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_subs32,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_sub_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_subs64,
+ .opc = INDEX_op_sub_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]);
+}
+
/* Perform a vector subtraction using normal subtraction and a mask.
Compare gen_addv_mask above. */
static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 14/26] tcg/optimize: Handle vector opcodes during optimize
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (12 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 13/26] tcg: Add generic vector helpers with a scalar variable operand Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 15/26] target/arm: Align vector registers Richard Henderson
` (14 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Trivial move and constant propagation. Some identity and constant
function folding, but nothing that requires knowledge of the size
of the vector element.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 150 +++++++++++++++++++++++++++++----------------------------
1 file changed, 77 insertions(+), 73 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 2cbbeefd53..d4ea67e541 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -32,6 +32,11 @@
glue(glue(case INDEX_op_, x), _i32): \
glue(glue(case INDEX_op_, x), _i64)
+#define CASE_OP_32_64_VEC(x) \
+ glue(glue(case INDEX_op_, x), _i32): \
+ glue(glue(case INDEX_op_, x), _i64): \
+ glue(glue(case INDEX_op_, x), _vec)
+
struct tcg_temp_info {
bool is_const;
TCGTemp *prev_copy;
@@ -108,40 +113,6 @@ static void init_arg_info(struct tcg_temp_info *infos,
init_ts_info(infos, temps_used, arg_temp(arg));
}
-static int op_bits(TCGOpcode op)
-{
- const TCGOpDef *def = &tcg_op_defs[op];
- return def->flags & TCG_OPF_64BIT ? 64 : 32;
-}
-
-static TCGOpcode op_to_mov(TCGOpcode op)
-{
- switch (op_bits(op)) {
- case 32:
- return INDEX_op_mov_i32;
- case 64:
- return INDEX_op_mov_i64;
- default:
- fprintf(stderr, "op_to_mov: unexpected return value of "
- "function op_bits.\n");
- tcg_abort();
- }
-}
-
-static TCGOpcode op_to_movi(TCGOpcode op)
-{
- switch (op_bits(op)) {
- case 32:
- return INDEX_op_movi_i32;
- case 64:
- return INDEX_op_movi_i64;
- default:
- fprintf(stderr, "op_to_movi: unexpected return value of "
- "function op_bits.\n");
- tcg_abort();
- }
-}
-
static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
{
TCGTemp *i;
@@ -199,11 +170,23 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2)
static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
{
- TCGOpcode new_op = op_to_movi(op->opc);
+ const TCGOpDef *def;
+ TCGOpcode new_op;
tcg_target_ulong mask;
struct tcg_temp_info *di = arg_info(dst);
+ def = &tcg_op_defs[op->opc];
+ if (def->flags & TCG_OPF_VECTOR) {
+ new_op = INDEX_op_dupi_vec;
+ } else if (def->flags & TCG_OPF_64BIT) {
+ new_op = INDEX_op_movi_i64;
+ } else {
+ new_op = INDEX_op_movi_i32;
+ }
op->opc = new_op;
+ /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
+ op->args[0] = dst;
+ op->args[1] = val;
reset_temp(dst);
di->is_const = true;
@@ -214,15 +197,13 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
mask |= ~0xffffffffull;
}
di->mask = mask;
-
- op->args[0] = dst;
- op->args[1] = val;
}
static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
{
TCGTemp *dst_ts = arg_temp(dst);
TCGTemp *src_ts = arg_temp(src);
+ const TCGOpDef *def;
struct tcg_temp_info *di;
struct tcg_temp_info *si;
tcg_target_ulong mask;
@@ -236,9 +217,16 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
reset_ts(dst_ts);
di = ts_info(dst_ts);
si = ts_info(src_ts);
- new_op = op_to_mov(op->opc);
-
+ def = &tcg_op_defs[op->opc];
+ if (def->flags & TCG_OPF_VECTOR) {
+ new_op = INDEX_op_mov_vec;
+ } else if (def->flags & TCG_OPF_64BIT) {
+ new_op = INDEX_op_mov_i64;
+ } else {
+ new_op = INDEX_op_mov_i32;
+ }
op->opc = new_op;
+ /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
op->args[0] = dst;
op->args[1] = src;
@@ -417,8 +405,9 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y)
{
+ const TCGOpDef *def = &tcg_op_defs[op];
TCGArg res = do_constant_folding_2(op, x, y);
- if (op_bits(op) == 32) {
+ if (!(def->flags & TCG_OPF_64BIT)) {
res = (int32_t)res;
}
return res;
@@ -508,13 +497,12 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
tcg_target_ulong xv = arg_info(x)->val;
tcg_target_ulong yv = arg_info(y)->val;
if (arg_is_const(x) && arg_is_const(y)) {
- switch (op_bits(op)) {
- case 32:
- return do_constant_folding_cond_32(xv, yv, c);
- case 64:
+ const TCGOpDef *def = &tcg_op_defs[op];
+ tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR));
+ if (def->flags & TCG_OPF_64BIT) {
return do_constant_folding_cond_64(xv, yv, c);
- default:
- tcg_abort();
+ } else {
+ return do_constant_folding_cond_32(xv, yv, c);
}
} else if (args_are_copies(x, y)) {
return do_constant_folding_cond_eq(c);
@@ -653,11 +641,11 @@ void tcg_optimize(TCGContext *s)
/* For commutative operations make constant second argument */
switch (opc) {
- CASE_OP_32_64(add):
- CASE_OP_32_64(mul):
- CASE_OP_32_64(and):
- CASE_OP_32_64(or):
- CASE_OP_32_64(xor):
+ CASE_OP_32_64_VEC(add):
+ CASE_OP_32_64_VEC(mul):
+ CASE_OP_32_64_VEC(and):
+ CASE_OP_32_64_VEC(or):
+ CASE_OP_32_64_VEC(xor):
CASE_OP_32_64(eqv):
CASE_OP_32_64(nand):
CASE_OP_32_64(nor):
@@ -722,7 +710,7 @@ void tcg_optimize(TCGContext *s)
continue;
}
break;
- CASE_OP_32_64(sub):
+ CASE_OP_32_64_VEC(sub):
{
TCGOpcode neg_op;
bool have_neg;
@@ -734,9 +722,12 @@ void tcg_optimize(TCGContext *s)
if (opc == INDEX_op_sub_i32) {
neg_op = INDEX_op_neg_i32;
have_neg = TCG_TARGET_HAS_neg_i32;
- } else {
+ } else if (opc == INDEX_op_sub_i64) {
neg_op = INDEX_op_neg_i64;
have_neg = TCG_TARGET_HAS_neg_i64;
+ } else {
+ neg_op = INDEX_op_neg_vec;
+ have_neg = TCG_TARGET_HAS_neg_vec;
}
if (!have_neg) {
break;
@@ -750,7 +741,7 @@ void tcg_optimize(TCGContext *s)
}
}
break;
- CASE_OP_32_64(xor):
+ CASE_OP_32_64_VEC(xor):
CASE_OP_32_64(nand):
if (!arg_is_const(op->args[1])
&& arg_is_const(op->args[2])
@@ -767,7 +758,7 @@ void tcg_optimize(TCGContext *s)
goto try_not;
}
break;
- CASE_OP_32_64(andc):
+ CASE_OP_32_64_VEC(andc):
if (!arg_is_const(op->args[2])
&& arg_is_const(op->args[1])
&& arg_info(op->args[1])->val == -1) {
@@ -775,7 +766,7 @@ void tcg_optimize(TCGContext *s)
goto try_not;
}
break;
- CASE_OP_32_64(orc):
+ CASE_OP_32_64_VEC(orc):
CASE_OP_32_64(eqv):
if (!arg_is_const(op->args[2])
&& arg_is_const(op->args[1])
@@ -789,7 +780,10 @@ void tcg_optimize(TCGContext *s)
TCGOpcode not_op;
bool have_not;
- if (def->flags & TCG_OPF_64BIT) {
+ if (def->flags & TCG_OPF_VECTOR) {
+ not_op = INDEX_op_not_vec;
+ have_not = TCG_TARGET_HAS_not_vec;
+ } else if (def->flags & TCG_OPF_64BIT) {
not_op = INDEX_op_not_i64;
have_not = TCG_TARGET_HAS_not_i64;
} else {
@@ -810,16 +804,16 @@ void tcg_optimize(TCGContext *s)
/* Simplify expression for "op r, a, const => mov r, a" cases */
switch (opc) {
- CASE_OP_32_64(add):
- CASE_OP_32_64(sub):
+ CASE_OP_32_64_VEC(add):
+ CASE_OP_32_64_VEC(sub):
+ CASE_OP_32_64_VEC(or):
+ CASE_OP_32_64_VEC(xor):
+ CASE_OP_32_64_VEC(andc):
CASE_OP_32_64(shl):
CASE_OP_32_64(shr):
CASE_OP_32_64(sar):
CASE_OP_32_64(rotl):
CASE_OP_32_64(rotr):
- CASE_OP_32_64(or):
- CASE_OP_32_64(xor):
- CASE_OP_32_64(andc):
if (!arg_is_const(op->args[1])
&& arg_is_const(op->args[2])
&& arg_info(op->args[2])->val == 0) {
@@ -827,8 +821,8 @@ void tcg_optimize(TCGContext *s)
continue;
}
break;
- CASE_OP_32_64(and):
- CASE_OP_32_64(orc):
+ CASE_OP_32_64_VEC(and):
+ CASE_OP_32_64_VEC(orc):
CASE_OP_32_64(eqv):
if (!arg_is_const(op->args[1])
&& arg_is_const(op->args[2])
@@ -1042,8 +1036,8 @@ void tcg_optimize(TCGContext *s)
/* Simplify expression for "op r, a, 0 => movi r, 0" cases */
switch (opc) {
- CASE_OP_32_64(and):
- CASE_OP_32_64(mul):
+ CASE_OP_32_64_VEC(and):
+ CASE_OP_32_64_VEC(mul):
CASE_OP_32_64(muluh):
CASE_OP_32_64(mulsh):
if (arg_is_const(op->args[2])
@@ -1058,8 +1052,8 @@ void tcg_optimize(TCGContext *s)
/* Simplify expression for "op r, a, a => mov r, a" cases */
switch (opc) {
- CASE_OP_32_64(or):
- CASE_OP_32_64(and):
+ CASE_OP_32_64_VEC(or):
+ CASE_OP_32_64_VEC(and):
if (args_are_copies(op->args[1], op->args[2])) {
tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
continue;
@@ -1071,9 +1065,9 @@ void tcg_optimize(TCGContext *s)
/* Simplify expression for "op r, a, a => movi r, 0" cases */
switch (opc) {
- CASE_OP_32_64(andc):
- CASE_OP_32_64(sub):
- CASE_OP_32_64(xor):
+ CASE_OP_32_64_VEC(andc):
+ CASE_OP_32_64_VEC(sub):
+ CASE_OP_32_64_VEC(xor):
if (args_are_copies(op->args[1], op->args[2])) {
tcg_opt_gen_movi(s, op, op->args[0], 0);
continue;
@@ -1087,13 +1081,23 @@ void tcg_optimize(TCGContext *s)
folding. Constants will be substituted to arguments by register
allocator where needed and possible. Also detect copies. */
switch (opc) {
- CASE_OP_32_64(mov):
+ CASE_OP_32_64_VEC(mov):
tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
break;
CASE_OP_32_64(movi):
+ case INDEX_op_dupi_vec:
tcg_opt_gen_movi(s, op, op->args[0], op->args[1]);
break;
+ case INDEX_op_dup_vec:
+ if (arg_is_const(op->args[1])) {
+ tmp = arg_info(op->args[1])->val;
+ tmp = dup_const(TCGOP_VECE(op), tmp);
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ continue;
+ }
+ break;
+
CASE_OP_32_64(not):
CASE_OP_32_64(neg):
CASE_OP_32_64(ext8s):
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 15/26] target/arm: Align vector registers
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (13 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 14/26] tcg/optimize: Handle vector opcodes during optimize Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 16/26] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
` (13 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 96316700dd..3ff4dea6b8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -492,7 +492,7 @@ typedef struct CPUARMState {
* the two execution states, and means we do not need to explicitly
* map these registers when changing states.
*/
- float64 regs[64];
+ float64 regs[64] QEMU_ALIGNED(16);
uint32_t xregs[16];
/* We store these fpcsr fields separately for convenience. */
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 16/26] target/arm: Use vector infrastructure for aa64 add/sub/logic
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (14 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 15/26] target/arm: Align vector registers Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 17/26] target/arm: Use vector infrastructure for aa64 mov/not/neg Richard Henderson
` (12 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 207 +++++++++++++++++++++++++++++----------------
1 file changed, 134 insertions(+), 73 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ba94f7d045..572af456d1 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
+#include "tcg-op-gvec.h"
#include "qemu/log.h"
#include "arm_ldst.h"
#include "translate.h"
@@ -83,6 +84,10 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
+/* Note that the gvec expanders operate on offsets + sizes. */
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+
/* initialize TCG globals. */
void a64_translate_init(void)
{
@@ -535,6 +540,21 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
return offs;
}
+/* Return the offset info CPUARMState of the "whole" vector register Qn. */
+static inline int vec_full_reg_offset(DisasContext *s, int regno)
+{
+ assert_fp_access_checked(s);
+ return offsetof(CPUARMState, vfp.regs[regno * 2]);
+}
+
+/* Return the byte size of the "whole" vector register, VL / 8. */
+static inline int vec_full_reg_size(DisasContext *s)
+{
+ /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
+ In the meantime this is just the AdvSIMD length of 128. */
+ return 128 / 8;
+}
+
/* Return the offset into CPUARMState of a slice (from
* the least significant end) of FP register Qn (ie
* Dn, Sn, Hn or Bn).
@@ -9048,85 +9068,125 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
}
}
+static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ tcg_gen_xor_i64(rn, rn, rm);
+ tcg_gen_and_i64(rn, rn, rd);
+ tcg_gen_xor_i64(rd, rm, rn);
+}
+
+static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ tcg_gen_xor_i64(rn, rn, rd);
+ tcg_gen_and_i64(rn, rn, rm);
+ tcg_gen_xor_i64(rd, rd, rn);
+}
+
+static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ tcg_gen_xor_i64(rn, rn, rd);
+ tcg_gen_andc_i64(rn, rn, rm);
+ tcg_gen_xor_i64(rd, rd, rn);
+}
+
+static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
+{
+ tcg_gen_xor_vec(vece, rn, rn, rm);
+ tcg_gen_and_vec(vece, rn, rn, rd);
+ tcg_gen_xor_vec(vece, rd, rm, rn);
+}
+
+static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
+{
+ tcg_gen_xor_vec(vece, rn, rn, rd);
+ tcg_gen_and_vec(vece, rn, rn, rm);
+ tcg_gen_xor_vec(vece, rd, rd, rn);
+}
+
+static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
+{
+ tcg_gen_xor_vec(vece, rn, rn, rd);
+ tcg_gen_andc_vec(vece, rn, rn, rm);
+ tcg_gen_xor_vec(vece, rd, rd, rn);
+}
+
/* Logic op (opcode == 3) subgroup of C3.6.16. */
static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
{
+ static const GVecGen3 bsl_op = {
+ .fni8 = gen_bsl_i64,
+ .fniv = gen_bsl_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true
+ };
+ static const GVecGen3 bit_op = {
+ .fni8 = gen_bit_i64,
+ .fniv = gen_bit_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true
+ };
+ static const GVecGen3 bif_op = {
+ .fni8 = gen_bif_i64,
+ .fniv = gen_bif_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true
+ };
+
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int rm = extract32(insn, 16, 5);
int size = extract32(insn, 22, 2);
bool is_u = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
- TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
- int pass;
+ GVecGen3Fn *gvec_fn;
+ const GVecGen3 *gvec_op;
if (!fp_access_check(s)) {
return;
}
- tcg_op1 = tcg_temp_new_i64();
- tcg_op2 = tcg_temp_new_i64();
- tcg_res[0] = tcg_temp_new_i64();
- tcg_res[1] = tcg_temp_new_i64();
-
- for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
- read_vec_element(s, tcg_op1, rn, pass, MO_64);
- read_vec_element(s, tcg_op2, rm, pass, MO_64);
-
- if (!is_u) {
- switch (size) {
- case 0: /* AND */
- tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- case 1: /* BIC */
- tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- case 2: /* ORR */
- tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- case 3: /* ORN */
- tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- }
- } else {
- if (size != 0) {
- /* B* ops need res loaded to operate on */
- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
- }
-
- switch (size) {
- case 0: /* EOR */
- tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- case 1: /* BSL bitwise select */
- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2);
- tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]);
- tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1);
- break;
- case 2: /* BIT, bitwise insert if true */
- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);
- tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2);
- tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
- break;
- case 3: /* BIF, bitwise insert if false */
- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);
- tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2);
- tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
- break;
- }
- }
- }
+ switch (size + 4 * is_u) {
+ case 0: /* AND */
+ gvec_fn = tcg_gen_gvec_and;
+ goto do_fn;
+ case 1: /* BIC */
+ gvec_fn = tcg_gen_gvec_andc;
+ goto do_fn;
+ case 2: /* ORR */
+ gvec_fn = tcg_gen_gvec_or;
+ goto do_fn;
+ case 3: /* ORN */
+ gvec_fn = tcg_gen_gvec_orc;
+ goto do_fn;
+ case 4: /* EOR */
+ gvec_fn = tcg_gen_gvec_xor;
+ goto do_fn;
+ do_fn:
+ gvec_fn(0, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+
+ case 5: /* BSL bitwise select */
+ gvec_op = &bsl_op;
+ goto do_op;
+ case 6: /* BIT, bitwise insert if true */
+ gvec_op = &bit_op;
+ goto do_op;
+ case 7: /* BIF, bitwise insert if false */
+ gvec_op = &bif_op;
+ goto do_op;
+ do_op:
+ tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s), gvec_op);
+ return;
- write_vec_element(s, tcg_res[0], rd, 0, MO_64);
- if (!is_q) {
- tcg_gen_movi_i64(tcg_res[1], 0);
+ default:
+ g_assert_not_reached();
}
- write_vec_element(s, tcg_res[1], rd, 1, MO_64);
-
- tcg_temp_free_i64(tcg_op1);
- tcg_temp_free_i64(tcg_op2);
- tcg_temp_free_i64(tcg_res[0]);
- tcg_temp_free_i64(tcg_res[1]);
}
/* Helper functions for 32 bit comparisons */
@@ -9387,6 +9447,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
int pass;
+ GVecGen3Fn *gvec_op;
switch (opcode) {
case 0x13: /* MUL, PMUL */
@@ -9426,6 +9487,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
return;
}
+ switch (opcode) {
+ case 0x10: /* ADD, SUB */
+ gvec_op = u ? tcg_gen_gvec_sub : tcg_gen_gvec_add;
+ gvec_op(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+ }
+
if (size == 3) {
assert(is_q);
for (pass = 0; pass < 2; pass++) {
@@ -9598,16 +9669,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn = fns[size][u];
break;
}
- case 0x10: /* ADD, SUB */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
- { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
- { tcg_gen_add_i32, tcg_gen_sub_i32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0x11: /* CMTST, CMEQ */
{
static NeonGenTwoOpFn * const fns[3][2] = {
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 17/26] target/arm: Use vector infrastructure for aa64 mov/not/neg
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (15 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 16/26] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 18/26] target/arm: Use vector infrastructure for aa64 dup/movi Richard Henderson
` (11 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 43 ++++++++++++++++++++++++++++++++++++++-----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 572af456d1..bc14c28e71 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -85,6 +85,7 @@ typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
/* Note that the gvec expanders operate on offsets + sizes. */
+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t);
@@ -4579,14 +4580,19 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
TCGv_i64 tcg_op;
TCGv_i64 tcg_res;
+ switch (opcode) {
+ case 0x0: /* FMOV */
+ tcg_gen_gvec_mov(0, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ 8, vec_full_reg_size(s));
+ return;
+ }
+
fpst = get_fpstatus_ptr();
tcg_op = read_fp_dreg(s, rn);
tcg_res = tcg_temp_new_i64();
switch (opcode) {
- case 0x0: /* FMOV */
- tcg_gen_mov_i64(tcg_res, tcg_op);
- break;
case 0x1: /* FABS */
gen_helper_vfp_absd(tcg_res, tcg_op);
break;
@@ -9153,6 +9159,12 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
gvec_fn = tcg_gen_gvec_andc;
goto do_fn;
case 2: /* ORR */
+ if (rn == rm) { /* MOV */
+ tcg_gen_gvec_mov(0, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+ }
gvec_fn = tcg_gen_gvec_or;
goto do_fn;
case 3: /* ORN */
@@ -10032,6 +10044,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
int rmode = -1;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
+ GVecGen2Fn *gvec_fn;
switch (opcode) {
case 0x0: /* REV64, REV32 */
@@ -10040,8 +10053,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
case 0x5: /* CNT, NOT, RBIT */
if (u && size == 0) {
- /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
- size = 3;
+ /* NOT */
break;
} else if (u && size == 1) {
/* RBIT */
@@ -10293,6 +10305,27 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_rmode = NULL;
}
+ switch (opcode) {
+ case 0x5:
+ if (u && size == 0) { /* NOT */
+ gvec_fn = tcg_gen_gvec_not;
+ goto do_fn;
+ }
+ break;
+ case 0xb:
+ if (u) { /* NEG */
+ gvec_fn = tcg_gen_gvec_neg;
+ goto do_fn;
+ }
+ break;
+
+ do_fn:
+ gvec_fn(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+ }
+
if (size == 3) {
/* All 64-bit element operations can be shared with scalar 2misc */
int pass;
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 18/26] target/arm: Use vector infrastructure for aa64 dup/movi
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (16 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 17/26] target/arm: Use vector infrastructure for aa64 mov/not/neg Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 19/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn Richard Henderson
` (10 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 83 +++++++++++++++++++---------------------------
1 file changed, 34 insertions(+), 49 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index bc14c28e71..55a4902fc2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5846,38 +5846,24 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
*
* size: encoded in imm5 (see ARM ARM LowestSetBit())
*/
+
static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
int imm5)
{
int size = ctz32(imm5);
- int esize = 8 << size;
- int elements = (is_q ? 128 : 64) / esize;
- int index, i;
- TCGv_i64 tmp;
+ int index = imm5 >> (size + 1);
if (size > 3 || (size == 3 && !is_q)) {
unallocated_encoding(s);
return;
}
-
if (!fp_access_check(s)) {
return;
}
- index = imm5 >> (size + 1);
-
- tmp = tcg_temp_new_i64();
- read_vec_element(s, tmp, rn, index, size);
-
- for (i = 0; i < elements; i++) {
- write_vec_element(s, tmp, rd, i, size);
- }
-
- if (!is_q) {
- clear_vec_high(s, rd);
- }
-
- tcg_temp_free_i64(tmp);
+ tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd),
+ vec_reg_offset(s, rn, index, size),
+ is_q ? 16 : 8, vec_full_reg_size(s));
}
/* DUP (element, scalar)
@@ -5926,9 +5912,7 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
int imm5)
{
int size = ctz32(imm5);
- int esize = 8 << size;
- int elements = (is_q ? 128 : 64)/esize;
- int i = 0;
+ uint32_t dofs, oprsz, maxsz;
if (size > 3 || ((size == 3) && !is_q)) {
unallocated_encoding(s);
@@ -5939,12 +5923,11 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
return;
}
- for (i = 0; i < elements; i++) {
- write_vec_element(s, cpu_reg(s, rn), rd, i, size);
- }
- if (!is_q) {
- clear_vec_high(s, rd);
- }
+ dofs = vec_full_reg_offset(s, rd);
+ oprsz = is_q ? 16 : 8;
+ maxsz = vec_full_reg_size(s);
+
+ tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn));
}
/* INS (Element)
@@ -6135,7 +6118,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
bool is_neg = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
uint64_t imm = 0;
- TCGv_i64 tcg_rd, tcg_imm;
int i;
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
@@ -6217,32 +6199,35 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
imm = ~imm;
}
- tcg_imm = tcg_const_i64(imm);
- tcg_rd = new_tmp_a64(s);
+ if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
+ /* MOVI or MVNI, with MVNI negation handled above. */
+ tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
+ vec_full_reg_size(s), imm);
+ } else {
+ TCGv_i64 tcg_imm = tcg_const_i64(imm);
+ TCGv_i64 tcg_rd = new_tmp_a64(s);
- for (i = 0; i < 2; i++) {
- int foffs = i ? fp_reg_hi_offset(s, rd) : fp_reg_offset(s, rd, MO_64);
+ for (i = 0; i < 2; i++) {
+ int foffs = vec_reg_offset(s, rd, i, MO_64);
- if (i == 1 && !is_q) {
- /* non-quad ops clear high half of vector */
- tcg_gen_movi_i64(tcg_rd, 0);
- } else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) {
- tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
- if (is_neg) {
- /* AND (BIC) */
- tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
+ if (i == 1 && !is_q) {
+ /* non-quad ops clear high half of vector */
+ tcg_gen_movi_i64(tcg_rd, 0);
} else {
- /* ORR */
- tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
+ tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
+ if (is_neg) {
+ /* AND (BIC) */
+ tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
+ } else {
+ /* ORR */
+ tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
+ }
}
- } else {
- /* MOVI */
- tcg_gen_mov_i64(tcg_rd, tcg_imm);
+ tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
}
- tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
- }
- tcg_temp_free_i64(tcg_imm);
+ tcg_temp_free_i64(tcg_imm);
+ }
}
/* AdvSIMD scalar copy
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 19/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (17 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 18/26] target/arm: Use vector infrastructure for aa64 dup/movi Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 20/26] target/arm: Use vector infrastructure for aa64 constant shifts Richard Henderson
` (9 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 103 +++++++++++++++------------------------------
1 file changed, 35 insertions(+), 68 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 55a4902fc2..8769b4505a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5576,11 +5576,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
int opcode = extract32(insn, 12, 2);
bool part = extract32(insn, 14, 1);
bool is_q = extract32(insn, 30, 1);
- int esize = 8 << size;
- int i, ofs;
- int datasize = is_q ? 128 : 64;
- int elements = datasize / esize;
- TCGv_i64 tcg_res, tcg_resl, tcg_resh;
+ GVecGen3Fn *gvec_fn;
if (opcode == 0 || (size == 3 && !is_q)) {
unallocated_encoding(s);
@@ -5591,60 +5587,24 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
return;
}
- tcg_resl = tcg_const_i64(0);
- tcg_resh = tcg_const_i64(0);
- tcg_res = tcg_temp_new_i64();
-
- for (i = 0; i < elements; i++) {
- switch (opcode) {
- case 1: /* UZP1/2 */
- {
- int midpoint = elements / 2;
- if (i < midpoint) {
- read_vec_element(s, tcg_res, rn, 2 * i + part, size);
- } else {
- read_vec_element(s, tcg_res, rm,
- 2 * (i - midpoint) + part, size);
- }
- break;
- }
- case 2: /* TRN1/2 */
- if (i & 1) {
- read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
- } else {
- read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
- }
- break;
- case 3: /* ZIP1/2 */
- {
- int base = part * elements / 2;
- if (i & 1) {
- read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
- } else {
- read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
- }
- break;
- }
- default:
- g_assert_not_reached();
- }
-
- ofs = i * esize;
- if (ofs < 64) {
- tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
- tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
- } else {
- tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
- tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
- }
+ switch (opcode) {
+ case 1: /* UZP1/2 */
+ gvec_fn = part ? tcg_gen_gvec_uzpo : tcg_gen_gvec_uzpe;
+ break;
+ case 2: /* TRN1/2 */
+ gvec_fn = part ? tcg_gen_gvec_trno : tcg_gen_gvec_trne;
+ break;
+ case 3: /* ZIP1/2 */
+ gvec_fn = part ? tcg_gen_gvec_ziph : tcg_gen_gvec_zipl;
+ break;
+ default:
+ g_assert_not_reached();
}
- tcg_temp_free_i64(tcg_res);
-
- write_vec_element(s, tcg_resl, rd, 0, MO_64);
- tcg_temp_free_i64(tcg_resl);
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
- tcg_temp_free_i64(tcg_resh);
+ gvec_fn(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
}
static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
@@ -7922,6 +7882,22 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
int destelt = is_q ? 2 : 0;
int passes = scalar ? 1 : 2;
+ if (opcode == 0x12 && !u) { /* XTN, XTN2 */
+ tcg_debug_assert(!scalar);
+ if (is_q) { /* XTN2 */
+ tcg_gen_gvec_uzpe(size, vec_reg_offset(s, rd, 1, MO_64),
+ vec_reg_offset(s, rn, 0, MO_64),
+ vec_reg_offset(s, rn, 1, MO_64),
+ 8, vec_full_reg_size(s) - 8);
+ } else {
+ tcg_gen_gvec_uzpe(size, vec_reg_offset(s, rd, 0, MO_64),
+ vec_reg_offset(s, rn, 0, MO_64),
+ vec_reg_offset(s, rn, 1, MO_64),
+ 8, vec_full_reg_size(s));
+ }
+ return;
+ }
+
if (scalar) {
tcg_res[1] = tcg_const_i32(0);
}
@@ -7939,23 +7915,14 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
tcg_res[pass] = tcg_temp_new_i32();
switch (opcode) {
- case 0x12: /* XTN, SQXTUN */
+ case 0x12: /* , SQXTUN */
{
- static NeonGenNarrowFn * const xtnfns[3] = {
- gen_helper_neon_narrow_u8,
- gen_helper_neon_narrow_u16,
- tcg_gen_extrl_i64_i32,
- };
static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
gen_helper_neon_unarrow_sat8,
gen_helper_neon_unarrow_sat16,
gen_helper_neon_unarrow_sat32,
};
- if (u) {
- genenvfn = sqxtunfns[size];
- } else {
- genfn = xtnfns[size];
- }
+ genenvfn = sqxtunfns[size];
break;
}
case 0x14: /* SQXTN, UQXTN */
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 20/26] target/arm: Use vector infrastructure for aa64 constant shifts
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (18 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 19/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 21/26] target/arm: Use vector infrastructure for aa64 compares Richard Henderson
` (8 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 386 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 329 insertions(+), 57 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8769b4505a..d8bb3bbb25 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6432,17 +6432,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
}
}
-/* Common SHL/SLI - Shift left with an optional insert */
-static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
- bool insert, int shift)
-{
- if (insert) { /* SLI */
- tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift);
- } else { /* SHL */
- tcg_gen_shli_i64(tcg_res, tcg_src, shift);
- }
-}
-
/* SRI: shift right with insert */
static void handle_shri_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
int size, int shift)
@@ -6546,7 +6535,11 @@ static void handle_scalar_simd_shli(DisasContext *s, bool insert,
tcg_rn = read_fp_dreg(s, rn);
tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
- handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
+ if (insert) {
+ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift);
+ } else {
+ tcg_gen_shli_i64(tcg_rd, tcg_rn, shift);
+ }
write_fp_dreg(s, rd, tcg_rd);
@@ -8283,16 +8276,195 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
}
+static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ tcg_gen_vec_sar8i_i64(a, a, shift);
+ tcg_gen_vec_add8_i64(d, d, a);
+}
+
+static void gen_ssra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ tcg_gen_vec_sar16i_i64(a, a, shift);
+ tcg_gen_vec_add16_i64(d, d, a);
+}
+
+static void gen_ssra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
+{
+ tcg_gen_sari_i32(a, a, shift);
+ tcg_gen_add_i32(d, d, a);
+}
+
+static void gen_ssra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ tcg_gen_sari_i64(a, a, shift);
+ tcg_gen_add_i64(d, d, a);
+}
+
+static void gen_ssra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
+{
+ tcg_gen_sari_vec(vece, a, a, sh);
+ tcg_gen_add_vec(vece, d, d, a);
+}
+
+static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ tcg_gen_vec_shr8i_i64(a, a, shift);
+ tcg_gen_vec_add8_i64(d, d, a);
+}
+
+static void gen_usra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ tcg_gen_vec_shr16i_i64(a, a, shift);
+ tcg_gen_vec_add16_i64(d, d, a);
+}
+
+static void gen_usra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
+{
+ tcg_gen_shri_i32(a, a, shift);
+ tcg_gen_add_i32(d, d, a);
+}
+
+static void gen_usra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ tcg_gen_shri_i64(a, a, shift);
+ tcg_gen_add_i64(d, d, a);
+}
+
+static void gen_usra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
+{
+ tcg_gen_shri_vec(vece, a, a, sh);
+ tcg_gen_add_vec(vece, d, d, a);
+}
+
+static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ uint64_t mask = (0xff >> shift) * (-1ull / 0xff);
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(t, a, shift);
+ tcg_gen_andi_i64(t, t, mask);
+ tcg_gen_andi_i64(d, d, ~mask);
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ uint64_t mask = (0xffff >> shift) * (-1ull / 0xffff);
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(t, a, shift);
+ tcg_gen_andi_i64(t, t, mask);
+ tcg_gen_andi_i64(d, d, ~mask);
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_shr32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
+{
+ tcg_gen_shri_i32(a, a, shift);
+ tcg_gen_deposit_i32(d, d, a, 0, 32 - shift);
+}
+
+static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ tcg_gen_shri_i64(a, a, shift);
+ tcg_gen_deposit_i64(d, d, a, 0, 64 - shift);
+}
+
+static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
+{
+ uint64_t mask = (2ull << ((8 << vece) - 1)) - 1;
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_temp_new_vec_matching(d);
+
+ tcg_gen_dupi_vec(vece, m, mask ^ (mask >> sh));
+ tcg_gen_shri_vec(vece, t, a, sh);
+ tcg_gen_and_vec(vece, d, d, m);
+ tcg_gen_or_vec(vece, d, d, t);
+
+ tcg_temp_free_vec(t);
+ tcg_temp_free_vec(m);
+}
+
/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
int immh, int immb, int opcode, int rn, int rd)
{
+ static const GVecGen2i ssra_op[4] = {
+ { .fni8 = gen_ssra8_i64,
+ .fniv = gen_ssra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_8 },
+ { .fni8 = gen_ssra16_i64,
+ .fniv = gen_ssra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_16 },
+ { .fni4 = gen_ssra32_i32,
+ .fniv = gen_ssra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_32 },
+ { .fni8 = gen_ssra64_i64,
+ .fniv = gen_ssra_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_64 },
+ };
+ static const GVecGen2i usra_op[4] = {
+ { .fni8 = gen_usra8_i64,
+ .fniv = gen_usra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_8, },
+ { .fni8 = gen_usra16_i64,
+ .fniv = gen_usra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_16, },
+ { .fni4 = gen_usra32_i32,
+ .fniv = gen_usra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_32, },
+ { .fni8 = gen_usra64_i64,
+ .fniv = gen_usra_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_64, },
+ };
+ static const GVecGen2i sri_op[4] = {
+ { .fni8 = gen_shr8_ins_i64,
+ .fniv = gen_shr_ins_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_8 },
+ { .fni8 = gen_shr16_ins_i64,
+ .fniv = gen_shr_ins_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_16 },
+ { .fni4 = gen_shr32_ins_i32,
+ .fniv = gen_shr_ins_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_32 },
+ { .fni8 = gen_shr64_ins_i64,
+ .fniv = gen_shr_ins_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_64 },
+ };
+
int size = 32 - clz32(immh) - 1;
int immhb = immh << 3 | immb;
int shift = 2 * (8 << size) - immhb;
bool accumulate = false;
- bool round = false;
- bool insert = false;
int dsize = is_q ? 128 : 64;
int esize = 8 << size;
int elements = dsize/esize;
@@ -8300,6 +8472,8 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
TCGv_i64 tcg_rn = new_tmp_a64(s);
TCGv_i64 tcg_rd = new_tmp_a64(s);
TCGv_i64 tcg_round;
+ uint64_t round_const;
+ const GVecGen2i *gvec_op;
int i;
if (extract32(immh, 3, 1) && !is_q) {
@@ -8318,64 +8492,141 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
switch (opcode) {
case 0x02: /* SSRA / USRA (accumulate) */
- accumulate = true;
- break;
+ if (is_u) {
+ /* Shift count same as element size produces zero to add. */
+ if (shift == 8 << size) {
+ goto done;
+ }
+ gvec_op = &usra_op[size];
+ } else {
+ /* Shift count same as element size produces all sign to add. */
+ if (shift == 8 << size) {
+ shift -= 1;
+ }
+ gvec_op = &ssra_op[size];
+ }
+ goto do_gvec;
+ case 0x08: /* SRI */
+ /* Shift count same as element size is valid but does nothing. */
+ if (shift == 8 << size) {
+ goto done;
+ }
+ gvec_op = &sri_op[size];
+ do_gvec:
+ tcg_gen_gvec_2i(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift, gvec_op);
+ return;
+
+ case 0x00: /* SSHR / USHR */
+ if (is_u) {
+ if (shift == 8 << size) {
+ /* Shift count the same size as element size produces zero. */
+ tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd),
+ is_q ? 16 : 8, vec_full_reg_size(s), 0);
+ } else {
+ tcg_gen_gvec_shri(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift);
+ }
+ } else {
+ /* Shift count the same size as element size produces all sign. */
+ if (shift == 8 << size) {
+ shift -= 1;
+ }
+ tcg_gen_gvec_sari(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift);
+ }
+ return;
+
case 0x04: /* SRSHR / URSHR (rounding) */
- round = true;
break;
case 0x06: /* SRSRA / URSRA (accum + rounding) */
- accumulate = round = true;
- break;
- case 0x08: /* SRI */
- insert = true;
+ accumulate = true;
break;
+ default:
+ g_assert_not_reached();
}
- if (round) {
- uint64_t round_const = 1ULL << (shift - 1);
- tcg_round = tcg_const_i64(round_const);
- } else {
- tcg_round = NULL;
- }
+ round_const = 1ULL << (shift - 1);
+ tcg_round = tcg_const_i64(round_const);
for (i = 0; i < elements; i++) {
read_vec_element(s, tcg_rn, rn, i, memop);
- if (accumulate || insert) {
+ if (accumulate) {
read_vec_element(s, tcg_rd, rd, i, memop);
}
- if (insert) {
- handle_shri_with_ins(tcg_rd, tcg_rn, size, shift);
- } else {
- handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
- accumulate, is_u, size, shift);
- }
+ handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
+ accumulate, is_u, size, shift);
write_vec_element(s, tcg_rd, rd, i, size);
}
+ tcg_temp_free_i64(tcg_round);
+ done:
if (!is_q) {
clear_vec_high(s, rd);
}
+}
- if (round) {
- tcg_temp_free_i64(tcg_round);
- }
+static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ uint64_t mask = ((0xff << shift) & 0xff) * (-1ull / 0xff);
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_shli_i64(t, a, shift);
+ tcg_gen_andi_i64(t, t, mask);
+ tcg_gen_andi_i64(d, d, ~mask);
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ uint64_t mask = ((0xffff << shift) & 0xffff) * (-1ull / 0xffff);
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_shli_i64(t, a, shift);
+ tcg_gen_andi_i64(t, t, mask);
+ tcg_gen_andi_i64(d, d, ~mask);
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_shl32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
+{
+ tcg_gen_deposit_i32(d, d, a, shift, 32 - shift);
+}
+
+static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
+{
+ tcg_gen_deposit_i64(d, d, a, shift, 64 - shift);
+}
+
+static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
+{
+ uint64_t mask = (1ull << sh) - 1;
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_temp_new_vec_matching(d);
+
+ tcg_gen_dupi_vec(vece, m, mask);
+ tcg_gen_shli_vec(vece, t, a, sh);
+ tcg_gen_and_vec(vece, d, d, m);
+ tcg_gen_or_vec(vece, d, d, t);
+
+ tcg_temp_free_vec(t);
+ tcg_temp_free_vec(m);
}
/* SHL/SLI - Vector shift left */
static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
- int immh, int immb, int opcode, int rn, int rd)
+ int immh, int immb, int opcode, int rn, int rd)
{
int size = 32 - clz32(immh) - 1;
int immhb = immh << 3 | immb;
int shift = immhb - (8 << size);
- int dsize = is_q ? 128 : 64;
- int esize = 8 << size;
- int elements = dsize/esize;
- TCGv_i64 tcg_rn = new_tmp_a64(s);
- TCGv_i64 tcg_rd = new_tmp_a64(s);
- int i;
if (extract32(immh, 3, 1) && !is_q) {
unallocated_encoding(s);
@@ -8391,19 +8642,40 @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
return;
}
- for (i = 0; i < elements; i++) {
- read_vec_element(s, tcg_rn, rn, i, size);
- if (insert) {
- read_vec_element(s, tcg_rd, rd, i, size);
- }
-
- handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
-
- write_vec_element(s, tcg_rd, rd, i, size);
- }
-
- if (!is_q) {
- clear_vec_high(s, rd);
+ if (insert) {
+ static const GVecGen2i shi_op[4] = {
+ { .fni8 = gen_shl8_ins_i64,
+ .fniv = gen_shl_ins_vec,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_8 },
+ { .fni8 = gen_shl16_ins_i64,
+ .fniv = gen_shl_ins_vec,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_16 },
+ { .fni4 = gen_shl32_ins_i32,
+ .fniv = gen_shl_ins_vec,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_32 },
+ { .fni8 = gen_shl64_ins_i64,
+ .fniv = gen_shl_ins_vec,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_64 },
+ };
+ tcg_gen_gvec_2i(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift, &shi_op[size]);
+ } else {
+ tcg_gen_gvec_shli(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift);
}
}
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 21/26] target/arm: Use vector infrastructure for aa64 compares
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (19 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 20/26] target/arm: Use vector infrastructure for aa64 constant shifts Richard Henderson
@ 2018-01-16 3:33 ` Richard Henderson
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 22/26] target/arm: Use vector infrastructure for aa64 multiplies Richard Henderson
` (7 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:33 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 96 ++++++++++++++++++++++++++++++----------------
1 file changed, 62 insertions(+), 34 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d8bb3bbb25..44e44cc9f2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7115,6 +7115,28 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
}
}
+/* CMTST : test is "if (X & Y != 0)". */
+static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_and_i32(d, a, b);
+ tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0);
+ tcg_gen_neg_i32(d, d);
+}
+
+static void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_and_i64(d, a, b);
+ tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0);
+ tcg_gen_neg_i64(d, d);
+}
+
+static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_and_vec(vece, d, a, b);
+ tcg_gen_dupi_vec(vece, a, 0);
+ tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a);
+}
+
static void handle_3same_64(DisasContext *s, int opcode, bool u,
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
{
@@ -7158,10 +7180,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
cond = TCG_COND_EQ;
goto do_cmop;
}
- /* CMTST : test is "if (X & Y != 0)". */
- tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
- tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0);
- tcg_gen_neg_i64(tcg_rd, tcg_rd);
+ gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm);
break;
case 0x8: /* SSHL, USHL */
if (u) {
@@ -9684,6 +9703,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
int rd = extract32(insn, 0, 5);
int pass;
GVecGen3Fn *gvec_op;
+ TCGCond cond;
switch (opcode) {
case 0x13: /* MUL, PMUL */
@@ -9731,6 +9751,44 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
vec_full_reg_offset(s, rm),
is_q ? 16 : 8, vec_full_reg_size(s));
return;
+ case 0x11:
+ if (u) { /* CMEQ */
+ cond = TCG_COND_EQ;
+ goto do_gvec_cmp;
+ } else { /* CMTST */
+ static const GVecGen3 cmtst_op[4] = {
+ { .fni4 = gen_helper_neon_tst_u8,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_8 },
+ { .fni4 = gen_helper_neon_tst_u16,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_16 },
+ { .fni4 = gen_cmtst_i32,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_32 },
+ { .fni8 = gen_cmtst_i64,
+ .fniv = gen_cmtst_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+ tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s),
+ &cmtst_op[size]);
+ }
+ return;
+ case 0x06: /* CMGT, CMHI */
+ cond = u ? TCG_COND_GTU : TCG_COND_GT;
+ goto do_gvec_cmp;
+ case 0x07: /* CMGE, CMHS */
+ cond = u ? TCG_COND_GEU : TCG_COND_GE;
+ do_gvec_cmp:
+ tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
}
if (size == 3) {
@@ -9813,26 +9871,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genenvfn = fns[size][u];
break;
}
- case 0x6: /* CMGT, CMHI */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 },
- { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 },
- { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 },
- };
- genfn = fns[size][u];
- break;
- }
- case 0x7: /* CMGE, CMHS */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 },
- { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 },
- { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0x8: /* SSHL, USHL */
{
static NeonGenTwoOpFn * const fns[3][2] = {
@@ -9905,16 +9943,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn = fns[size][u];
break;
}
- case 0x11: /* CMTST, CMEQ */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 },
- { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 },
- { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0x13: /* MUL, PMUL */
if (u) {
/* PMUL */
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 22/26] target/arm: Use vector infrastructure for aa64 multiplies
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (20 preceding siblings ...)
2018-01-16 3:33 ` [Qemu-devel] [PATCH v9 21/26] target/arm: Use vector infrastructure for aa64 compares Richard Henderson
@ 2018-01-16 3:34 ` Richard Henderson
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 23/26] target/arm: Use vector infrastructure for aa64 widening shifts Richard Henderson
` (6 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 171 ++++++++++++++++++++++++++++++++++++---------
1 file changed, 138 insertions(+), 33 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 44e44cc9f2..48caba3d9f 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9691,6 +9691,66 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
}
}
+static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_helper_neon_mul_u8(a, a, b);
+ gen_helper_neon_add_u8(d, d, a);
+}
+
+static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_helper_neon_mul_u16(a, a, b);
+ gen_helper_neon_add_u16(d, d, a);
+}
+
+static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_mul_i32(a, a, b);
+ tcg_gen_add_i32(d, d, a);
+}
+
+static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_mul_i64(a, a, b);
+ tcg_gen_add_i64(d, d, a);
+}
+
+static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_mul_vec(vece, a, a, b);
+ tcg_gen_add_vec(vece, d, d, a);
+}
+
+static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_helper_neon_mul_u8(a, a, b);
+ gen_helper_neon_sub_u8(d, d, a);
+}
+
+static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_helper_neon_mul_u16(a, a, b);
+ gen_helper_neon_sub_u16(d, d, a);
+}
+
+static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_mul_i32(a, a, b);
+ tcg_gen_sub_i32(d, d, a);
+}
+
+static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_mul_i64(a, a, b);
+ tcg_gen_sub_i64(d, d, a);
+}
+
+static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_mul_vec(vece, a, a, b);
+ tcg_gen_sub_vec(vece, d, d, a);
+}
+
/* Integer op subgroup of C3.6.16. */
static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
{
@@ -9702,7 +9762,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
int pass;
- GVecGen3Fn *gvec_op;
+ GVecGen3Fn *gvec_fn;
+ const GVecGen3 *gvec_op;
TCGCond cond;
switch (opcode) {
@@ -9745,12 +9806,70 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
switch (opcode) {
case 0x10: /* ADD, SUB */
- gvec_op = u ? tcg_gen_gvec_sub : tcg_gen_gvec_add;
- gvec_op(size, vec_full_reg_offset(s, rd),
+ gvec_fn = u ? tcg_gen_gvec_sub : tcg_gen_gvec_add;
+ do_gvec:
+ gvec_fn(size, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
is_q ? 16 : 8, vec_full_reg_size(s));
return;
+ case 0x13: /* MUL, PMUL */
+ if (!u) { /* MUL */
+ gvec_fn = tcg_gen_gvec_mul;
+ goto do_gvec;
+ }
+ break;
+ case 0x12: /* MLA, MLS */
+ {
+ static const GVecGen3 mla_op[4] = {
+ { .fni4 = gen_mla8_i32,
+ .fniv = gen_mla_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_8 },
+ { .fni4 = gen_mla16_i32,
+ .fniv = gen_mla_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_16 },
+ { .fni4 = gen_mla32_i32,
+ .fniv = gen_mla_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_32 },
+ { .fni8 = gen_mla64_i64,
+ .fniv = gen_mla_vec,
+ .opc = INDEX_op_mul_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_64 },
+ };
+ static const GVecGen3 mls_op[4] = {
+ { .fni4 = gen_mls8_i32,
+ .fniv = gen_mls_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_8 },
+ { .fni4 = gen_mls16_i32,
+ .fniv = gen_mls_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_16 },
+ { .fni4 = gen_mls32_i32,
+ .fniv = gen_mls_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_32 },
+ { .fni8 = gen_mls64_i64,
+ .fniv = gen_mls_vec,
+ .opc = INDEX_op_mul_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_64 },
+ };
+ gvec_op = (u ? &mls_op[size] : &mla_op[size]);
+ }
+ goto do_gvec_op;
case 0x11:
if (u) { /* CMEQ */
cond = TCG_COND_EQ;
@@ -9771,12 +9890,13 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
- tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
- vec_full_reg_offset(s, rn),
- vec_full_reg_offset(s, rm),
- is_q ? 16 : 8, vec_full_reg_size(s),
- &cmtst_op[size]);
+ gvec_op = &cmtst_op[size];
}
+ do_gvec_op:
+ tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s), gvec_op);
return;
case 0x06: /* CMGT, CMHI */
cond = u ? TCG_COND_GTU : TCG_COND_GT;
@@ -9944,23 +10064,10 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
break;
}
case 0x13: /* MUL, PMUL */
- if (u) {
- /* PMUL */
- assert(size == 0);
- genfn = gen_helper_neon_mul_p8;
- break;
- }
- /* fall through : MUL */
- case 0x12: /* MLA, MLS */
- {
- static NeonGenTwoOpFn * const fns[3] = {
- gen_helper_neon_mul_u8,
- gen_helper_neon_mul_u16,
- tcg_gen_mul_i32,
- };
- genfn = fns[size];
+ assert(u); /* PMUL */
+ assert(size == 0);
+ genfn = gen_helper_neon_mul_p8;
break;
- }
case 0x16: /* SQDMULH, SQRDMULH */
{
static NeonGenTwoOpEnvFn * const fns[2][2] = {
@@ -9981,18 +10088,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn(tcg_res, tcg_op1, tcg_op2);
}
- if (opcode == 0xf || opcode == 0x12) {
- /* SABA, UABA, MLA, MLS: accumulating ops */
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
- { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
- { tcg_gen_add_i32, tcg_gen_sub_i32 },
+ if (opcode == 0xf) {
+ /* SABA, UABA: accumulating ops */
+ static NeonGenTwoOpFn * const fns[3] = {
+ gen_helper_neon_add_u8,
+ gen_helper_neon_add_u16,
+ tcg_gen_add_i32,
};
- bool is_sub = (opcode == 0x12 && u); /* MLS */
- genfn = fns[size][is_sub];
read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
- genfn(tcg_res, tcg_op1, tcg_res);
+ fns[size](tcg_res, tcg_op1, tcg_res);
}
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 23/26] target/arm: Use vector infrastructure for aa64 widening shifts
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (21 preceding siblings ...)
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 22/26] target/arm: Use vector infrastructure for aa64 multiplies Richard Henderson
@ 2018-01-16 3:34 ` Richard Henderson
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 24/26] target/arm: Use vector infrastructure for aa64 orr/bic immediate Richard Henderson
` (5 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 48caba3d9f..4f15e58556 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -8705,12 +8705,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
int size = 32 - clz32(immh) - 1;
int immhb = immh << 3 | immb;
int shift = immhb - (8 << size);
- int dsize = 64;
- int esize = 8 << size;
- int elements = dsize/esize;
- TCGv_i64 tcg_rn = new_tmp_a64(s);
- TCGv_i64 tcg_rd = new_tmp_a64(s);
- int i;
+ GVecGen2Fn *gvec_fn;
if (size >= 3) {
unallocated_encoding(s);
@@ -8721,18 +8716,18 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
return;
}
- /* For the LL variants the store is larger than the load,
- * so if rd == rn we would overwrite parts of our input.
- * So load everything right now and use shifts in the main loop.
- */
- read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);
-
- for (i = 0; i < elements; i++) {
- tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);
- ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0);
- tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
- write_vec_element(s, tcg_rd, rd, i, size + 1);
+ if (is_u) {
+ gvec_fn = is_q ? tcg_gen_gvec_extuh : tcg_gen_gvec_extul;
+ } else {
+ gvec_fn = is_q ? tcg_gen_gvec_extsh : tcg_gen_gvec_extsl;
}
+ gvec_fn(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), 16, 16);
+
+ /* Perform the shift in the wider format. */
+ tcg_gen_gvec_shli(size + 1, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rd),
+ 16, vec_full_reg_size(s), shift);
}
/* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 24/26] target/arm: Use vector infrastructure for aa64 orr/bic immediate
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (22 preceding siblings ...)
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 23/26] target/arm: Use vector infrastructure for aa64 widening shifts Richard Henderson
@ 2018-01-16 3:34 ` Richard Henderson
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 25/26] tcg/i386: Add vector operations Richard Henderson
` (4 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 38 +++++++++++++++++---------------------
1 file changed, 17 insertions(+), 21 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 4f15e58556..5963eedd41 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6078,7 +6078,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
bool is_neg = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
uint64_t imm = 0;
- int i;
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
unallocated_encoding(s);
@@ -6164,28 +6163,25 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
vec_full_reg_size(s), imm);
} else {
+ /* ORR or BIC, with BIC negation to AND handled above. */
+ static const GVecGen2s ops[2] = {
+ { .fni8 = tcg_gen_or_i64,
+ .fniv = tcg_gen_or_vec,
+ .opc = INDEX_op_or_vec,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64 },
+ { .fni8 = tcg_gen_and_i64,
+ .fniv = tcg_gen_and_vec,
+ .opc = INDEX_op_and_vec,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
+ };
TCGv_i64 tcg_imm = tcg_const_i64(imm);
- TCGv_i64 tcg_rd = new_tmp_a64(s);
-
- for (i = 0; i < 2; i++) {
- int foffs = vec_reg_offset(s, rd, i, MO_64);
-
- if (i == 1 && !is_q) {
- /* non-quad ops clear high half of vector */
- tcg_gen_movi_i64(tcg_rd, 0);
- } else {
- tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
- if (is_neg) {
- /* AND (BIC) */
- tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
- } else {
- /* ORR */
- tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
- }
- }
- tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
- }
+ tcg_gen_gvec_2s(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rd),
+ is_q ? 16 : 8, vec_full_reg_size(s),
+ tcg_imm, &ops[is_neg]);
tcg_temp_free_i64(tcg_imm);
}
}
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 25/26] tcg/i386: Add vector operations
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (23 preceding siblings ...)
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 24/26] target/arm: Use vector infrastructure for aa64 orr/bic immediate Richard Henderson
@ 2018-01-16 3:34 ` Richard Henderson
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 26/26] tcg/aarch64: " Richard Henderson
` (3 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The x86 vector instruction set is extremely irregular. With newer
editions, Intel has filled in some of the blanks. However, we don't
get many 64-bit operations until SSE4.2, introduced in 2009.
The subsequent edition was for AVX1, introduced in 2011, which added
three-operand addressing, and adjusts how all instructions should be
encoded.
Given the relatively narrow 2 year window between possible to support
and desirable to support, and to vastly simplify code maintainence,
I am only planning to support AVX1 and later cpus.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 46 +-
tcg/i386/tcg-target.opc.h | 13 +
tcg/i386/tcg-target.inc.c | 1331 +++++++++++++++++++++++++++++++++++++++++++--
3 files changed, 1336 insertions(+), 54 deletions(-)
create mode 100644 tcg/i386/tcg-target.opc.h
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b89dababf4..e77b95cc2c 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -30,10 +30,10 @@
#ifdef __x86_64__
# define TCG_TARGET_REG_BITS 64
-# define TCG_TARGET_NB_REGS 16
+# define TCG_TARGET_NB_REGS 32
#else
# define TCG_TARGET_REG_BITS 32
-# define TCG_TARGET_NB_REGS 8
+# define TCG_TARGET_NB_REGS 24
#endif
typedef enum {
@@ -56,6 +56,26 @@ typedef enum {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
+
+ TCG_REG_XMM0,
+ TCG_REG_XMM1,
+ TCG_REG_XMM2,
+ TCG_REG_XMM3,
+ TCG_REG_XMM4,
+ TCG_REG_XMM5,
+ TCG_REG_XMM6,
+ TCG_REG_XMM7,
+
+ /* 64-bit registers; likewise always define. */
+ TCG_REG_XMM8,
+ TCG_REG_XMM9,
+ TCG_REG_XMM10,
+ TCG_REG_XMM11,
+ TCG_REG_XMM12,
+ TCG_REG_XMM13,
+ TCG_REG_XMM14,
+ TCG_REG_XMM15,
+
TCG_REG_RAX = TCG_REG_EAX,
TCG_REG_RCX = TCG_REG_ECX,
TCG_REG_RDX = TCG_REG_EDX,
@@ -77,6 +97,8 @@ typedef enum {
extern bool have_bmi1;
extern bool have_popcnt;
+extern bool have_avx1;
+extern bool have_avx2;
/* optional instructions */
#define TCG_TARGET_HAS_div2_i32 1
@@ -146,6 +168,26 @@ extern bool have_popcnt;
#define TCG_TARGET_HAS_mulsh_i64 0
#endif
+/* We do not support older SSE systems, only beginning with AVX1. */
+#define TCG_TARGET_HAS_v64 have_avx1
+#define TCG_TARGET_HAS_v128 have_avx1
+#define TCG_TARGET_HAS_v256 have_avx2
+
+#define TCG_TARGET_HAS_andc_vec 1
+#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_shi_vec 1
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_zip_vec 1
+#define TCG_TARGET_HAS_uzp_vec 0
+#define TCG_TARGET_HAS_trn_vec 0
+#define TCG_TARGET_HAS_cmp_vec 1
+#define TCG_TARGET_HAS_mul_vec 1
+#define TCG_TARGET_HAS_extl_vec 1
+#define TCG_TARGET_HAS_exth_vec 0
+
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
((ofs) == 0 && (len) == 16))
diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target.opc.h
new file mode 100644
index 0000000000..e5fa88ba25
--- /dev/null
+++ b/tcg/i386/tcg-target.opc.h
@@ -0,0 +1,13 @@
+/* Target-specific opcodes for host vector expansion. These will be
+ emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ consider these to be UNSPEC with names. */
+
+DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC)
+DEF(x86_vpblendvb_vec, 1, 3, 0, IMPLVEC)
+DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)
+DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)
+DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)
+DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
+DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
+DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
+DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 63d27f10e7..4805da6130 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -28,9 +28,14 @@
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#if TCG_TARGET_REG_BITS == 64
"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
- "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
#else
"%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
+#endif
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
+ "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
+#if TCG_TARGET_REG_BITS == 64
+ "%xmm8", "%xmm9", "%xmm10", "%xmm11",
+ "%xmm12", "%xmm13", "%xmm14", "%xmm15",
#endif
};
#endif
@@ -60,6 +65,28 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_ECX,
TCG_REG_EDX,
TCG_REG_EAX,
+#endif
+ TCG_REG_XMM0,
+ TCG_REG_XMM1,
+ TCG_REG_XMM2,
+ TCG_REG_XMM3,
+ TCG_REG_XMM4,
+ TCG_REG_XMM5,
+#ifndef _WIN64
+ /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save
+ any of them. Therefore only allow xmm0-xmm5 to be allocated. */
+ TCG_REG_XMM6,
+ TCG_REG_XMM7,
+#if TCG_TARGET_REG_BITS == 64
+ TCG_REG_XMM8,
+ TCG_REG_XMM9,
+ TCG_REG_XMM10,
+ TCG_REG_XMM11,
+ TCG_REG_XMM12,
+ TCG_REG_XMM13,
+ TCG_REG_XMM14,
+ TCG_REG_XMM15,
+#endif
#endif
};
@@ -94,7 +121,7 @@ static const int tcg_target_call_oarg_regs[] = {
#define TCG_CT_CONST_I32 0x400
#define TCG_CT_CONST_WSZ 0x800
-/* Registers used with L constraint, which are the first argument
+/* Registers used with L constraint, which are the first argument
registers on x86_64, and two random call clobbered registers on
i386. */
#if TCG_TARGET_REG_BITS == 64
@@ -125,6 +152,8 @@ static bool have_cmov;
it there. Therefore we always define the variable. */
bool have_bmi1;
bool have_popcnt;
+bool have_avx1;
+bool have_avx2;
#ifdef CONFIG_CPUID_H
static bool have_movbe;
@@ -148,6 +177,8 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
if (value != (int32_t)value) {
tcg_abort();
}
+ /* FALLTHRU */
+ case R_386_32:
tcg_patch32(code_ptr, value);
break;
case R_386_PC8:
@@ -162,6 +193,14 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
}
}
+#if TCG_TARGET_REG_BITS == 64
+#define ALL_GENERAL_REGS 0x0000ffffu
+#define ALL_VECTOR_REGS 0xffff0000u
+#else
+#define ALL_GENERAL_REGS 0x000000ffu
+#define ALL_VECTOR_REGS 0x00ff0000u
+#endif
+
/* parse target specific constraints */
static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type)
@@ -192,21 +231,29 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
break;
case 'q':
+ /* A register that can be used as a byte operand. */
ct->ct |= TCG_CT_REG;
ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
break;
case 'Q':
+ /* A register with an addressable second byte (e.g. %ah). */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xf;
break;
case 'r':
+ /* A general register. */
ct->ct |= TCG_CT_REG;
- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
+ ct->u.regs |= ALL_GENERAL_REGS;
break;
case 'W':
/* With TZCNT/LZCNT, we can have operand-size as an input. */
ct->ct |= TCG_CT_CONST_WSZ;
break;
+ case 'x':
+ /* A vector register. */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs |= ALL_VECTOR_REGS;
+ break;
/* qemu_ld/st address constraint */
case 'L':
@@ -277,14 +324,17 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
# define P_REXB_RM 0
# define P_GS 0
#endif
-#define P_SIMDF3 0x10000 /* 0xf3 opcode prefix */
-#define P_SIMDF2 0x20000 /* 0xf2 opcode prefix */
+#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */
+#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */
+#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */
+#define P_VEXL 0x80000 /* Set VEX.L = 1 */
#define OPC_ARITH_EvIz (0x81)
#define OPC_ARITH_EvIb (0x83)
#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */
#define OPC_ANDN (0xf2 | P_EXT38)
#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))
+#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16)
#define OPC_BSF (0xbc | P_EXT)
#define OPC_BSR (0xbd | P_EXT)
#define OPC_BSWAP (0xc8 | P_EXT)
@@ -310,11 +360,68 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_MOVL_Iv (0xb8)
#define OPC_MOVBE_GyMy (0xf0 | P_EXT38)
#define OPC_MOVBE_MyGy (0xf1 | P_EXT38)
+#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16)
+#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16)
+#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2)
+#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16)
+#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16)
+#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3)
+#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3)
+#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3)
+#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16)
#define OPC_MOVSBL (0xbe | P_EXT)
#define OPC_MOVSWL (0xbf | P_EXT)
#define OPC_MOVSLQ (0x63 | P_REXW)
#define OPC_MOVZBL (0xb6 | P_EXT)
#define OPC_MOVZWL (0xb7 | P_EXT)
+#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16)
+#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16)
+#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16)
+#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16)
+#define OPC_PADDB (0xfc | P_EXT | P_DATA16)
+#define OPC_PADDW (0xfd | P_EXT | P_DATA16)
+#define OPC_PADDD (0xfe | P_EXT | P_DATA16)
+#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16)
+#define OPC_PAND (0xdb | P_EXT | P_DATA16)
+#define OPC_PANDN (0xdf | P_EXT | P_DATA16)
+#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16)
+#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16)
+#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16)
+#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16)
+#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16)
+#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16)
+#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16)
+#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16)
+#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16)
+#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16)
+#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16)
+#define OPC_POR (0xeb | P_EXT | P_DATA16)
+#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16)
+#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16)
+#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2)
+#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3)
+#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16)
+#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16)
+#define OPC_PSUBD (0xfa | P_EXT | P_DATA16)
+#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16)
+#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16)
+#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16)
+#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16)
+#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16)
+#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16)
+#define OPC_PXOR (0xef | P_EXT | P_DATA16)
#define OPC_POP_r32 (0x58)
#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3)
#define OPC_PUSH_r32 (0x50)
@@ -326,14 +433,26 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_SHIFT_Ib (0xc1)
#define OPC_SHIFT_cl (0xd3)
#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3)
+#define OPC_SHUFPS (0xc6 | P_EXT)
#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
#define OPC_TESTL (0x85)
#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
+#define OPC_UD2 (0x0b | P_EXT)
+#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16)
+#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16)
+#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
+#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW)
+#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90)
#define OPC_GRP3_Ev (0xf7)
#define OPC_GRP5 (0xff)
+#define OPC_GRP14 (0x73 | P_EXT | P_DATA16)
/* Group 1 opcode extensions for 0x80-0x83.
These are also used as modifiers for OPC_ARITH. */
@@ -439,10 +558,12 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
tcg_out8(s, (uint8_t)(rex | 0x40));
}
- if (opc & (P_EXT | P_EXT38)) {
+ if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
tcg_out8(s, 0x0f);
if (opc & P_EXT38) {
tcg_out8(s, 0x38);
+ } else if (opc & P_EXT3A) {
+ tcg_out8(s, 0x3a);
}
}
@@ -459,10 +580,12 @@ static void tcg_out_opc(TCGContext *s, int opc)
} else if (opc & P_SIMDF2) {
tcg_out8(s, 0xf2);
}
- if (opc & (P_EXT | P_EXT38)) {
+ if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
tcg_out8(s, 0x0f);
if (opc & P_EXT38) {
tcg_out8(s, 0x38);
+ } else if (opc & P_EXT3A) {
+ tcg_out8(s, 0x3a);
}
}
tcg_out8(s, opc);
@@ -479,34 +602,42 @@ static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
}
-static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
+static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
+ int rm, int index)
{
int tmp;
- if ((opc & (P_REXW | P_EXT | P_EXT38)) || (rm & 8)) {
+ /* Use the two byte form if possible, which cannot encode
+ VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */
+ if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT
+ && ((rm | index) & 8) == 0) {
+ /* Two byte VEX prefix. */
+ tcg_out8(s, 0xc5);
+
+ tmp = (r & 8 ? 0 : 0x80); /* VEX.R */
+ } else {
/* Three byte VEX prefix. */
tcg_out8(s, 0xc4);
/* VEX.m-mmmm */
- if (opc & P_EXT38) {
+ if (opc & P_EXT3A) {
+ tmp = 3;
+ } else if (opc & P_EXT38) {
tmp = 2;
} else if (opc & P_EXT) {
tmp = 1;
} else {
- tcg_abort();
+ g_assert_not_reached();
}
- tmp |= 0x40; /* VEX.X */
- tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */
- tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
+ tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */
+ tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */
+ tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
tcg_out8(s, tmp);
- tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
- } else {
- /* Two byte VEX prefix. */
- tcg_out8(s, 0xc5);
-
- tmp = (r & 8 ? 0 : 0x80); /* VEX.R */
+ tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
}
+
+ tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */
/* VEX.pp */
if (opc & P_DATA16) {
tmp |= 1; /* 0x66 */
@@ -518,6 +649,11 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
tmp |= (~v & 15) << 3; /* VEX.vvvv */
tcg_out8(s, tmp);
tcg_out8(s, opc);
+}
+
+static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
+{
+ tcg_out_vex_opc(s, opc, r, v, rm, 0);
tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
}
@@ -526,8 +662,8 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
mode for absolute addresses, ~RM is the size of the immediate operand
that will follow the instruction. */
-static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
- int index, int shift, intptr_t offset)
+static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index,
+ int shift, intptr_t offset)
{
int mod, len;
@@ -538,7 +674,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm;
intptr_t disp = offset - pc;
if (disp == (int32_t)disp) {
- tcg_out_opc(s, opc, r, 0, 0);
tcg_out8(s, (LOWREGMASK(r) << 3) | 5);
tcg_out32(s, disp);
return;
@@ -548,7 +683,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
use of the MODRM+SIB encoding and is therefore larger than
rip-relative addressing. */
if (offset == (int32_t)offset) {
- tcg_out_opc(s, opc, r, 0, 0);
tcg_out8(s, (LOWREGMASK(r) << 3) | 4);
tcg_out8(s, (4 << 3) | 5);
tcg_out32(s, offset);
@@ -556,10 +690,9 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
}
/* ??? The memory isn't directly addressable. */
- tcg_abort();
+ g_assert_not_reached();
} else {
/* Absolute address. */
- tcg_out_opc(s, opc, r, 0, 0);
tcg_out8(s, (r << 3) | 5);
tcg_out32(s, offset);
return;
@@ -582,7 +715,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
that would be used for %esp is the escape to the two byte form. */
if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) {
/* Single byte MODRM format. */
- tcg_out_opc(s, opc, r, rm, 0);
tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
} else {
/* Two byte MODRM+SIB format. */
@@ -596,7 +728,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
tcg_debug_assert(index != TCG_REG_ESP);
}
- tcg_out_opc(s, opc, r, rm, index);
tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4);
tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm));
}
@@ -608,6 +739,21 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
}
}
+static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
+ int index, int shift, intptr_t offset)
+{
+ tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index);
+ tcg_out_sib_offset(s, r, rm, index, shift, offset);
+}
+
+static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v,
+ int rm, int index, int shift,
+ intptr_t offset)
+{
+ tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index);
+ tcg_out_sib_offset(s, r, rm, index, shift, offset);
+}
+
/* A simplification of the above with no index or shift. */
static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r,
int rm, intptr_t offset)
@@ -615,6 +761,30 @@ static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r,
tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset);
}
+static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r,
+ int v, int rm, intptr_t offset)
+{
+ tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset);
+}
+
+/* Output an opcode with an expected reference to the constant pool. */
+static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r)
+{
+ tcg_out_opc(s, opc, r, 0, 0);
+ /* Absolute for 32-bit, pc-relative for 64-bit. */
+ tcg_out8(s, LOWREGMASK(r) << 3 | 5);
+ tcg_out32(s, 0);
+}
+
+/* Output an opcode with an expected reference to the constant pool. */
+static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r)
+{
+ tcg_out_vex_opc(s, opc, r, 0, 0, 0);
+ /* Absolute for 32-bit, pc-relative for 64-bit. */
+ tcg_out8(s, LOWREGMASK(r) << 3 | 5);
+ tcg_out32(s, 0);
+}
+
/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */
static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
{
@@ -625,12 +795,116 @@ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src);
}
-static inline void tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
+static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ int rexw = 0;
+
+ if (arg == ret) {
+ return;
+ }
+ switch (type) {
+ case TCG_TYPE_I64:
+ rexw = P_REXW;
+ /* fallthru */
+ case TCG_TYPE_I32:
+ if (ret < 16) {
+ if (arg < 16) {
+ tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg);
+ } else {
+ tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, arg, 0, ret);
+ }
+ } else {
+ if (arg < 16) {
+ tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg);
+ } else {
+ tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
+ }
+ }
+ break;
+
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg);
+ break;
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg r, TCGReg a)
+{
+ if (have_avx2) {
+ static const int dup_insn[4] = {
+ OPC_VPBROADCASTB, OPC_VPBROADCASTW,
+ OPC_VPBROADCASTD, OPC_VPBROADCASTQ,
+ };
+ int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
+ tcg_out_vex_modrm(s, dup_insn[vece] + vex_l, r, 0, a);
+ } else {
+ switch (vece) {
+ case MO_8:
+ /* ??? With zero in a register, use PSHUFB. */
+ tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, 0, a);
+ a = r;
+ /* FALLTHRU */
+ case MO_16:
+ tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, 0, a);
+ a = r;
+ /* FALLTHRU */
+ case MO_32:
+ tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a);
+ /* imm8 operand: all output lanes selected from input lane 0. */
+ tcg_out8(s, 0);
+ break;
+ case MO_64:
+ tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, 0, a);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
{
- if (arg != ret) {
- int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
- tcg_out_modrm(s, opc, ret, arg);
+ int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
+
+ if (arg == 0) {
+ tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret);
+ return;
+ }
+ if (arg == -1) {
+ tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret);
+ return;
+ }
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (type == TCG_TYPE_V64) {
+ tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret);
+ } else if (have_avx2) {
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret);
+ } else {
+ tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret);
+ }
+ new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
+ } else if (have_avx2) {
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
+ new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
+ } else {
+ tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy, ret);
+ new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
+ tcg_out_dup_vec(s, type, MO_32, ret, ret);
}
}
@@ -639,6 +913,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
{
tcg_target_long diff;
+ switch (type) {
+ case TCG_TYPE_I32:
+#if TCG_TARGET_REG_BITS == 64
+ case TCG_TYPE_I64:
+#endif
+ if (ret < 16) {
+ break;
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_dupi_vec(s, type, ret, arg);
+ return;
+ default:
+ g_assert_not_reached();
+ }
+
if (arg == 0) {
tgen_arithr(s, ARITH_XOR, ret, ret);
return;
@@ -667,6 +960,59 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
tcg_out64(s, arg);
}
+static void tcg_out_movi_vec(TCGContext *s, TCGType type,
+ TCGReg ret, const TCGArg *a)
+{
+ int n = (64 / TCG_TARGET_REG_BITS) << (type - TCG_TYPE_V64);
+ int opc, ofs, rel;
+
+ tcg_debug_assert(ret >= 16);
+ tcg_debug_assert(type >= TCG_TYPE_V64);
+
+ /* We assume that INDEX_op_dupi could not be used and therefore
+ we must use a constant pool entry. */
+
+ switch (type) {
+ case TCG_TYPE_V64:
+ opc = OPC_MOVQ_VqWq;
+ break;
+ case TCG_TYPE_V128:
+ opc = OPC_MOVDQU_VxWx;
+ break;
+ case TCG_TYPE_V256:
+ opc = OPC_MOVDQU_VxWx | P_VEXL;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_out_vex_modrm_pool(s, opc, ret);
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ rel = R_386_PC32, ofs = -4;
+ } else {
+ rel = R_386_32, ofs = 0;
+ }
+ switch (n) {
+ case 1:
+ new_pool_label(s, a[0], rel, s->code_ptr - 4, rel);
+ break;
+ case 2:
+ new_pool_l2(s, rel, s->code_ptr - 4, ofs, a[0], a[1]);
+ break;
+ case 4:
+ new_pool_l4(s, rel, s->code_ptr - 4, ofs, a[0], a[1], a[2], a[3]);
+ break;
+#if TCG_TARGET_REG_BITS == 32
+ case 8:
+ new_pool_l8(s, rel, s->code_ptr - 4, ofs,
+ a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7]);
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+}
+
static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
{
if (val == (int8_t)val) {
@@ -702,18 +1048,74 @@ static inline void tcg_out_pop(TCGContext *s, int reg)
tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0);
}
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg arg1, intptr_t arg2)
{
- int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
- tcg_out_modrm_offset(s, opc, ret, arg1, arg2);
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (ret < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2);
+ } else {
+ tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2);
+ }
+ break;
+ case TCG_TYPE_I64:
+ if (ret < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2);
+ break;
+ }
+ /* FALLTHRU */
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx, ret, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL,
+ ret, 0, arg1, arg2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
{
- int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0);
- tcg_out_modrm_offset(s, opc, arg, arg1, arg2);
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (arg < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2);
+ } else {
+ tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2);
+ }
+ break;
+ case TCG_TYPE_I64:
+ if (arg < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2);
+ break;
+ }
+ /* FALLTHRU */
+ case TCG_TYPE_V64:
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx, arg, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V256:
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL,
+ arg, 0, arg1, arg2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
@@ -725,6 +1127,8 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
return false;
}
rexw = P_REXW;
+ } else if (type != TCG_TYPE_I32) {
+ return false;
}
tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs);
tcg_out32(s, val);
@@ -2259,8 +2663,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
+ case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
+ case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
@@ -2269,6 +2675,206 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
#undef OP_32_64
}
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ static int const add_insn[4] = {
+ OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ
+ };
+ static int const sub_insn[4] = {
+ OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
+ };
+ static int const mul_insn[4] = {
+ OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
+ };
+ static int const shift_imm_insn[4] = {
+ OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib
+ };
+ static int const cmpeq_insn[4] = {
+ OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ
+ };
+ static int const cmpgt_insn[4] = {
+ OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ
+ };
+ static int const punpckl_insn[4] = {
+ OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ
+ };
+ static int const punpckh_insn[4] = {
+ OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ
+ };
+ static int const packss_insn[4] = {
+ OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2
+ };
+ static int const packus_insn[4] = {
+ OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2
+ };
+ static int const pmovsx_insn[3] = {
+ OPC_PMOVSXBW, OPC_PMOVSXWD, OPC_PMOVSXDQ
+ };
+ static int const pmovzx_insn[3] = {
+ OPC_PMOVZXBW, OPC_PMOVZXWD, OPC_PMOVZXDQ
+ };
+
+ TCGType type = vecl + TCG_TYPE_V64;
+ int insn, sub;
+ TCGArg a0, a1, a2;
+
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+
+ switch (opc) {
+ case INDEX_op_add_vec:
+ insn = add_insn[vece];
+ goto gen_simd;
+ case INDEX_op_sub_vec:
+ insn = sub_insn[vece];
+ goto gen_simd;
+ case INDEX_op_mul_vec:
+ insn = mul_insn[vece];
+ goto gen_simd;
+ case INDEX_op_and_vec:
+ insn = OPC_PAND;
+ goto gen_simd;
+ case INDEX_op_or_vec:
+ insn = OPC_POR;
+ goto gen_simd;
+ case INDEX_op_xor_vec:
+ insn = OPC_PXOR;
+ goto gen_simd;
+ case INDEX_op_zipl_vec:
+ case INDEX_op_x86_punpckl_vec:
+ insn = punpckl_insn[vece];
+ goto gen_simd;
+ case INDEX_op_ziph_vec:
+ case INDEX_op_x86_punpckh_vec:
+ insn = punpckh_insn[vece];
+ goto gen_simd;
+ case INDEX_op_x86_packss_vec:
+ insn = packss_insn[vece];
+ goto gen_simd;
+ case INDEX_op_x86_packus_vec:
+ insn = packus_insn[vece];
+ goto gen_simd;
+ gen_simd:
+ tcg_debug_assert(insn != OPC_UD2);
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ break;
+
+ case INDEX_op_extsl_vec:
+ insn = pmovsx_insn[vece];
+ goto gen_simd2;
+ case INDEX_op_extul_vec:
+ insn = pmovzx_insn[vece];
+ goto gen_simd2;
+ gen_simd2:
+ tcg_debug_assert(vece < MO_64);
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, 0, a1);
+ break;
+
+ case INDEX_op_cmp_vec:
+ sub = args[3];
+ if (sub == TCG_COND_EQ) {
+ insn = cmpeq_insn[vece];
+ } else if (sub == TCG_COND_GT) {
+ insn = cmpgt_insn[vece];
+ } else {
+ g_assert_not_reached();
+ }
+ goto gen_simd;
+
+ case INDEX_op_andc_vec:
+ insn = OPC_PANDN;
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a2, a1);
+ break;
+
+ case INDEX_op_shli_vec:
+ sub = 6;
+ goto gen_shift;
+ case INDEX_op_shri_vec:
+ sub = 2;
+ goto gen_shift;
+ case INDEX_op_sari_vec:
+ tcg_debug_assert(vece != MO_64);
+ sub = 4;
+ gen_shift:
+ tcg_debug_assert(vece != MO_8);
+ insn = shift_imm_insn[vece];
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, sub, a0, a1);
+ tcg_out8(s, a2);
+ break;
+
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_movi_vec:
+ tcg_out_movi_vec(s, type, a0, args + 1);
+ break;
+ case INDEX_op_dup_vec:
+ tcg_out_dup_vec(s, type, vece, a0, a1);
+ break;
+
+ case INDEX_op_x86_shufps_vec:
+ insn = OPC_SHUFPS;
+ sub = args[3];
+ goto gen_simd_imm8;
+ case INDEX_op_x86_blend_vec:
+ if (vece == MO_16) {
+ insn = OPC_PBLENDW;
+ } else if (vece == MO_32) {
+ insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS);
+ } else {
+ g_assert_not_reached();
+ }
+ sub = args[3];
+ goto gen_simd_imm8;
+ case INDEX_op_x86_vperm2i128_vec:
+ insn = OPC_VPERM2I128;
+ sub = args[3];
+ goto gen_simd_imm8;
+ gen_simd_imm8:
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ tcg_out8(s, sub);
+ break;
+
+ case INDEX_op_x86_vpblendvb_vec:
+ insn = OPC_VPBLENDVB;
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ tcg_out8(s, args[3] << 4);
+ break;
+
+ case INDEX_op_x86_psrldq_vec:
+ tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1);
+ tcg_out8(s, a2);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
@@ -2292,6 +2898,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
= { .args_ct_str = { "r", "r", "L", "L" } };
static const TCGTargetOpDef L_L_L_L
= { .args_ct_str = { "L", "L", "L", "L" } };
+ static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
+ static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
+ static const TCGTargetOpDef x_x_x_x
+ = { .args_ct_str = { "x", "x", "x", "x" } };
+ static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
switch (op) {
case INDEX_op_goto_ptr:
@@ -2493,12 +3104,608 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
return &s2;
}
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ return &x_r;
+
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_zipl_vec:
+ case INDEX_op_ziph_vec:
+ case INDEX_op_x86_shufps_vec:
+ case INDEX_op_x86_blend_vec:
+ case INDEX_op_x86_packss_vec:
+ case INDEX_op_x86_packus_vec:
+ case INDEX_op_x86_vperm2i128_vec:
+ case INDEX_op_x86_punpckl_vec:
+ case INDEX_op_x86_punpckh_vec:
+ return &x_x_x;
+ case INDEX_op_dup_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_extsl_vec:
+ case INDEX_op_extul_vec:
+ case INDEX_op_x86_psrldq_vec:
+ return &x_x;
+ case INDEX_op_x86_vpblendvb_vec:
+ return &x_x_x_x;
+
default:
break;
}
return NULL;
}
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_extsl_vec:
+ case INDEX_op_extul_vec:
+ return 1;
+ case INDEX_op_cmp_vec:
+ case INDEX_op_extsh_vec:
+ case INDEX_op_extuh_vec:
+ case INDEX_op_trne_vec:
+ case INDEX_op_trno_vec:
+ return -1;
+
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ /* We must expand the operation for MO_8. */
+ return vece == MO_8 ? -1 : 1;
+
+ case INDEX_op_sari_vec:
+ /* We must expand the operation for MO_8. */
+ if (vece == MO_8) {
+ return -1;
+ }
+ /* We can emulate this for MO_64, but it does not pay off
+ unless we're producing at least 4 values. */
+ if (vece == MO_64) {
+ return type >= TCG_TYPE_V256 ? -1 : 0;
+ }
+ return 1;
+
+ case INDEX_op_mul_vec:
+ if (vece == MO_8) {
+ /* We can expand the operation for MO_8. */
+ return -1;
+ }
+ if (vece == MO_64) {
+ return 0;
+ }
+ return 1;
+
+ case INDEX_op_zipl_vec:
+ /* We could support v256, but with 3 insns per opcode.
+ It is better to expand with v128 instead. */
+ return type <= TCG_TYPE_V128;
+ case INDEX_op_ziph_vec:
+ if (type == TCG_TYPE_V64) {
+ return -1;
+ }
+ return type == TCG_TYPE_V128;
+
+ case INDEX_op_uzpe_vec:
+ case INDEX_op_uzpo_vec:
+ /* ??? Not implemented for V256. */
+ return -(type <= TCG_TYPE_V128);
+
+ default:
+ return 0;
+ }
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+ va_list va;
+ TCGArg a1, a2;
+ TCGv_vec v0, v1, v2, t1, t2, t3, t4;
+
+ va_start(va, a0);
+ v0 = temp_tcgv_vec(arg_temp(a0));
+
+ switch (opc) {
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ tcg_debug_assert(vece == MO_8);
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ /* Unpack to W, shift, and repack. Tricky bits:
+ (1) Use punpck*bw x,x to produce DDCCBBAA,
+ i.e. duplicate in other half of the 16-bit lane.
+ (2) For right-shift, add 8 so that the high half of
+ the lane becomes zero. For left-shift, we must
+ shift up and down again.
+ (3) Step 2 leaves high half zero such that PACKUSWB
+ (pack with unsigned saturation) does not modify
+ the quantity. */
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_zipl_vec, type, MO_8, tcgv_vec_arg(t1), a1, a1);
+ vec_gen_3(INDEX_op_ziph_vec, type, MO_8, tcgv_vec_arg(t2), a1, a1);
+ if (opc == INDEX_op_shri_vec) {
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
+ } else {
+ vec_gen_3(INDEX_op_shli_vec, type, MO_16,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_16,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), 8);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), 8);
+ }
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+
+ case INDEX_op_sari_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ if (vece == MO_8) {
+ /* Unpack to W, shift, and repack, as above. */
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_zipl_vec, type, MO_8, tcgv_vec_arg(t1), a1, a1);
+ vec_gen_3(INDEX_op_ziph_vec, type, MO_8, tcgv_vec_arg(t2), a1, a1);
+ vec_gen_3(INDEX_op_sari_vec, type, MO_16,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
+ vec_gen_3(INDEX_op_sari_vec, type, MO_16,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
+ vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ }
+ tcg_debug_assert(vece == MO_64);
+ /* MO_64: If the shift is <= 32, we can emulate the sign extend by
+ performing an arithmetic 32-bit shift and overwriting the high
+ half of the result (note that the ISA says shift of 32 is valid). */
+ if (a2 <= 32) {
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_sari_vec, type, MO_32, tcgv_vec_arg(t1), a1, a2);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_64, a0, a1, a2);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
+ a0, a0, tcgv_vec_arg(t1), 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ }
+ /* Otherwise we will need to use a compare vs 0 to produce the
+ sign-extend, shift and merge. */
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_const_zeros_vec(type);
+ vec_gen_4(INDEX_op_cmp_vec, type, MO_64,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t2), a1, TCG_COND_GT);
+ tcg_temp_free_vec(t2);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_64, a0, a1, a2);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_64,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), 64 - a2);
+ vec_gen_3(INDEX_op_or_vec, type, MO_64, a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+
+ case INDEX_op_mul_vec:
+ tcg_debug_assert(vece == MO_8);
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ switch (type) {
+ case TCG_TYPE_V64:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup16i_vec(t2, 0);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t1), a1, tcgv_vec_arg(t2));
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2);
+ tcg_gen_mul_vec(MO_16, t1, t1, t2);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+
+ case TCG_TYPE_V128:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t3 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t4 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup16i_vec(t4, 0);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t1), a1, tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t4), a2);
+ vec_gen_3(INDEX_op_ziph_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t3), a1, tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_ziph_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t4), tcgv_vec_arg(t4), a2);
+ tcg_gen_mul_vec(MO_16, t1, t1, t2);
+ tcg_gen_mul_vec(MO_16, t3, t3, t4);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ tcg_gen_shri_vec(MO_16, t3, t3, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t3));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t4);
+ break;
+
+ case TCG_TYPE_V256:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V256);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V256);
+ t3 = tcg_temp_new_vec(TCG_TYPE_V256);
+ t4 = tcg_temp_new_vec(TCG_TYPE_V256);
+ tcg_gen_dup16i_vec(t4, 0);
+ /* a1: A[0-7] ... D[0-7]; a2: W[0-7] ... Z[0-7]
+ t1: extends of B[0-7], D[0-7]
+ t2: extends of X[0-7], Z[0-7]
+ t3: extends of A[0-7], C[0-7]
+ t4: extends of W[0-7], Y[0-7]. */
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V256, MO_8,
+ tcgv_vec_arg(t1), a1, tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V256, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t4), a2);
+ vec_gen_3(INDEX_op_ziph_vec, TCG_TYPE_V256, MO_8,
+ tcgv_vec_arg(t3), a1, tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_ziph_vec, TCG_TYPE_V256, MO_8,
+ tcgv_vec_arg(t4), tcgv_vec_arg(t4), a2);
+ /* t1: BX DZ; t2: AW CY. */
+ tcg_gen_mul_vec(MO_16, t1, t1, t2);
+ tcg_gen_mul_vec(MO_16, t3, t3, t4);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ tcg_gen_shri_vec(MO_16, t3, t3, 8);
+ /* a0: AW BX CY DZ. */
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V256, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t3));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t4);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_ziph_vec:
+ tcg_debug_assert(type == TCG_TYPE_V64);
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, vece, a0, a1, a2);
+ vec_gen_3(INDEX_op_x86_psrldq_vec, TCG_TYPE_V128, MO_64, a0, a0, 8);
+ break;
+
+ case INDEX_op_extsh_vec:
+ case INDEX_op_extuh_vec:
+ a1 = va_arg(va, TCGArg);
+ switch (type) {
+ case TCG_TYPE_V64:
+ vec_gen_3(INDEX_op_x86_psrldq_vec, type, MO_64, a0, a1, 4);
+ break;
+ case TCG_TYPE_V128:
+ vec_gen_3(INDEX_op_x86_psrldq_vec, type, MO_64, a0, a1, 8);
+ break;
+ case TCG_TYPE_V256:
+ vec_gen_4(INDEX_op_x86_vperm2i128_vec, type, 4, a0, a1, a1, 0x81);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ vec_gen_2(opc == INDEX_op_extsh_vec ? INDEX_op_extsl_vec
+ : INDEX_op_extul_vec, type, vece, a0, a0);
+ break;
+
+ case INDEX_op_uzpe_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ v1 = temp_tcgv_vec(arg_temp(a1));
+ v2 = temp_tcgv_vec(arg_temp(a2));
+
+ if (type == TCG_TYPE_V128) {
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ tcg_gen_dup16i_vec(t2, 0x00ff);
+ tcg_gen_and_vec(MO_16, t1, v2, t2);
+ tcg_gen_and_vec(MO_16, v0, v1, t2);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ tcg_gen_dup32i_vec(t2, 0x0000ffff);
+ tcg_gen_and_vec(MO_32, t1, v2, t2);
+ tcg_gen_and_vec(MO_32, v0, v1, t2);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_16,
+ a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_32:
+ vec_gen_4(INDEX_op_x86_shufps_vec, type, MO_32,
+ a0, a1, a2, 0x88);
+ break;
+ case MO_64:
+ tcg_gen_zipl_vec(vece, v0, v1, v2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ tcg_debug_assert(type == TCG_TYPE_V64);
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_64,
+ tcgv_vec_arg(t1), a1, a2);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup16i_vec(t2, 0x00ff);
+ tcg_gen_and_vec(MO_16, t1, t1, t2);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_64,
+ tcgv_vec_arg(t1), a1, a2);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup32i_vec(t2, 0x0000ffff);
+ tcg_gen_and_vec(MO_32, t1, t1, t2);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_16,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_32:
+ tcg_gen_zipl_vec(vece, v0, v1, v2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ break;
+
+ case INDEX_op_uzpo_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ v1 = temp_tcgv_vec(arg_temp(a1));
+ v2 = temp_tcgv_vec(arg_temp(a2));
+
+ if (type == TCG_TYPE_V128) {
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_shri_vec(MO_16, t1, v2, 8);
+ tcg_gen_shri_vec(MO_16, v0, v1, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_shri_vec(MO_32, t1, v2, 16);
+ tcg_gen_shri_vec(MO_32, v0, v1, 16);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_16,
+ a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_32:
+ vec_gen_4(INDEX_op_x86_shufps_vec, type, MO_32,
+ a0, a1, a2, 0xdd);
+ break;
+ case MO_64:
+ tcg_gen_ziph_vec(vece, v0, v1, v2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_64,
+ tcgv_vec_arg(t1), a1, a2);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_64,
+ tcgv_vec_arg(t1), a1, a2);
+ tcg_gen_shri_vec(MO_32, t1, t1, 16);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_16,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_32:
+ tcg_gen_ziph_vec(vece, v0, v1, v2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ break;
+
+ case INDEX_op_trne_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_16,
+ tcgv_vec_arg(t1), a2, 8);
+ tcg_gen_dup16i_vec(t2, 0xff00);
+ vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, MO_8,
+ a0, a1, tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_32,
+ tcgv_vec_arg(t1), a2, 16);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_16,
+ a0, a1, tcgv_vec_arg(t1), 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_32:
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_64,
+ tcgv_vec_arg(t1), a2, 32);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
+ a0, a1, tcgv_vec_arg(t1), 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_64:
+ vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_64, a0, a1, a2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_trno_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t1), a1, 8);
+ tcg_gen_dup16i_vec(t2, 0xff00);
+ vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, MO_8,
+ a0, tcgv_vec_arg(t1), a2, tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_32,
+ tcgv_vec_arg(t1), a1, 16);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_16,
+ a0, tcgv_vec_arg(t1), a2, 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_32:
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_64,
+ tcgv_vec_arg(t1), a1, 32);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
+ a0, tcgv_vec_arg(t1), a2, 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_64:
+ vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_64, a0, a1, a2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_cmp_vec:
+ {
+ enum {
+ NEED_SWAP = 1,
+ NEED_INV = 2,
+ NEED_BIAS = 4
+ };
+ static const uint8_t fixups[16] = {
+ [0 ... 15] = -1,
+ [TCG_COND_EQ] = 0,
+ [TCG_COND_NE] = NEED_INV,
+ [TCG_COND_GT] = 0,
+ [TCG_COND_LT] = NEED_SWAP,
+ [TCG_COND_LE] = NEED_INV,
+ [TCG_COND_GE] = NEED_SWAP | NEED_INV,
+ [TCG_COND_GTU] = NEED_BIAS,
+ [TCG_COND_LTU] = NEED_BIAS | NEED_SWAP,
+ [TCG_COND_LEU] = NEED_BIAS | NEED_INV,
+ [TCG_COND_GEU] = NEED_BIAS | NEED_SWAP | NEED_INV,
+ };
+
+ TCGCond cond;
+ uint8_t fixup;
+
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ cond = va_arg(va, TCGArg);
+ fixup = fixups[cond & 15];
+ tcg_debug_assert(fixup != 0xff);
+
+ if (fixup & NEED_INV) {
+ cond = tcg_invert_cond(cond);
+ }
+ if (fixup & NEED_SWAP) {
+ TCGArg t;
+ t = a1, a1 = a2, a2 = t;
+ cond = tcg_swap_cond(cond);
+ }
+
+ t1 = t2 = NULL;
+ if (fixup & NEED_BIAS) {
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));
+ tcg_gen_sub_vec(vece, t1, temp_tcgv_vec(arg_temp(a1)), t2);
+ tcg_gen_sub_vec(vece, t2, temp_tcgv_vec(arg_temp(a2)), t2);
+ a1 = tcgv_vec_arg(t1);
+ a2 = tcgv_vec_arg(t2);
+ cond = tcg_signed_cond(cond);
+ }
+
+ tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT);
+ vec_gen_4(INDEX_op_cmp_vec, type, vece, a0, a1, a2, cond);
+
+ if (fixup & NEED_BIAS) {
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ }
+ if (fixup & NEED_INV) {
+ tcg_gen_not_vec(vece, v0, v0);
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ va_end(va);
+}
+
static const int tcg_target_callee_save_regs[] = {
#if TCG_TARGET_REG_BITS == 64
TCG_REG_RBP,
@@ -2577,6 +3784,9 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend);
+ if (have_avx2) {
+ tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0);
+ }
for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
tcg_out_pop(s, tcg_target_callee_save_regs[i]);
}
@@ -2598,9 +3808,16 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
static void tcg_target_init(TCGContext *s)
{
#ifdef CONFIG_CPUID_H
- unsigned a, b, c, d;
+ unsigned a, b, c, d, b7 = 0;
int max = __get_cpuid_max(0, 0);
+ if (max >= 7) {
+ /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
+ __cpuid_count(7, 0, a, b7, c, d);
+ have_bmi1 = (b7 & bit_BMI) != 0;
+ have_bmi2 = (b7 & bit_BMI2) != 0;
+ }
+
if (max >= 1) {
__cpuid(1, a, b, c, d);
#ifndef have_cmov
@@ -2609,17 +3826,22 @@ static void tcg_target_init(TCGContext *s)
available, we'll use a small forward branch. */
have_cmov = (d & bit_CMOV) != 0;
#endif
+
/* MOVBE is only available on Intel Atom and Haswell CPUs, so we
need to probe for it. */
have_movbe = (c & bit_MOVBE) != 0;
have_popcnt = (c & bit_POPCNT) != 0;
- }
- if (max >= 7) {
- /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
- __cpuid_count(7, 0, a, b, c, d);
- have_bmi1 = (b & bit_BMI) != 0;
- have_bmi2 = (b & bit_BMI2) != 0;
+ /* There are a number of things we must check before we can be
+ sure of not hitting invalid opcode. */
+ if (c & bit_OSXSAVE) {
+ unsigned xcrl, xcrh;
+ asm ("xgetbv" : "=a" (xcrl), "=d" (xcrh) : "c" (0));
+ if ((xcrl & 6) == 6) {
+ have_avx1 = (c & bit_AVX) != 0;
+ have_avx2 = (b7 & bit_AVX2) != 0;
+ }
+ }
}
max = __get_cpuid_max(0x8000000, 0);
@@ -2630,11 +3852,16 @@ static void tcg_target_init(TCGContext *s)
}
#endif /* CONFIG_CPUID_H */
+ tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
if (TCG_TARGET_REG_BITS == 64) {
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
- } else {
- tcg_target_available_regs[TCG_TYPE_I32] = 0xff;
+ tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
+ }
+ if (have_avx1) {
+ tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
+ tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
+ }
+ if (have_avx2) {
+ tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
}
tcg_target_call_clobber_regs = 0;
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [Qemu-devel] [PATCH v9 26/26] tcg/aarch64: Add vector operations
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (24 preceding siblings ...)
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 25/26] tcg/i386: Add vector operations Richard Henderson
@ 2018-01-16 3:34 ` Richard Henderson
2018-01-16 4:02 ` [Qemu-devel] [PATCH v9 00/26] tcg: generic " no-reply
` (2 subsequent siblings)
28 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 3:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 30 +-
tcg/aarch64/tcg-target.opc.h | 3 +
tcg/aarch64/tcg-target.inc.c | 674 ++++++++++++++++++++++++++++++++++++++++---
3 files changed, 660 insertions(+), 47 deletions(-)
create mode 100644 tcg/aarch64/tcg-target.opc.h
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index c2525066ab..46434ecca4 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -31,13 +31,22 @@ typedef enum {
TCG_REG_SP = 31,
TCG_REG_XZR = 31,
+ TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+ TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
+ TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
+
/* Aliases. */
TCG_REG_FP = TCG_REG_X29,
TCG_REG_LR = TCG_REG_X30,
TCG_AREG0 = TCG_REG_X19,
} TCGReg;
-#define TCG_TARGET_NB_REGS 32
+#define TCG_TARGET_NB_REGS 64
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_SP
@@ -113,6 +122,25 @@ typedef enum {
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_direct_jump 1
+#define TCG_TARGET_HAS_v64 1
+#define TCG_TARGET_HAS_v128 1
+#define TCG_TARGET_HAS_v256 0
+
+#define TCG_TARGET_HAS_andc_vec 1
+#define TCG_TARGET_HAS_orc_vec 1
+#define TCG_TARGET_HAS_not_vec 1
+#define TCG_TARGET_HAS_neg_vec 1
+#define TCG_TARGET_HAS_shi_vec 1
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_zip_vec 1
+#define TCG_TARGET_HAS_uzp_vec 1
+#define TCG_TARGET_HAS_trn_vec 1
+#define TCG_TARGET_HAS_cmp_vec 1
+#define TCG_TARGET_HAS_mul_vec 1
+#define TCG_TARGET_HAS_extl_vec 1
+#define TCG_TARGET_HAS_exth_vec 1
+
#define TCG_TARGET_DEFAULT_MO (0)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h
new file mode 100644
index 0000000000..4816a6c3d4
--- /dev/null
+++ b/tcg/aarch64/tcg-target.opc.h
@@ -0,0 +1,3 @@
+/* Target-specific opcodes for host vector expansion. These will be
+ emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ consider these to be UNSPEC with names. */
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 150530f30e..b2ce818d7c 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -20,10 +20,15 @@ QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
#ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%x0", "%x1", "%x2", "%x3", "%x4", "%x5", "%x6", "%x7",
- "%x8", "%x9", "%x10", "%x11", "%x12", "%x13", "%x14", "%x15",
- "%x16", "%x17", "%x18", "%x19", "%x20", "%x21", "%x22", "%x23",
- "%x24", "%x25", "%x26", "%x27", "%x28", "%fp", "%x30", "%sp",
+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
+ "x24", "x25", "x26", "x27", "x28", "fp", "x30", "sp",
+
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "fp", "v30", "v31",
};
#endif /* CONFIG_DEBUG_TCG */
@@ -43,6 +48,14 @@ static const int tcg_target_reg_alloc_order[] = {
/* X19 reserved for AREG0 */
/* X29 reserved as fp */
/* X30 reserved as temporary */
+
+ TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+ /* V8 - V15 are call-saved, and skipped. */
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
};
static const int tcg_target_call_iarg_regs[8] = {
@@ -54,6 +67,7 @@ static const int tcg_target_call_oarg_regs[1] = {
};
#define TCG_REG_TMP TCG_REG_X30
+#define TCG_VEC_TMP TCG_REG_V31
#ifndef CONFIG_SOFTMMU
/* Note that XZR cannot be encoded in the address base register slot,
@@ -119,9 +133,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type)
{
switch (*ct_str++) {
- case 'r':
+ case 'r': /* general registers */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffffu;
+ ct->u.regs |= 0xffffffffu;
+ break;
+ case 'w': /* advsimd registers */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs |= 0xffffffff00000000ull;
break;
case 'l': /* qemu_ld / qemu_st address, data_reg */
ct->ct |= TCG_CT_REG;
@@ -178,6 +196,98 @@ static inline bool is_limm(uint64_t val)
return (val & (val - 1)) == 0;
}
+static bool is_fimm(uint64_t v64, int *op, int *cmode, int *imm8)
+{
+ int i;
+
+ *op = 0;
+ if (v64 == (-1ull / 0xff) * (v64 & 0xff)) {
+ *cmode = 0xe;
+ *imm8 = v64 & 0xff;
+ return true;
+ }
+ if (v64 == (-1ull / 0xffff) * (v64 & 0xffff)) {
+ uint64_t v16 = v64 & 0xffff;
+
+ if (v16 == (v64 & 0xff)) {
+ *cmode = 0x8;
+ *imm8 = v64 & 0xff;
+ return true;
+ } else if (v16 == (v64 & 0xff00)) {
+ *cmode = 0xa;
+ *imm8 = v16 >> 8;
+ return true;
+ }
+ }
+ if (v64 == deposit64(v64, 32, 32, v64)) {
+ uint64_t v32 = (uint32_t)v64;
+
+ if (v32 == (v64 & 0xff)) {
+ *cmode = 0x0;
+ *imm8 = v64 & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff00)) {
+ *cmode = 0x2;
+ *imm8 = (v64 >> 8) & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff0000)) {
+ *cmode = 0x4;
+ *imm8 = (v64 >> 16) & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff000000)) {
+ *cmode = 0x6;
+ *imm8 = v32 >> 24;
+ return true;
+ } else if ((v32 & 0xffff00ff) == 0xff) {
+ *cmode = 0xc;
+ *imm8 = (v64 >> 8) & 0xff;
+ return true;
+ } else if ((v32 & 0xff00ffff) == 0xffff) {
+ *cmode = 0xd;
+ *imm8 = (v64 >> 16) & 0xff;
+ return true;
+ } else if (extract32(v32, 0, 19) == 0
+ && (extract32(v32, 25, 6) == 0x20
+ || extract32(v32, 25, 6) == 0x1f)) {
+ *cmode = 0xf;
+ *imm8 = (extract32(v32, 31, 1) << 7)
+ | (extract32(v32, 25, 1) << 6)
+ | extract32(v32, 19, 6);
+ return true;
+ }
+ }
+ if (extract64(v64, 0, 48) == 0
+ && (extract64(v64, 54, 9) == 0x100
+ || extract64(v64, 54, 9) == 0x0ff)) {
+ *cmode = 0xf;
+ *op = 1;
+ *imm8 = (extract64(v64, 63, 1) << 7)
+ | (extract64(v64, 54, 1) << 6)
+ | extract64(v64, 48, 6);
+ return true;
+ }
+ for (i = 0; i < 64; i += 8) {
+ uint64_t byte = extract64(v64, i, 8);
+ if (byte != 0 && byte != 0xff) {
+ break;
+ }
+ }
+ if (i == 64) {
+ *cmode = 0xe;
+ *op = 1;
+ *imm8 = (extract64(v64, 0, 1) << 0)
+ | (extract64(v64, 8, 1) << 1)
+ | (extract64(v64, 16, 1) << 2)
+ | (extract64(v64, 24, 1) << 3)
+ | (extract64(v64, 32, 1) << 4)
+ | (extract64(v64, 40, 1) << 5)
+ | (extract64(v64, 48, 1) << 6)
+ | (extract64(v64, 56, 1) << 7);
+ return true;
+ }
+ return false;
+}
+
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
{
@@ -271,6 +381,9 @@ typedef enum {
/* Load literal for loading the address at pc-relative offset */
I3305_LDR = 0x58000000,
+ I3305_LDR_v64 = 0x5c000000,
+ I3305_LDR_v128 = 0x9c000000,
+
/* Load/store register. Described here as 3.3.12, but the helper
that emits them can transform to 3.3.10 or 3.3.13. */
I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
@@ -290,6 +403,15 @@ typedef enum {
I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,
I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,
+ I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,
+ I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,
+
+ I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,
+ I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,
+
+ I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,
+ I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,
+
I3312_TO_I3310 = 0x00200800,
I3312_TO_I3313 = 0x01000000,
@@ -374,8 +496,58 @@ typedef enum {
I3510_EON = 0x4a200000,
I3510_ANDS = 0x6a000000,
- NOP = 0xd503201f,
+ /* AdvSIMD zip.uzp/trn */
+ I3603_ZIP1 = 0x0e003800,
+ I3603_UZP1 = 0x0e001800,
+ I3603_TRN1 = 0x0e002800,
+ I3603_ZIP2 = 0x0e007800,
+ I3603_UZP2 = 0x0e005800,
+ I3603_TRN2 = 0x0e006800,
+
+ /* AdvSIMD copy */
+ I3605_DUP = 0x0e000400,
+ I3605_INS = 0x4e001c00,
+ I3605_UMOV = 0x0e003c00,
+
+ /* AdvSIMD modified immediate */
+ I3606_MOVI = 0x0f000400,
+
+ /* AdvSIMD shift by immediate */
+ I3614_SSHR = 0x0f000400,
+ I3614_SSRA = 0x0f001400,
+ I3614_SHL = 0x0f005400,
+ I3614_SSHLL = 0x0f00a400,
+ I3614_USHR = 0x2f000400,
+ I3614_USRA = 0x2f001400,
+ I3614_USHLL = 0x2f00a400,
+
+ /* AdvSIMD three same. */
+ I3616_ADD = 0x0e208400,
+ I3616_AND = 0x0e201c00,
+ I3616_BIC = 0x0e601c00,
+ I3616_EOR = 0x2e201c00,
+ I3616_MUL = 0x0e209c00,
+ I3616_ORR = 0x0ea01c00,
+ I3616_ORN = 0x0ee01c00,
+ I3616_SUB = 0x2e208400,
+ I3616_CMGT = 0x0e203400,
+ I3616_CMGE = 0x0e203c00,
+ I3616_CMTST = 0x0e208c00,
+ I3616_CMHI = 0x2e203400,
+ I3616_CMHS = 0x2e203c00,
+ I3616_CMEQ = 0x2e208c00,
+
+ /* AdvSIMD two-reg misc. */
+ I3617_CMGT0 = 0x0e208800,
+ I3617_CMEQ0 = 0x0e209800,
+ I3617_CMLT0 = 0x0e20a800,
+ I3617_CMGE0 = 0x2e208800,
+ I3617_CMLE0 = 0x2e20a800,
+ I3617_NOT = 0x2e205800,
+ I3617_NEG = 0x2e20b800,
+
/* System instructions. */
+ NOP = 0xd503201f,
DMB_ISH = 0xd50338bf,
DMB_LD = 0x00000100,
DMB_ST = 0x00000200,
@@ -520,26 +692,71 @@ static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);
}
+static void tcg_out_insn_3603(TCGContext *s, AArch64Insn insn, bool q,
+ unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
+{
+ tcg_out32(s, insn | q << 30 | (size << 22) | (rd & 0x1f)
+ | (rn & 0x1f) << 5 | (rm & 0x1f) << 16);
+}
+
+static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, TCGReg rn, int dst_idx, int src_idx)
+{
+ /* Note that bit 11 set means general register input. Therefore
+ we can handle both register sets with one function. */
+ tcg_out32(s, insn | q << 30 | (dst_idx << 16) | (src_idx << 11)
+ | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5);
+}
+
+static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, bool op, int cmode, uint8_t imm8)
+{
+ tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f)
+ | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);
+}
+
+static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, TCGReg rn, unsigned immhb)
+{
+ tcg_out32(s, insn | q << 30 | immhb << 16
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q,
+ unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
+{
+ tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,
+ unsigned size, TCGReg rd, TCGReg rn)
+{
+ tcg_out32(s, insn | q << 30 | (size << 22)
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
TCGReg rd, TCGReg base, TCGType ext,
TCGReg regoff)
{
/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
- 0x4000 | ext << 13 | base << 5 | rd);
+ 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
}
static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
TCGReg rd, TCGReg rn, intptr_t offset)
{
- tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | rd);
+ tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));
}
static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,
TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)
{
/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
- tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10 | rn << 5 | rd);
+ tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10
+ | rn << 5 | (rd & 0x1f));
}
/* Register to register move using ORR (shifted register with no shift). */
@@ -585,6 +802,35 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
}
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+ TCGReg rd, uint64_t v64)
+{
+ int op, cmode, imm8;
+
+ if (is_fimm(v64, &op, &cmode, &imm8)) {
+ tcg_out_insn(s, 3606, MOVI, type == TCG_TYPE_V128, rd, op, cmode, imm8);
+ } else if (type == TCG_TYPE_V128) {
+ new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);
+ tcg_out_insn(s, 3305, LDR_v128, 0, rd);
+ } else {
+ new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0);
+ tcg_out_insn(s, 3305, LDR_v64, 0, rd);
+ }
+}
+
+static void tcg_out_movi_vec(TCGContext *s, TCGType type,
+ TCGReg ret, const TCGArg *a)
+{
+ if (type == TCG_TYPE_V128) {
+ /* We assume that INDEX_op_dupi could not be used and
+ therefore we must use a constant pool entry. */
+ new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, a[0], a[1]);
+ tcg_out_insn(s, 3305, LDR_v128, 0, ret);
+ } else {
+ tcg_out_dupi_vec(s, TCG_TYPE_V64, ret, a[0]);
+ }
+}
+
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_target_long value)
{
@@ -594,6 +840,22 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
int s0, s1;
AArch64Insn opc;
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ tcg_debug_assert(rd < 32);
+ break;
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_debug_assert(rd >= 32);
+ tcg_out_dupi_vec(s, type, rd, value);
+ return;
+
+ default:
+ g_assert_not_reached();
+ }
+
/* For 32-bit values, discard potential garbage in value. For 64-bit
values within [2**31, 2**32-1], we can create smaller sequences by
interpreting this as a negative 32-bit number, while ensuring that
@@ -669,15 +931,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
/* Define something more legible for general use. */
#define tcg_out_ldst_r tcg_out_insn_3310
-static void tcg_out_ldst(TCGContext *s, AArch64Insn insn,
- TCGReg rd, TCGReg rn, intptr_t offset)
+static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
+ TCGReg rn, intptr_t offset, int lgsize)
{
- TCGMemOp size = (uint32_t)insn >> 30;
-
/* If the offset is naturally aligned and in range, then we can
use the scaled uimm12 encoding */
- if (offset >= 0 && !(offset & ((1 << size) - 1))) {
- uintptr_t scaled_uimm = offset >> size;
+ if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) {
+ uintptr_t scaled_uimm = offset >> lgsize;
if (scaled_uimm <= 0xfff) {
tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm);
return;
@@ -695,32 +955,102 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn,
tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
}
-static inline void tcg_out_mov(TCGContext *s,
- TCGType type, TCGReg ret, TCGReg arg)
+static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- if (ret != arg) {
- tcg_out_movr(s, type, ret, arg);
+ if (ret == arg) {
+ return;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ if (ret < 32 && arg < 32) {
+ tcg_out_movr(s, type, ret, arg);
+ break;
+ } else if (ret < 32) {
+ tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0);
+ break;
+ } else if (arg < 32) {
+ tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0);
+ break;
+ }
+ /* FALLTHRU */
+
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 32 && arg >= 32);
+ tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 32 && arg >= 32);
+ tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg);
+ break;
+
+ default:
+ g_assert_not_reached();
}
}
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg base, intptr_t ofs)
{
- tcg_out_ldst(s, type == TCG_TYPE_I32 ? I3312_LDRW : I3312_LDRX,
- arg, arg1, arg2);
+ AArch64Insn insn;
+ int lgsz;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS);
+ lgsz = 2;
+ break;
+ case TCG_TYPE_I64:
+ insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD);
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V64:
+ insn = I3312_LDRVD;
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V128:
+ insn = I3312_LDRVQ;
+ lgsz = 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_out_ldst(s, insn, ret, base, ofs, lgsz);
}
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src,
+ TCGReg base, intptr_t ofs)
{
- tcg_out_ldst(s, type == TCG_TYPE_I32 ? I3312_STRW : I3312_STRX,
- arg, arg1, arg2);
+ AArch64Insn insn;
+ int lgsz;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ insn = (src < 32 ? I3312_STRW : I3312_STRVS);
+ lgsz = 2;
+ break;
+ case TCG_TYPE_I64:
+ insn = (src < 32 ? I3312_STRX : I3312_STRVD);
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V64:
+ insn = I3312_STRVD;
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V128:
+ insn = I3312_STRVQ;
+ lgsz = 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_out_ldst(s, insn, src, base, ofs, lgsz);
}
static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
TCGReg base, intptr_t ofs)
{
- if (val == 0) {
+ if (type <= TCG_TYPE_I64 && val == 0) {
tcg_out_st(s, type, TCG_REG_XZR, base, ofs);
return true;
}
@@ -1210,14 +1540,15 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
/* Merge "low bits" from tlb offset, load the tlb comparator into X0.
X0 = load [X2 + (tlb_offset & 0x000fff)] */
tcg_out_ldst(s, TARGET_LONG_BITS == 32 ? I3312_LDRW : I3312_LDRX,
- TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff);
+ TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff,
+ TARGET_LONG_BITS == 32 ? 2 : 3);
/* Load the tlb addend. Do that early to avoid stalling.
X1 = load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */
tcg_out_ldst(s, I3312_LDRX, TCG_REG_X1, TCG_REG_X2,
(tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) -
(is_read ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write)));
+ : offsetof(CPUTLBEntry, addr_write)), 3);
/* Perform the address comparison. */
tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);
@@ -1435,49 +1766,49 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
- tcg_out_ldst(s, I3312_LDRB, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0);
break;
case INDEX_op_ld8s_i32:
- tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0);
break;
case INDEX_op_ld8s_i64:
- tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0);
break;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
- tcg_out_ldst(s, I3312_LDRH, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1);
break;
case INDEX_op_ld16s_i32:
- tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1);
break;
case INDEX_op_ld16s_i64:
- tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1);
break;
case INDEX_op_ld_i32:
case INDEX_op_ld32u_i64:
- tcg_out_ldst(s, I3312_LDRW, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2);
break;
case INDEX_op_ld32s_i64:
- tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2);
break;
case INDEX_op_ld_i64:
- tcg_out_ldst(s, I3312_LDRX, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3);
break;
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
- tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2);
+ tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);
break;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
- tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2);
+ tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);
break;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
- tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2);
+ tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);
break;
case INDEX_op_st_i64:
- tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2);
+ tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);
break;
case INDEX_op_add_i32:
@@ -1776,25 +2107,230 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
+ case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
+ case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
- tcg_abort();
+ g_assert_not_reached();
}
#undef REG0
}
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ static const AArch64Insn cmp_insn[16] = {
+ [TCG_COND_EQ] = I3616_CMEQ,
+ [TCG_COND_GT] = I3616_CMGT,
+ [TCG_COND_GE] = I3616_CMGE,
+ [TCG_COND_GTU] = I3616_CMHI,
+ [TCG_COND_GEU] = I3616_CMHS,
+ };
+ static const AArch64Insn cmp0_insn[16] = {
+ [TCG_COND_EQ] = I3617_CMEQ0,
+ [TCG_COND_GT] = I3617_CMGT0,
+ [TCG_COND_GE] = I3617_CMGE0,
+ [TCG_COND_LT] = I3617_CMLT0,
+ [TCG_COND_LE] = I3617_CMLE0,
+ };
+
+ TCGType type = vecl + TCG_TYPE_V64;
+ unsigned is_q = vecl;
+ TCGArg a0, a1, a2;
+
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+
+ switch (opc) {
+ case INDEX_op_movi_vec:
+ tcg_out_movi_vec(s, type, a0, args + 1);
+ break;
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_add_vec:
+ tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_sub_vec:
+ tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_mul_vec:
+ tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_neg_vec:
+ tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
+ break;
+ case INDEX_op_and_vec:
+ tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_or_vec:
+ tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_xor_vec:
+ tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_andc_vec:
+ tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_orc_vec:
+ tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_not_vec:
+ tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
+ break;
+ case INDEX_op_dup_vec:
+ tcg_out_insn(s, 3605, DUP, is_q, a0, a1, 1 << vece, 0);
+ break;
+ case INDEX_op_shli_vec:
+ tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
+ break;
+ case INDEX_op_shri_vec:
+ tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
+ break;
+ case INDEX_op_sari_vec:
+ tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
+ break;
+ case INDEX_op_cmp_vec:
+ {
+ TCGCond cond = args[3];
+ AArch64Insn insn;
+
+ if (cond == TCG_COND_NE) {
+ if (const_args[2]) {
+ tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
+ } else {
+ tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
+ tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
+ }
+ } else {
+ if (const_args[2]) {
+ insn = cmp0_insn[cond];
+ if (insn) {
+ tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
+ break;
+ }
+ tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0);
+ a2 = TCG_VEC_TMP;
+ }
+ insn = cmp_insn[cond];
+ if (insn == 0) {
+ TCGArg t;
+ t = a1, a1 = a2, a2 = t;
+ cond = tcg_swap_cond(cond);
+ insn = cmp_insn[cond];
+ tcg_debug_assert(insn != 0);
+ }
+ tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
+ }
+ }
+ break;
+ case INDEX_op_zipl_vec:
+ tcg_out_insn(s, 3603, ZIP1, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_ziph_vec:
+ tcg_out_insn(s, 3603, ZIP2, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_uzpe_vec:
+ tcg_out_insn(s, 3603, UZP1, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_uzpo_vec:
+ tcg_out_insn(s, 3603, UZP2, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_trne_vec:
+ tcg_out_insn(s, 3603, TRN1, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_trno_vec:
+ tcg_out_insn(s, 3603, TRN2, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_extul_vec:
+ tcg_out_insn(s, 3614, USHLL, 0, a0, a1, 0 + (8 << vece));
+ break;
+ case INDEX_op_extuh_vec:
+ if (is_q) {
+ tcg_out_insn(s, 3614, USHLL, 1, a0, a1, 0 + (8 << vece));
+ } else {
+ tcg_out_insn(s, 3614, USHLL, 0, a0, a1, 0 + (8 << vece));
+ tcg_out_insn(s, 3605, INS, 0, a0, a0, 8, 16);
+ }
+ break;
+ case INDEX_op_extsl_vec:
+ tcg_out_insn(s, 3614, SSHLL, 0, a0, a1, 0 + (8 << vece));
+ break;
+ case INDEX_op_extsh_vec:
+ if (is_q) {
+ tcg_out_insn(s, 3614, SSHLL, 1, a0, a1, 0 + (8 << vece));
+ } else {
+ tcg_out_insn(s, 3614, SSHLL, 0, a0, a1, 0 + (8 << vece));
+ tcg_out_insn(s, 3605, INS, 0, a0, a0, 8, 16);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_not_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_zipl_vec:
+ case INDEX_op_ziph_vec:
+ case INDEX_op_uzpe_vec:
+ case INDEX_op_uzpo_vec:
+ case INDEX_op_trne_vec:
+ case INDEX_op_trno_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_extul_vec:
+ case INDEX_op_extuh_vec:
+ case INDEX_op_extsl_vec:
+ case INDEX_op_extsh_vec:
+ return 1;
+
+ default:
+ return 0;
+ }
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+}
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef w = { .args_ct_str = { "w" } };
static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
+ static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
+ static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
+ static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
+ static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
@@ -1938,6 +2474,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sub2_i64:
return &add2;
+ case INDEX_op_movi_vec:
+ return &w;
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_zipl_vec:
+ case INDEX_op_ziph_vec:
+ case INDEX_op_uzpe_vec:
+ case INDEX_op_uzpo_vec:
+ case INDEX_op_trne_vec:
+ case INDEX_op_trno_vec:
+ return &w_w_w;
+ case INDEX_op_not_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_extul_vec:
+ case INDEX_op_extuh_vec:
+ case INDEX_op_extsl_vec:
+ case INDEX_op_extsh_vec:
+ return &w_w;
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ return &w_r;
+ case INDEX_op_dup_vec:
+ return &w_wr;
+ case INDEX_op_cmp_vec:
+ return &w_w_wZ;
+
default:
return NULL;
}
@@ -1947,8 +2518,10 @@ static void tcg_target_init(TCGContext *s)
{
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
- tcg_target_call_clobber_regs = 0xfffffffu;
+ tcg_target_call_clobber_regs = -1ull;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21);
@@ -1960,12 +2533,21 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
}
/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */
--
2.14.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (25 preceding siblings ...)
2018-01-16 3:34 ` [Qemu-devel] [PATCH v9 26/26] tcg/aarch64: " Richard Henderson
@ 2018-01-16 4:02 ` no-reply
2018-01-16 4:27 ` no-reply
2018-01-16 11:59 ` Peter Maydell
28 siblings, 0 replies; 32+ messages in thread
From: no-reply @ 2018-01-16 4:02 UTC (permalink / raw)
To: richard.henderson; +Cc: famz, qemu-devel, peter.maydell
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180116033404.31532-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20180106153730.30313-1-hpoussin@reactos.org -> patchew/20180106153730.30313-1-hpoussin@reactos.org
* [new tag] patchew/20180116033404.31532-1-richard.henderson@linaro.org -> patchew/20180116033404.31532-1-richard.henderson@linaro.org
Switched to a new branch 'test'
318acc661a tcg/aarch64: Add vector operations
43511156d7 tcg/i386: Add vector operations
c29ad91d5c target/arm: Use vector infrastructure for aa64 orr/bic immediate
083b52d1fc target/arm: Use vector infrastructure for aa64 widening shifts
d6371398a3 target/arm: Use vector infrastructure for aa64 multiplies
25df8a60db target/arm: Use vector infrastructure for aa64 compares
57c1ab2b50 target/arm: Use vector infrastructure for aa64 constant shifts
8bfefd6b52 target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
ad7234c694 target/arm: Use vector infrastructure for aa64 dup/movi
6f14f6cfe8 target/arm: Use vector infrastructure for aa64 mov/not/neg
d97b762c05 target/arm: Use vector infrastructure for aa64 add/sub/logic
1ddbc6628e target/arm: Align vector registers
d7a8026fd9 tcg/optimize: Handle vector opcodes during optimize
fbeeb215e8 tcg: Add generic vector helpers with a scalar variable operand
5155c310c9 tcg: Add generic vector helpers with a scalar immediate operand
e13611c9d9 tcg: Loosen vec_gen_op* typecheck rules
03086dbc06 tcg: Add generic helpers for saturating arithmetic
ef1031a706 tcg: Add generic vector ops for extension
1629aea426 tcg: Add generic vector ops for multiplication
9788bdeec6 tcg: Add generic vector ops for comparisons
58c28e1fce tcg: Add generic vector ops for constant shifts
cc69b266cc tcg: Add generic vector ops for interleave
7c955c796b tcg: Add generic vector expanders
62b38cf8bf tcg: Standardize integral arguments to expanders
fbdd0d55ff tcg: Add types and basic operations for host vectors
3d46adc466 tcg: Allow multiple word entries into the constant pool
=== OUTPUT BEGIN ===
Checking PATCH 1/26: tcg: Allow multiple word entries into the constant pool...
ERROR: spaces prohibited around that ':' (ctx:WxW)
#23: FILE: tcg/tcg-pool.inc.c:26:
+ int addend : 32;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#24: FILE: tcg/tcg-pool.inc.c:27:
+ int rtype : 16;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#25: FILE: tcg/tcg-pool.inc.c:28:
+ int nlong : 16;
^
total: 3 errors, 0 warnings, 156 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 2/26: tcg: Add types and basic operations for host vectors...
ERROR: externs should be avoided in .c files
#137: FILE: tcg/tcg-op-vec.c:37:
+extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64);
ERROR: externs should be avoided in .c files
#138: FILE: tcg/tcg-op-vec.c:38:
+extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
ERROR: Macros with complex values should be enclosed in parenthesis
#535: FILE: tcg/tcg-opc.h:209:
+#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
WARNING: line over 80 characters
#538: FILE: tcg/tcg-opc.h:212:
+DEF(movi_vec, 1, 0, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) /* vecl defines const args */
ERROR: Macros with complex values should be enclosed in parenthesis
#800: FILE: tcg/tcg.h:621:
+#define TCGOP_VECL(X) (X)->param1
ERROR: Macros with complex values should be enclosed in parenthesis
#801: FILE: tcg/tcg.h:622:
+#define TCGOP_VECE(X) (X)->param2
total: 5 errors, 1 warnings, 807 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/26: tcg: Standardize integral arguments to expanders...
Checking PATCH 4/26: tcg: Add generic vector expanders...
ERROR: spaces required around that '&' (ctx:WxO)
#320: FILE: accel/tcg/tcg-runtime-gvec.c:281:
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
^
ERROR: space prohibited after that '~' (ctx:OxW)
#320: FILE: accel/tcg/tcg-runtime-gvec.c:281:
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
^
ERROR: spaces required around that '|' (ctx:WxO)
#331: FILE: accel/tcg/tcg-runtime-gvec.c:292:
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
^
ERROR: space prohibited after that '~' (ctx:OxW)
#331: FILE: accel/tcg/tcg-runtime-gvec.c:292:
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
^
ERROR: trailing whitespace
#896: FILE: tcg/tcg-op-gvec.c:464:
+ } $
total: 5 errors, 0 warnings, 2025 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/26: tcg: Add generic vector ops for interleave...
ERROR: code indent should never use tabs
#41: FILE: accel/tcg/tcg-runtime-gvec.c:318:
+^I*(TYPE *)(d + 2 * i + 0) = *(TYPE *)(a + i); \$
ERROR: code indent should never use tabs
#42: FILE: accel/tcg/tcg-runtime-gvec.c:319:
+^I*(TYPE *)(d + 2 * i + sizeof(TYPE)) = *(TYPE *)(b + i); \$
ERROR: code indent should never use tabs
#87: FILE: accel/tcg/tcg-runtime-gvec.c:364:
+^I*(TYPE *)(d + i + 0) = ae; \$
ERROR: code indent should never use tabs
#88: FILE: accel/tcg/tcg-runtime-gvec.c:365:
+^I*(TYPE *)(d + i + sizeof(TYPE)) = be; \$
total: 4 errors, 0 warnings, 571 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/26: tcg: Add generic vector ops for constant shifts...
Checking PATCH 7/26: tcg: Add generic vector ops for comparisons...
ERROR: spaces required around that '*' (ctx:WxV)
#24: FILE: accel/tcg/tcg-runtime-gvec.c:530:
+ *(TYPE *)(d + i) = *(TYPE *)(a + i) OP *(TYPE *)(b + i); \
^
ERROR: spaces required around that '==' (ctx:WxB)
#30: FILE: accel/tcg/tcg-runtime-gvec.c:536:
+ DO_CMP1(gvec_eq##SZ, vec##SZ, ==) \
^
ERROR: spaces required around that '!=' (ctx:WxB)
#31: FILE: accel/tcg/tcg-runtime-gvec.c:537:
+ DO_CMP1(gvec_ne##SZ, vec##SZ, !=) \
^
ERROR: spaces required around that '<' (ctx:WxB)
#32: FILE: accel/tcg/tcg-runtime-gvec.c:538:
+ DO_CMP1(gvec_lt##SZ, svec##SZ, <) \
^
ERROR: spaces required around that '<=' (ctx:WxB)
#33: FILE: accel/tcg/tcg-runtime-gvec.c:539:
+ DO_CMP1(gvec_le##SZ, svec##SZ, <=) \
^
ERROR: spaces required around that '<' (ctx:WxB)
#34: FILE: accel/tcg/tcg-runtime-gvec.c:540:
+ DO_CMP1(gvec_ltu##SZ, vec##SZ, <) \
^
ERROR: spaces required around that '<=' (ctx:WxB)
#35: FILE: accel/tcg/tcg-runtime-gvec.c:541:
+ DO_CMP1(gvec_leu##SZ, vec##SZ, <=)
^
ERROR: space prohibited after that '&&' (ctx:ExW)
#223: FILE: tcg/tcg-op-gvec.c:1986:
+ && check_size_impl(oprsz, 8)
^
total: 8 errors, 0 warnings, 294 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 8/26: tcg: Add generic vector ops for multiplication...
Checking PATCH 9/26: tcg: Add generic vector ops for extension...
Checking PATCH 10/26: tcg: Add generic helpers for saturating arithmetic...
ERROR: spaces required around that '&' (ctx:WxO)
#64: FILE: accel/tcg/tcg-runtime-gvec.c:661:
+ if (((di ^ ai) &~ (ai ^ bi)) < 0) {
^
ERROR: space prohibited after that '~' (ctx:OxW)
#64: FILE: accel/tcg/tcg-runtime-gvec.c:661:
+ if (((di ^ ai) &~ (ai ^ bi)) < 0) {
^
ERROR: spaces required around that '&' (ctx:WxO)
#82: FILE: accel/tcg/tcg-runtime-gvec.c:679:
+ if (((di ^ ai) &~ (ai ^ bi)) < 0) {
^
ERROR: space prohibited after that '~' (ctx:OxW)
#82: FILE: accel/tcg/tcg-runtime-gvec.c:679:
+ if (((di ^ ai) &~ (ai ^ bi)) < 0) {
^
total: 4 errors, 0 warnings, 411 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 11/26: tcg: Loosen vec_gen_op* typecheck rules...
Checking PATCH 12/26: tcg: Add generic vector helpers with a scalar immediate operand...
Checking PATCH 13/26: tcg: Add generic vector helpers with a scalar variable operand...
Checking PATCH 14/26: tcg/optimize: Handle vector opcodes during optimize...
ERROR: spaces required around that ':' (ctx:VxE)
#170: FILE: tcg/optimize.c:644:
+ CASE_OP_32_64_VEC(add):
^
ERROR: spaces required around that ':' (ctx:VxE)
#171: FILE: tcg/optimize.c:645:
+ CASE_OP_32_64_VEC(mul):
^
ERROR: spaces required around that ':' (ctx:VxE)
#172: FILE: tcg/optimize.c:646:
+ CASE_OP_32_64_VEC(and):
^
ERROR: spaces required around that ':' (ctx:VxE)
#173: FILE: tcg/optimize.c:647:
+ CASE_OP_32_64_VEC(or):
^
ERROR: spaces required around that ':' (ctx:VxE)
#174: FILE: tcg/optimize.c:648:
+ CASE_OP_32_64_VEC(xor):
^
ERROR: spaces required around that ':' (ctx:VxE)
#183: FILE: tcg/optimize.c:713:
+ CASE_OP_32_64_VEC(sub):
^
ERROR: spaces required around that ':' (ctx:VxE)
#206: FILE: tcg/optimize.c:744:
+ CASE_OP_32_64_VEC(xor):
^
ERROR: spaces required around that ':' (ctx:VxE)
#215: FILE: tcg/optimize.c:761:
+ CASE_OP_32_64_VEC(andc):
^
ERROR: spaces required around that ':' (ctx:VxE)
#224: FILE: tcg/optimize.c:769:
+ CASE_OP_32_64_VEC(orc):
^
ERROR: spaces required around that ':' (ctx:VxE)
#246: FILE: tcg/optimize.c:807:
+ CASE_OP_32_64_VEC(add):
^
ERROR: spaces required around that ':' (ctx:VxE)
#247: FILE: tcg/optimize.c:808:
+ CASE_OP_32_64_VEC(sub):
^
ERROR: spaces required around that ':' (ctx:VxE)
#248: FILE: tcg/optimize.c:809:
+ CASE_OP_32_64_VEC(or):
^
ERROR: spaces required around that ':' (ctx:VxE)
#249: FILE: tcg/optimize.c:810:
+ CASE_OP_32_64_VEC(xor):
^
ERROR: spaces required around that ':' (ctx:VxE)
#250: FILE: tcg/optimize.c:811:
+ CASE_OP_32_64_VEC(andc):
^
ERROR: spaces required around that ':' (ctx:VxE)
#268: FILE: tcg/optimize.c:824:
+ CASE_OP_32_64_VEC(and):
^
ERROR: spaces required around that ':' (ctx:VxE)
#269: FILE: tcg/optimize.c:825:
+ CASE_OP_32_64_VEC(orc):
^
ERROR: spaces required around that ':' (ctx:VxE)
#279: FILE: tcg/optimize.c:1039:
+ CASE_OP_32_64_VEC(and):
^
ERROR: spaces required around that ':' (ctx:VxE)
#280: FILE: tcg/optimize.c:1040:
+ CASE_OP_32_64_VEC(mul):
^
ERROR: spaces required around that ':' (ctx:VxE)
#290: FILE: tcg/optimize.c:1055:
+ CASE_OP_32_64_VEC(or):
^
ERROR: spaces required around that ':' (ctx:VxE)
#291: FILE: tcg/optimize.c:1056:
+ CASE_OP_32_64_VEC(and):
^
ERROR: spaces required around that ':' (ctx:VxE)
#302: FILE: tcg/optimize.c:1068:
+ CASE_OP_32_64_VEC(andc):
^
ERROR: spaces required around that ':' (ctx:VxE)
#303: FILE: tcg/optimize.c:1069:
+ CASE_OP_32_64_VEC(sub):
^
ERROR: spaces required around that ':' (ctx:VxE)
#304: FILE: tcg/optimize.c:1070:
+ CASE_OP_32_64_VEC(xor):
^
ERROR: spaces required around that ':' (ctx:VxE)
#313: FILE: tcg/optimize.c:1084:
+ CASE_OP_32_64_VEC(mov):
^
total: 24 errors, 0 warnings, 296 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 15/26: target/arm: Align vector registers...
Checking PATCH 16/26: target/arm: Use vector infrastructure for aa64 add/sub/logic...
Checking PATCH 17/26: target/arm: Use vector infrastructure for aa64 mov/not/neg...
Checking PATCH 18/26: target/arm: Use vector infrastructure for aa64 dup/movi...
Checking PATCH 19/26: target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn...
Checking PATCH 20/26: target/arm: Use vector infrastructure for aa64 constant shifts...
Checking PATCH 21/26: target/arm: Use vector infrastructure for aa64 compares...
Checking PATCH 22/26: target/arm: Use vector infrastructure for aa64 multiplies...
Checking PATCH 23/26: target/arm: Use vector infrastructure for aa64 widening shifts...
Checking PATCH 24/26: target/arm: Use vector infrastructure for aa64 orr/bic immediate...
Checking PATCH 25/26: tcg/i386: Add vector operations...
Checking PATCH 26/26: tcg/aarch64: Add vector operations...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (26 preceding siblings ...)
2018-01-16 4:02 ` [Qemu-devel] [PATCH v9 00/26] tcg: generic " no-reply
@ 2018-01-16 4:27 ` no-reply
2018-01-16 11:59 ` Peter Maydell
28 siblings, 0 replies; 32+ messages in thread
From: no-reply @ 2018-01-16 4:27 UTC (permalink / raw)
To: richard.henderson; +Cc: famz, qemu-devel, peter.maydell
Hi,
This series failed build test on ppc host. Please find the details below.
Subject: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations
Message-id: 20180116033404.31532-1-richard.henderson@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit that has the patches applied on top of "base"
# branch
set -e
echo "=== ENV ==="
env
echo "=== PACKAGES ==="
rpm -qa
echo "=== TEST BEGIN ==="
INSTALL=$PWD/install
BUILD=$PWD/build
mkdir -p $BUILD $INSTALL
SRC=$PWD
cd $BUILD
$SRC/configure --prefix=$INSTALL
make -j100
# XXX: we need reliable clean up
# make check -j100 V=1
make install
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20180106153730.30313-1-hpoussin@reactos.org -> patchew/20180106153730.30313-1-hpoussin@reactos.org
* [new tag] patchew/20180116033404.31532-1-richard.henderson@linaro.org -> patchew/20180116033404.31532-1-richard.henderson@linaro.org
Submodule 'capstone' (git://git.qemu.org/capstone.git) registered for path 'capstone'
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (git://git.qemu.org/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (git://git.qemu-project.org/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (git://git.qemu-project.org/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (git://git.qemu-project.org/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (git://git.qemu-project.org/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (git://github.com/rth7680/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (git://git.qemu-project.org/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/sgabios' (git://git.qemu-project.org/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (git://git.qemu.org/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (git://git.qemu-project.org/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/vgabios' (git://git.qemu-project.org/vgabios.git/) registered for path 'roms/vgabios'
Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'fa981320a1e0968d6fc1b8de319723ff8212b337'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out '0600d3ae94f93efd10fc6b3c7420a9557a3a1670'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '83818bdb4460170621d789429ad5a75e8c73efd1'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 'f3c7e44c70254975df2a00af39701eafbac4d471'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out '63451fca13c75870e1703eb3e20584d91179aebc'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out '762d0082f18e4fb921a2d44a1051b02d8b0f6381'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/vgabios'...
Submodule path 'roms/vgabios': checked out '19ea12c230ded95928ecaef0db47a82231c2e485'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '10739aa26051a5d49d88132604539d3ed085e72e'
Switched to a new branch 'test'
318acc6 tcg/aarch64: Add vector operations
4351115 tcg/i386: Add vector operations
c29ad91 target/arm: Use vector infrastructure for aa64 orr/bic immediate
083b52d target/arm: Use vector infrastructure for aa64 widening shifts
d637139 target/arm: Use vector infrastructure for aa64 multiplies
25df8a6 target/arm: Use vector infrastructure for aa64 compares
57c1ab2 target/arm: Use vector infrastructure for aa64 constant shifts
8bfefd6 target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
ad7234c target/arm: Use vector infrastructure for aa64 dup/movi
6f14f6c target/arm: Use vector infrastructure for aa64 mov/not/neg
d97b762 target/arm: Use vector infrastructure for aa64 add/sub/logic
1ddbc66 target/arm: Align vector registers
d7a8026 tcg/optimize: Handle vector opcodes during optimize
fbeeb21 tcg: Add generic vector helpers with a scalar variable operand
5155c31 tcg: Add generic vector helpers with a scalar immediate operand
e13611c tcg: Loosen vec_gen_op* typecheck rules
03086db tcg: Add generic helpers for saturating arithmetic
ef1031a tcg: Add generic vector ops for extension
1629aea tcg: Add generic vector ops for multiplication
9788bde tcg: Add generic vector ops for comparisons
58c28e1 tcg: Add generic vector ops for constant shifts
cc69b26 tcg: Add generic vector ops for interleave
7c955c7 tcg: Add generic vector expanders
62b38cf tcg: Standardize integral arguments to expanders
fbdd0d5 tcg: Add types and basic operations for host vectors
3d46adc tcg: Allow multiple word entries into the constant pool
=== OUTPUT BEGIN ===
=== ENV ===
XDG_SESSION_ID=139424
SHELL=/bin/sh
USER=patchew
PATCHEW=/home/patchew/patchew/patchew-cli -s http://patchew.org --nodebug
PATH=/usr/bin:/bin
PWD=/var/tmp/patchew-tester-tmp-r7vd2rsz/src
LANG=en_US.UTF-8
HOME=/home/patchew
SHLVL=2
LOGNAME=patchew
XDG_RUNTIME_DIR=/run/user/1000
_=/usr/bin/env
=== PACKAGES ===
plymouth-core-libs-0.8.9-0.28.20140113.el7.centos.ppc64le
vim-common-7.4.160-2.el7.ppc64le
perl-Test-Simple-0.98-243.el7.noarch
hplip-common-3.15.9-3.el7.ppc64le
valgrind-3.12.0-8.el7.ppc64le
gamin-0.1.10-16.el7.ppc64le
libpeas-loader-python-1.20.0-1.el7.ppc64le
telepathy-filesystem-0.0.2-6.el7.noarch
colord-libs-1.3.4-1.el7.ppc64le
kbd-legacy-1.15.5-13.el7.noarch
perl-CPAN-Meta-YAML-0.008-14.el7.noarch
libvirt-daemon-driver-nwfilter-3.2.0-14.el7.ppc64le
ntsysv-1.7.4-1.el7.ppc64le
kernel-bootwrapper-3.10.0-693.el7.ppc64le
telepathy-farstream-0.6.0-5.el7.ppc64le
kdenetwork-common-4.10.5-8.el7_0.noarch
elfutils-devel-0.168-8.el7.ppc64le
pm-utils-1.4.1-27.el7.ppc64le
perl-Error-0.17020-2.el7.noarch
usbmuxd-1.1.0-1.el7.ppc64le
bzip2-devel-1.0.6-13.el7.ppc64le
blktrace-1.0.5-8.el7.ppc64le
gnome-keyring-pam-3.20.0-3.el7.ppc64le
tzdata-java-2017b-1.el7.noarch
perl-devel-5.16.3-292.el7.ppc64le
gnome-getting-started-docs-3.22.0-1.el7.noarch
perl-Log-Message-Simple-0.10-2.el7.noarch
totem-pl-parser-3.10.7-1.el7.ppc64le
lohit-oriya-fonts-2.5.4.1-3.el7.noarch
python-coverage-3.6-0.5.b3.el7.ppc64le
java-1.7.0-openjdk-1.7.0.141-2.6.10.5.el7.ppc64le
mailcap-2.1.41-2.el7.noarch
perl-CPANPLUS-0.91.38-4.el7.noarch
fprintd-pam-0.5.0-4.0.el7_0.ppc64le
less-458-9.el7.ppc64le
gupnp-igd-0.2.4-1.el7.ppc64le
thai-scalable-waree-fonts-0.5.0-7.el7.noarch
python-di-0.3-2.el7.noarch
yelp-libs-3.22.0-1.el7.ppc64le
vte-profile-0.46.2-1.el7.ppc64le
gpm-libs-1.20.7-5.el7.ppc64le
gnome-clocks-3.22.1-1.el7.ppc64le
p11-kit-trust-0.23.5-3.el7.ppc64le
gssproxy-0.7.0-4.el7.ppc64le
gnu-free-mono-fonts-20120503-8.el7.noarch
python-dateutil-1.5-7.el7.noarch
gucharmap-libs-3.18.2-1.el7.ppc64le
glibc-common-2.17-196.el7.ppc64le
libreport-plugin-mantisbt-2.1.11-38.el7.centos.ppc64le
motif-devel-2.3.4-8.1.el7_3.ppc64le
celt051-0.5.1.3-8.el7.ppc64le
radvd-1.9.2-9.el7.ppc64le
lohit-tamil-fonts-2.5.3-2.el7.noarch
python-ipaddress-1.0.16-2.el7.noarch
anaconda-widgets-21.48.22.121-1.el7.centos.ppc64le
zlib-1.2.7-17.el7.ppc64le
libstdc++-devel-4.8.5-16.el7.ppc64le
system-config-printer-1.4.1-19.el7.ppc64le
mozjs24-24.2.0-7.el7.ppc64le
device-mapper-multipath-libs-0.4.9-111.el7.ppc64le
wqy-microhei-fonts-0.2.0-0.12.beta.el7.noarch
python-schedutils-0.4-6.el7.ppc64le
gnome-bluetooth-3.20.1-1.el7.ppc64le
nss-util-3.28.4-3.el7.ppc64le
dotconf-1.3-8.el7.ppc64le
ibus-rawcode-1.3.2-3.el7.ppc64le
abattis-cantarell-fonts-0.0.25-1.el7.noarch
sssd-common-1.15.2-50.el7.ppc64le
sil-padauk-fonts-2.8-5.el7.noarch
bind-utils-9.9.4-50.el7.ppc64le
sox-14.4.1-6.el7.ppc64le
libSM-1.2.2-2.el7.ppc64le
libtiff-devel-4.0.3-27.el7_3.ppc64le
plymouth-system-theme-0.8.9-0.28.20140113.el7.centos.ppc64le
python-libs-2.7.5-58.el7.ppc64le
sssd-1.15.2-50.el7.ppc64le
rfkill-0.4-9.el7.ppc64le
cyrus-sasl-md5-2.1.26-21.el7.ppc64le
libXtst-devel-1.2.3-1.el7.ppc64le
avahi-libs-0.6.31-17.el7.ppc64le
ruby-2.0.0.648-30.el7.ppc64le
seahorse-3.20.0-1.el7.ppc64le
python-six-1.9.0-2.el7.noarch
gpgme-1.3.2-5.el7.ppc64le
iwl7260-firmware-22.0.7.0-56.el7.noarch
libsss_certmap-1.15.2-50.el7.ppc64le
xorg-x11-drv-wacom-0.34.2-2.el7.ppc64le
libXau-1.0.8-2.1.el7.ppc64le
shadow-utils-4.1.5.1-24.el7.ppc64le
evolution-ews-3.22.6-6.el7.ppc64le
libsecret-0.18.5-2.el7.ppc64le
perl-Module-Signature-0.73-2.el7.noarch
rootfiles-8.1-11.el7.noarch
trace-cmd-2.6.0-8.el7.ppc64le
hamcrest-1.3-6.el7.noarch
gawk-4.0.2-4.el7_3.1.ppc64le
usermode-1.111-5.el7.ppc64le
gnome-terminal-nautilus-3.22.1-2.el7.ppc64le
gvfs-client-1.30.4-3.el7.ppc64le
yum-utils-1.1.31-42.el7.noarch
iwl3945-firmware-15.32.2.9-56.el7.noarch
perl-Archive-Zip-1.30-11.el7.noarch
spice-glib-0.33-6.el7.ppc64le
augeas-libs-1.4.0-2.el7.ppc64le
openlmi-providers-0.5.0-4.el7.ppc64le
gnome-color-manager-3.22.2-1.el7.ppc64le
imsettings-libs-1.6.3-9.el7.ppc64le
nss-softokn-devel-3.28.3-6.el7.ppc64le
python34-3.4.5-4.el7.ppc64le
perl-DBI-1.627-4.el7.ppc64le
plymouth-plugin-label-0.8.9-0.28.20140113.el7.centos.ppc64le
binutils-2.25.1-31.base.el7.ppc64le
libsss_nss_idmap-1.15.2-50.el7.ppc64le
gvfs-smb-1.30.4-3.el7.ppc64le
freetype-devel-2.4.11-15.el7.ppc64le
libXi-1.7.9-1.el7.ppc64le
perl-Text-Diff-1.41-5.el7.noarch
gcr-devel-3.20.0-1.el7.ppc64le
numactl-libs-2.0.9-6.el7_2.ppc64le
hardlink-1.0-19.el7.ppc64le
gnome-disk-utility-3.22.1-1.el7.ppc64le
mariadb-libs-5.5.56-2.el7.ppc64le
libnotify-0.7.7-1.el7.ppc64le
perl-TimeDate-2.30-2.el7.noarch
soprano-devel-2.9.2-3.el7.ppc64le
pixman-0.34.0-1.el7.ppc64le
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kdenetwork-krdc-libs-4.10.5-8.el7_0.ppc64le
opal-prd-5.5.0-1.el7.ppc64le
rdma-core-13-7.el7.ppc64le
pulseaudio-10.0-3.el7.ppc64le
python-sssdconfig-1.15.2-50.el7.noarch
libisofs-1.2.8-4.el7.ppc64le
libverto-0.2.5-4.el7.ppc64le
kdesdk-kmtrace-devel-4.10.5-6.el7.ppc64le
systemd-devel-219-42.el7.ppc64le
mesa-dri-drivers-17.0.1-6.20170307.el7.ppc64le
clutter-1.26.0-1.el7.ppc64le
fipscheck-1.4.1-6.el7.ppc64le
dwz-0.11-3.el7.ppc64le
boost-regex-1.53.0-27.el7.ppc64le
libXaw-1.0.13-4.el7.ppc64le
gcc-gfortran-4.8.5-16.el7.ppc64le
systemd-python-219-42.el7.ppc64le
zenity-3.22.0-1.el7.ppc64le
boost-atomic-1.53.0-27.el7.ppc64le
rpm-libs-4.11.3-25.el7.ppc64le
GeoIP-1.5.0-11.el7.ppc64le
libksane-devel-4.10.5-4.el7.ppc64le
rubygem-bundler-1.7.8-3.el7.noarch
git-1.8.3.1-11.el7.ppc64le
brasero-libs-3.12.1-2.el7.ppc64le
c-ares-1.10.0-3.el7.ppc64le
libnfsidmap-0.25-17.el7.ppc64le
cdparanoia-libs-10.2-17.el7.ppc64le
tk-8.5.13-6.el7.ppc64le
libhugetlbfs-devel-2.16-12.el7.ppc64le
NetworkManager-wifi-1.8.0-9.el7.ppc64le
libcanberra-gtk2-0.30-5.el7.ppc64le
hostname-3.13-3.el7.ppc64le
redland-1.0.16-6.el7.ppc64le
libdaemon-0.14-7.el7.ppc64le
brasero-3.12.1-2.el7.ppc64le
cups-devel-1.6.3-29.el7.ppc64le
qca2-2.0.3-7.el7.ppc64le
pangomm-2.40.1-1.el7.ppc64le
libnetfilter_conntrack-1.0.6-1.el7_3.ppc64le
sip-devel-4.14.6-4.el7.ppc64le
perl-parent-0.225-244.el7.noarch
libkkc-0.3.1-9.el7.ppc64le
crypto-utils-2.4.1-42.el7.ppc64le
lvm2-2.02.171-8.el7.ppc64le
poppler-glib-0.26.5-16.el7.ppc64le
crash-7.1.9-2.el7.ppc64le
libbluray-0.2.3-5.el7.ppc64le
perl-Filter-1.49-3.el7.ppc64le
control-center-3.22.2-5.el7.ppc64le
c-ares-devel-1.10.0-3.el7.ppc64le
sysstat-10.1.5-12.el7.ppc64le
mesa-libGL-devel-17.0.1-6.20170307.el7.ppc64le
python-pwquality-1.2.3-4.el7.ppc64le
liblouis-python-2.5.2-10.el7.noarch
perl-PathTools-3.40-5.el7.ppc64le
gnome-shell-extension-apps-menu-3.22.2-10.el7.noarch
hunspell-devel-1.3.2-15.el7.ppc64le
policycoreutils-python-2.5-17.1.el7.ppc64le
libwnck3-3.20.1-1.el7.ppc64le
gsettings-desktop-schemas-devel-3.22.0-1.el7.ppc64le
lsof-4.87-4.el7.ppc64le
perl-Getopt-Long-2.40-2.el7.noarch
nfs-utils-1.3.0-0.48.el7.ppc64le
mtr-0.85-7.el7.ppc64le
autofs-5.0.7-69.el7.ppc64le
cairo-devel-1.14.8-2.el7.ppc64le
xorg-x11-xbitmaps-1.1.1-6.el7.noarch
libreport-2.1.11-38.el7.centos.ppc64le
perl-XML-Parser-2.41-10.el7.ppc64le
libvirt-daemon-driver-storage-3.2.0-14.el7.ppc64le
python2-caribou-0.4.21-1.el7.noarch
fontpackages-filesystem-1.44-8.el7.noarch
perl-Test-Pod-1.48-3.el7.noarch
libuuid-devel-2.23.2-43.el7.ppc64le
perl-Package-Constants-0.02-292.el7.noarch
gnutls-3.3.26-9.el7.ppc64le
libreport-cli-2.1.11-38.el7.centos.ppc64le
gettext-common-devel-0.19.8.1-2.el7.noarch
cups-filters-1.0.35-22.el7.ppc64le
xkeyboard-config-2.20-1.el7.noarch
bison-3.0.4-1.el7.ppc64le
compat-libcolord1-1.0.4-1.el7.ppc64le
perl-Digest-MD5-2.52-3.el7.ppc64le
gnutls-dane-3.3.26-9.el7.ppc64le
libusbx-devel-1.0.20-1.el7.ppc64le
initial-setup-0.3.9.40-1.el7.centos.ppc64le
libchamplain-gtk-0.12.15-1.el7.ppc64le
libreport-filesystem-2.1.11-38.el7.centos.ppc64le
m17n-contrib-1.1.14-3.el7.noarch
newt-python-0.52.15-4.el7.ppc64le
perl-Locale-Maketext-1.23-3.el7.noarch
libvirt-daemon-driver-nodedev-3.2.0-14.el7.ppc64le
perl-ExtUtils-Install-1.58-292.el7.noarch
libvirt-3.2.0-14.el7.ppc64le
gnome-themes-standard-3.22.2-1.el7.ppc64le
gl-manpages-1.1-7.20130122.el7.noarch
lohit-gujarati-fonts-2.5.3-2.el7.noarch
python-backports-ssl_match_hostname-3.4.0.2-4.el7.noarch
perl-local-lib-1.008010-4.el7.noarch
rest-0.8.0-1.el7.ppc64le
perl-Module-Build-0.40.05-2.el7.noarch
ibus-kkc-1.5.18-7.el7.ppc64le
webkitgtk4-plugin-process-gtk2-2.14.7-2.el7.ppc64le
basesystem-10.0-7.el7.centos.noarch
madan-fonts-2.000-11.el7.noarch
python-beaker-1.5.4-10.el7.noarch
boost-locale-1.53.0-27.el7.ppc64le
dleyna-core-0.5.0-1.el7.ppc64le
liberation-sans-fonts-1.07.2-15.el7.noarch
tk-devel-8.5.13-6.el7.ppc64le
gnome-packagekit-updater-3.22.1-2.el7.ppc64le
cim-schema-2.33.0-6.el7.noarch
lohit-assamese-fonts-2.5.3-2.el7.noarch
tagsoup-1.2.1-8.el7.noarch
libshout-2.2.2-11.el7.ppc64le
ntpdate-4.2.6p5-25.el7.centos.2.ppc64le
libproxy-0.4.11-10.el7.ppc64le
gvfs-gphoto2-1.30.4-3.el7.ppc64le
gspell-1.2.3-1.el7.ppc64le
libstdc++-4.8.5-16.el7.ppc64le
sil-nuosu-fonts-2.1.1-5.el7.noarch
python-ntplib-0.3.2-1.el7.noarch
bc-1.06.95-13.el7.ppc64le
libvirt-daemon-driver-lxc-3.2.0-14.el7.ppc64le
libreport-anaconda-2.1.11-38.el7.centos.ppc64le
kdepimlibs-devel-4.10.5-4.el7.ppc64le
unique3-3.0.2-8.el7.ppc64le
freetype-2.4.11-15.el7.ppc64le
lohit-marathi-fonts-2.5.3-2.el7.noarch
python2-cryptography-1.7.2-1.el7.ppc64le
libss-1.42.9-10.el7.ppc64le
kernel-tools-libs-3.10.0-693.el7.ppc64le
libsysfs-2.1.0-16.el7.ppc64le
ibus-hangul-1.4.2-10.el7.ppc64le
freerdp-1.0.2-10.el7.ppc64le
popt-1.13-16.el7.ppc64le
open-sans-fonts-1.10-1.el7.noarch
bind-libs-lite-9.9.4-50.el7.ppc64le
lksctp-tools-1.0.17-2.el7.ppc64le
sssd-common-pac-1.15.2-50.el7.ppc64le
libtiff-4.0.3-27.el7_3.ppc64le
gnome-desktop3-devel-3.22.2-2.el7.ppc64le
cdrdao-1.2.3-20.el7.ppc64le
expat-2.1.0-10.el7_3.ppc64le
latrace-0.5.11-6.1.el7.ppc64le
perl-Net-SSLeay-1.55-6.el7.ppc64le
cups-libs-1.6.3-29.el7.ppc64le
dmraid-events-1.0.0.rc16-28.el7.ppc64le
rubygem-io-console-0.4.2-30.el7.ppc64le
gutenprint-cups-5.2.9-18.el7.ppc64le
xorg-x11-server-Xorg-1.19.3-11.el7.ppc64le
libtalloc-2.1.9-1.el7.ppc64le
iwl6000g2b-firmware-17.168.5.2-56.el7.noarch
nss-sysinit-3.28.4-8.el7.ppc64le
glib2-2.50.3-3.el7.ppc64le
rpm-python-4.11.3-25.el7.ppc64le
ustr-1.0.4-16.el7.ppc64le
gucharmap-3.18.2-1.el7.ppc64le
xorg-x11-drv-dummy-0.3.7-1.el7.ppc64le
libogg-1.3.0-7.el7.ppc64le
iwl6000-firmware-9.221.4.1-56.el7.noarch
docbook-dtds-1.0-60.el7.noarch
xorg-x11-proto-devel-7.7-20.el7.noarch
pygpgme-0.3-9.el7.ppc64le
openssh-7.4p1-11.el7.ppc64le
cheese-3.22.1-1.el7.ppc64le
jline-1.0-8.el7.noarch
libcap-2.22-9.el7.ppc64le
ivtv-firmware-20080701-26.el7.noarch
perl-Pod-LaTeX-0.61-2.el7.noarch
enchant-1.6.0-8.el7.ppc64le
python2-ipalib-4.5.0-20.el7.centos.noarch
tog-pegasus-libs-2.14.1-5.el7.ppc64le
firstboot-19.12-1.el7.ppc64le
gupnp-dlna-0.10.5-1.el7.ppc64le
which-2.20-7.el7.ppc64le
epel-release-7-9.noarch
perl-Net-Daemon-0.48-5.el7.noarch
libcroco-0.6.11-1.el7.ppc64le
liboauth-devel-0.9.7-4.el7.ppc64le
libhangul-0.1.0-8.el7.ppc64le
eog-3.20.5-2.el7.ppc64le
plymouth-theme-charge-0.8.9-0.28.20140113.el7.centos.ppc64le
libcollection-0.6.2-27.el7.ppc64le
perl-Locale-Codes-3.26-2.el7.noarch
pygobject2-2.28.6-11.el7.ppc64le
libXdamage-1.1.4-4.1.el7.ppc64le
libestr-0.1.9-2.el7.ppc64le
PackageKit-gtk3-module-1.1.5-1.el7.centos.ppc64le
libgweather-devel-3.20.4-1.el7.ppc64le
xz-5.2.2-1.el7.ppc64le
perl-WWW-RobotRules-6.02-5.el7.noarch
libICE-devel-1.0.9-9.el7.ppc64le
libXft-2.3.2-2.el7.ppc64le
cryptsetup-libs-1.7.4-3.el7.ppc64le
alsa-plugins-pulseaudio-1.1.1-1.el7.ppc64le
glx-utils-8.2.0-3.el7.ppc64le
speex-1.2-0.19.rc1.el7.ppc64le
perl-HTTP-Negotiate-6.01-5.el7.noarch
libtirpc-0.2.4-0.10.el7.ppc64le
pulseaudio-libs-glib2-10.0-3.el7.ppc64le
mesa-libgbm-17.0.1-6.20170307.el7.ppc64le
pulseaudio-libs-devel-10.0-3.el7.ppc64le
imsettings-1.6.3-9.el7.ppc64le
hunspell-en-US-0.20121024-6.el7.noarch
perl-IO-Socket-IP-0.21-4.el7.noarch
nss-util-devel-3.28.4-3.el7.ppc64le
libXxf86vm-1.1.4-1.el7.ppc64le
hwdata-0.252-8.6.el7.ppc64le
kernel-tools-3.10.0-693.el7.ppc64le
nepomuk-core-libs-4.10.5-5.el7.ppc64le
exiv2-libs-0.23-6.el7.ppc64le
perl-libwww-perl-6.05-2.el7.noarch
p11-kit-devel-0.23.5-3.el7.ppc64le
librsvg2-2.40.16-1.el7.ppc64le
libsmbclient-4.6.2-8.el7.ppc64le
abrt-console-notification-2.1.11-48.el7.centos.ppc64le
kdesdk-okteta-libs-4.10.5-6.el7.ppc64le
boost-chrono-1.53.0-27.el7.ppc64le
iw-4.3-1.el7.ppc64le
libcom_err-devel-1.42.9-10.el7.ppc64le
akonadi-1.9.2-4.el7.ppc64le
accountsservice-libs-0.6.45-2.el7.ppc64le
wvdial-1.61-9.el7.ppc64le
libkexiv2-devel-4.10.5-3.el7.ppc64le
libmpc-1.0.1-3.el7.ppc64le
lm_sensors-devel-3.4.0-4.20160601gitf9185e5.el7.ppc64le
meanwhile-1.1.0-12.el7.ppc64le
libXt-devel-1.1.5-3.el7.ppc64le
plymouth-scripts-0.8.9-0.28.20140113.el7.centos.ppc64le
mod_fcgid-2.3.9-4.el7.ppc64le
kdepim-runtime-libs-4.10.5-3.el7.ppc64le
mesa-libglapi-17.0.1-6.20170307.el7.ppc64le
hunspell-en-GB-0.20121024-6.el7.noarch
sip-4.14.6-4.el7.ppc64le
cairomm-1.12.0-1.el7.ppc64le
abrt-addon-xorg-2.1.11-48.el7.centos.ppc64le
ModemManager-1.6.0-2.el7.ppc64le
kdenetwork-krdc-devel-4.10.5-8.el7_0.ppc64le
libieee1284-0.2.11-15.el7.ppc64le
highlight-3.13-3.el7.ppc64le
pyOpenSSL-0.13.1-3.el7.ppc64le
gtk-update-icon-cache-3.22.10-4.el7.ppc64le
NetworkManager-1.8.0-9.el7.ppc64le
crda-3.13_2016.02.08-1.el7.ppc64le
kdesdk-kompare-libs-4.10.5-6.el7.ppc64le
newt-0.52.15-4.el7.ppc64le
xcb-util-0.4.0-2.el7.ppc64le
automake-1.13.4-3.el7.noarch
libgweather-3.20.4-1.el7.ppc64le
lockdev-1.0.4-0.13.20111007git.el7.ppc64le
man-db-2.6.3-9.el7.ppc64le
gd-2.0.35-26.el7.ppc64le
exempi-2.2.0-8.el7.ppc64le
curl-7.29.0-42.el7.ppc64le
snappy-1.1.0-3.el7.ppc64le
libreport-gtk-2.1.11-38.el7.centos.ppc64le
unbound-libs-1.4.20-34.el7.ppc64le
tcpdump-4.9.0-5.el7.ppc64le
sane-backends-drivers-scanners-1.0.24-9.el7.ppc64le
libedit-3.0-12.20121213cvs.el7.ppc64le
liboauth-0.9.7-4.el7.ppc64le
libmpcdec-1.2.6-12.el7.ppc64le
libnm-gtk-1.8.0-3.el7.ppc64le
grub2-tools-extra-2.02-0.64.el7.centos.ppc64le
libitm-devel-4.8.5-16.el7.ppc64le
libdmx-1.1.3-3.el7.ppc64le
wavpack-4.60.1-9.el7.ppc64le
rasqal-0.9.30-4.el7.ppc64le
autogen-libopts-5.18-5.el7.ppc64le
gnome-bluetooth-libs-3.20.1-1.el7.ppc64le
qt-settings-19-23.5.el7.centos.noarch
libxslt-devel-1.1.28-5.el7.ppc64le
grilo-plugins-0.3.4-1.el7.ppc64le
SDL-1.2.15-14.el7.ppc64le
sip-macros-4.14.6-4.el7.ppc64le
iptables-1.4.21-18.0.1.el7.centos.ppc64le
gstreamer-plugins-good-0.10.31-13.el7.ppc64le
qjson-0.8.1-4.el7.ppc64le
perl-Test-Pod-Coverage-1.08-21.el7.noarch
pcp-conf-3.11.8-7.el7.ppc64le
perl-podlators-2.5.1-3.el7.noarch
libcurl-devel-7.29.0-42.el7.ppc64le
graphite2-devel-1.3.6-1.el7_2.ppc64le
pygtk2-2.24.0-9.el7.ppc64le
kexec-tools-2.0.14-17.el7.ppc64le
iptables-devel-1.4.21-18.0.1.el7.centos.ppc64le
gnome-shell-3.22.3-17.el7.ppc64le
perl-Carp-1.26-244.el7.noarch
liblouis-2.5.2-10.el7.ppc64le
dvd+rw-tools-7.1-15.el7.ppc64le
ptlib-2.10.10-6.el7.ppc64le
samba-common-libs-4.6.2-8.el7.ppc64le
gvfs-devel-1.30.4-3.el7.ppc64le
gnome-shell-extension-launch-new-instance-3.22.2-10.el7.noarch
perl-libs-5.16.3-292.el7.ppc64le
libselinux-utils-2.5-11.el7.ppc64le
libsepol-devel-2.5-6.el7.ppc64le
festival-lib-1.96-28.el7.ppc64le
oddjob-0.31.5-4.el7.ppc64le
latencytop-tui-0.5-13.el7.ppc64le
libvirt-daemon-driver-storage-core-3.2.0-14.el7.ppc64le
perl-Data-Dumper-2.145-3.el7.ppc64le
libreport-python-2.1.11-38.el7.centos.ppc64le
libical-devel-1.0.1-1.el7.ppc64le
libmx-1.4.7-10.el7.ppc64le
cups-pk-helper-0.2.6-2.el7.ppc64le
=== TEST BEGIN ===
Install prefix /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install
BIOS directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/share/qemu
firmware path /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/share/qemu-firmware
binary directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/bin
library directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/lib
module directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/lib/qemu
libexec directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/libexec
include directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/include
config directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/etc
local state directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/var
Manual directory /var/tmp/patchew-tester-tmp-r7vd2rsz/src/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /var/tmp/patchew-tester-tmp-r7vd2rsz/src
GIT binary git
GIT submodules ui/keycodemapdb dtc capstone
C compiler cc
Host C compiler cc
C++ compiler c++
Objective-C compiler cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -Werror -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -DNCURSES_WIDECHAR -m64 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -Wno-missing-braces -I/usr/include/p11-kit-1 -I/usr/include/libpng15 -I$(SRC_PATH)/capstone/include
LDFLAGS -Wl,--warn-common -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU ppc64
host big endian no
target list aarch64-softmmu alpha-softmmu arm-softmmu cris-softmmu i386-softmmu lm32-softmmu m68k-softmmu microblazeel-softmmu microblaze-softmmu mips64el-softmmu mips64-softmmu mipsel-softmmu mips-softmmu moxie-softmmu nios2-softmmu or1k-softmmu ppc64-softmmu ppcemb-softmmu ppc-softmmu s390x-softmmu sh4eb-softmmu sh4-softmmu sparc64-softmmu sparc-softmmu tricore-softmmu unicore32-softmmu x86_64-softmmu xtensaeb-softmmu xtensa-softmmu aarch64_be-linux-user aarch64-linux-user alpha-linux-user armeb-linux-user arm-linux-user cris-linux-user hppa-linux-user i386-linux-user m68k-linux-user microblazeel-linux-user microblaze-linux-user mips64el-linux-user mips64-linux-user mipsel-linux-user mips-linux-user mipsn32el-linux-user mipsn32-linux-user nios2-linux-user or1k-linux-user ppc64abi32-linux-user ppc64le-linux-user ppc64-linux-user ppc-linux-user s390x-linux-user sh4eb-linux-user sh4-linux-user sparc32plus-linux-user sparc64-linux-user sparc-linux-user tilegx-linux-user x86_64-linux-user
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
SDL support yes (1.2.15)
GTK support yes (3.22.10)
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support yes
GNUTLS rnd yes
libgcrypt no
libgcrypt kdf no
nettle yes (2.7.1)
nettle kdf yes
libtasn1 yes
curses support yes
virgl support no
curl support yes
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support yes
Multipath support no
VNC support yes
VNC SASL support yes
VNC JPEG support yes
VNC PNG support yes
xen support no
brlapi support no
bluez support no
Documentation no
PIE no
vde support no
netmap support no
Linux AIO support yes
ATTR/XATTR support yes
Install blobs yes
KVM support yes
HAX support no
HVF support no
TCG support yes
TCG debug enabled no
TCG interpreter no
malloc trim support yes
RDMA support yes
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support yes
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
vhost-user support yes
Trace backends log
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb yes
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
crypto afalg no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support no
TPM passthrough no
TPM emulator yes
QOM debugging yes
Live block migration yes
lzo support no
snappy support no
bzip2 support yes
NUMA host support yes
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
VxHS block device no
capstone git
GEN aarch64-softmmu/config-devices.mak.tmp
GEN alpha-softmmu/config-devices.mak.tmp
GEN arm-softmmu/config-devices.mak.tmp
GEN cris-softmmu/config-devices.mak.tmp
GEN i386-softmmu/config-devices.mak.tmp
GEN lm32-softmmu/config-devices.mak.tmp
GEN microblazeel-softmmu/config-devices.mak.tmp
GEN microblaze-softmmu/config-devices.mak.tmp
GEN mips64el-softmmu/config-devices.mak.tmp
GEN mipsel-softmmu/config-devices.mak.tmp
GEN mips64-softmmu/config-devices.mak.tmp
GEN m68k-softmmu/config-devices.mak.tmp
GEN moxie-softmmu/config-devices.mak.tmp
GEN nios2-softmmu/config-devices.mak.tmp
GEN or1k-softmmu/config-devices.mak.tmp
GEN ppc64-softmmu/config-devices.mak.tmp
GEN mips-softmmu/config-devices.mak.tmp
GEN ppcemb-softmmu/config-devices.mak.tmp
GEN alpha-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN cris-softmmu/config-devices.mak
GEN lm32-softmmu/config-devices.mak
GEN i386-softmmu/config-devices.mak
GEN m68k-softmmu/config-devices.mak
GEN microblazeel-softmmu/config-devices.mak
GEN arm-softmmu/config-devices.mak
GEN microblaze-softmmu/config-devices.mak
GEN mipsel-softmmu/config-devices.mak
GEN sh4eb-softmmu/config-devices.mak.tmp
GEN mips64el-softmmu/config-devices.mak
GEN nios2-softmmu/config-devices.mak
GEN s390x-softmmu/config-devices.mak.tmp
GEN sh4-softmmu/config-devices.mak.tmp
GEN ppc-softmmu/config-devices.mak.tmp
GEN or1k-softmmu/config-devices.mak
GEN sparc64-softmmu/config-devices.mak.tmp
GEN moxie-softmmu/config-devices.mak
GEN mips64-softmmu/config-devices.mak
GEN ppc64-softmmu/config-devices.mak
GEN mips-softmmu/config-devices.mak
GEN s390x-softmmu/config-devices.mak
GEN ppcemb-softmmu/config-devices.mak
GEN sparc-softmmu/config-devices.mak.tmp
GEN tricore-softmmu/config-devices.mak.tmp
GEN unicore32-softmmu/config-devices.mak.tmp
GEN sh4-softmmu/config-devices.mak
GEN x86_64-softmmu/config-devices.mak.tmp
GEN sh4eb-softmmu/config-devices.mak
GEN sparc64-softmmu/config-devices.mak
GEN xtensa-softmmu/config-devices.mak.tmp
GEN aarch64_be-linux-user/config-devices.mak.tmp
GEN aarch64-linux-user/config-devices.mak.tmp
GEN alpha-linux-user/config-devices.mak.tmp
GEN armeb-linux-user/config-devices.mak.tmp
GEN ppc-softmmu/config-devices.mak
GEN arm-linux-user/config-devices.mak.tmp
GEN sparc-softmmu/config-devices.mak
GEN cris-linux-user/config-devices.mak.tmp
GEN xtensaeb-softmmu/config-devices.mak.tmp
GEN i386-linux-user/config-devices.mak.tmp
GEN m68k-linux-user/config-devices.mak.tmp
GEN tricore-softmmu/config-devices.mak
GEN unicore32-softmmu/config-devices.mak
GEN hppa-linux-user/config-devices.mak.tmp
GEN aarch64_be-linux-user/config-devices.mak
GEN x86_64-softmmu/config-devices.mak
GEN xtensa-softmmu/config-devices.mak
GEN aarch64-linux-user/config-devices.mak
GEN alpha-linux-user/config-devices.mak
GEN armeb-linux-user/config-devices.mak
GEN arm-linux-user/config-devices.mak
GEN i386-linux-user/config-devices.mak
GEN cris-linux-user/config-devices.mak
GEN m68k-linux-user/config-devices.mak
GEN hppa-linux-user/config-devices.mak
GEN xtensaeb-softmmu/config-devices.mak
GEN microblazeel-linux-user/config-devices.mak.tmp
GEN microblaze-linux-user/config-devices.mak.tmp
GEN mips64el-linux-user/config-devices.mak.tmp
GEN mips64-linux-user/config-devices.mak.tmp
GEN mipsel-linux-user/config-devices.mak.tmp
GEN mips-linux-user/config-devices.mak.tmp
GEN mipsn32el-linux-user/config-devices.mak.tmp
GEN mipsn32-linux-user/config-devices.mak.tmp
GEN microblazeel-linux-user/config-devices.mak
GEN or1k-linux-user/config-devices.mak.tmp
GEN nios2-linux-user/config-devices.mak.tmp
GEN ppc64abi32-linux-user/config-devices.mak.tmp
GEN ppc64le-linux-user/config-devices.mak.tmp
GEN ppc64-linux-user/config-devices.mak.tmp
GEN mips64-linux-user/config-devices.mak
GEN mips64el-linux-user/config-devices.mak
GEN ppc-linux-user/config-devices.mak.tmp
GEN s390x-linux-user/config-devices.mak.tmp
GEN sh4eb-linux-user/config-devices.mak.tmp
GEN mipsn32el-linux-user/config-devices.mak
GEN sparc32plus-linux-user/config-devices.mak.tmp
GEN sh4-linux-user/config-devices.mak.tmp
GEN sparc64-linux-user/config-devices.mak.tmp
GEN sparc-linux-user/config-devices.mak.tmp
GEN microblaze-linux-user/config-devices.mak
GEN mips-linux-user/config-devices.mak
GEN mipsel-linux-user/config-devices.mak
GEN nios2-linux-user/config-devices.mak
GEN ppc64le-linux-user/config-devices.mak
GEN mipsn32-linux-user/config-devices.mak
GEN ppc64abi32-linux-user/config-devices.mak
GEN or1k-linux-user/config-devices.mak
GEN sh4eb-linux-user/config-devices.mak
GEN ppc64-linux-user/config-devices.mak
GEN sparc32plus-linux-user/config-devices.mak
GEN tilegx-linux-user/config-devices.mak.tmp
GEN ppc-linux-user/config-devices.mak
GEN s390x-linux-user/config-devices.mak
GEN x86_64-linux-user/config-devices.mak.tmp
GEN sparc64-linux-user/config-devices.mak
GEN sh4-linux-user/config-devices.mak
GEN sparc-linux-user/config-devices.mak
GEN config-host.h
GIT ui/keycodemapdb dtc capstone
GEN x86_64-linux-user/config-devices.mak
GEN tilegx-linux-user/config-devices.mak
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN qapi-types.c
GEN qmp-marshal.c
GEN qapi-visit.c
GEN qmp-introspect.h
GEN qapi-event.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers-wrappers.h
GEN qmp-introspect.c
GEN trace/generated-helpers.c
GEN module_block.h
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN tests/test-qmp-commands.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN chardev/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sparc64/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN hw/ide/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN accel/tcg/trace.h
GEN accel/kvm/trace.h
GEN nbd/trace.h
GEN scsi/trace.h
GEN trace-root.c
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN chardev/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sparc64/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN hw/ide/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN accel/tcg/trace.c
GEN accel/kvm/trace.c
GEN nbd/trace.c
GEN scsi/trace.c
GEN config-all-devices.mak
mkdir -p dtc/libfdt
mkdir -p dtc/tests
GEN ui/input-keymap-linux-to-qcode.c
GEN ui/input-keymap-qcode-to-qnum.c
GEN ui/input-keymap-qcode-to-linux.c
GEN ui/input-keymap-qnum-to-qcode.c
CC cs.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/dumptrees.c
CC utils.o
CC SStream.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/trees.S
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/testutils.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/value-labels.c
CC MCInstrDesc.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/asm_tree_dump.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/truncated_property.c
CC MCRegisterInfo.o
CC arch/ARM/ARMInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/overlay_bad_fixup.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/check_path.c
CC arch/ARM/ARMDisassembler.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/overlay.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/subnode_iterate.c
CC arch/ARM/ARMMapping.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/property_iterate.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/path_offset_aliases.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/add_subnode_with_nops.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/dtb_reverse.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/integer-expressions.c
CC arch/ARM/ARMModule.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/dtbs_equal_ordered.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/utilfdt_test.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/dtbs_equal_unordered.c
CC arch/AArch64/AArch64BaseInfo.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/extra-terminating-null.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/phandle_format.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/boot-cpuid.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/path-references.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/references.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/incbin.c
CC arch/AArch64/AArch64Disassembler.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/string_escapes.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/propname_escapes.c
CC arch/AArch64/AArch64InstPrinter.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/appendprop2.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/appendprop1.c
CC arch/AArch64/AArch64Mapping.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/del_node.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/del_property.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/setprop.c
CC arch/AArch64/AArch64Module.o
CC arch/Mips/MipsDisassembler.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/set_name.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/rw_tree1.c
CC arch/Mips/MipsInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/open_pack.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/nopulate.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/mangle-layout.c
CC arch/Mips/MipsMapping.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/move_and_save.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/nop_node.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/get_alias.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/addr_size_cells.c
CC arch/PowerPC/PPCInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/notfound.c
CC arch/PowerPC/PPCDisassembler.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/sized_cells.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/setprop_inplace.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/char_literal.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/stringlist.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/nop_property.c
CC arch/Mips/MipsModule.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/node_offset_by_compatible.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/sw_tree1.c
CC arch/PowerPC/PPCMapping.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/node_check_compatible.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/parent_offset.c
CC arch/Sparc/SparcDisassembler.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/node_offset_by_phandle.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/node_offset_by_prop_value.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/get_phandle.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/get_path.c
CC arch/PowerPC/PPCModule.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/supernode_atdepth_offset.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/get_name.c
CC arch/Sparc/SparcInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/subnode_offset.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/path_offset.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt_overlay.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/root_node.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/find_property.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt_addresses.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/getprop.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/tests/get_mem_rsv.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt_strerror.c
CC arch/Sparc/SparcMapping.o
CC arch/Sparc/SparcModule.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt_empty_tree.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt_rw.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt_sw.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt_ro.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/util.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/fdtput.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/libfdt/fdt_wip.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/fdtdump.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/fdtoverlay.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/fdtget.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/srcpos.c
LEX convert-dtsv0-lexer.lex.c
BISON dtc-parser.tab.c
CC arch/SystemZ/SystemZDisassembler.o
CC arch/SystemZ/SystemZInstPrinter.o
LEX dtc-lexer.lex.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/treesource.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/fstree.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/livetree.c
CC arch/SystemZ/SystemZMapping.o
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/flattree.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/dtc.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/checks.c
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/data.c
CC arch/SystemZ/SystemZMCTargetDesc.o
CC arch/SystemZ/SystemZModule.o
CC arch/X86/X86DisassemblerDecoder.o
CC arch/X86/X86Disassembler.o
CC arch/X86/X86IntelInstPrinter.o
CC arch/X86/X86ATTInstPrinter.o
CC arch/X86/X86Mapping.o
CC arch/X86/X86Module.o
CC arch/XCore/XCoreInstPrinter.o
CC arch/XCore/XCoreDisassembler.o
CC arch/XCore/XCoreMapping.o
CC arch/XCore/XCoreModule.o
CC MCInst.o
DEP convert-dtsv0-lexer.lex.c
DEP dtc-parser.tab.c
DEP dtc-lexer.lex.c
CHK version_gen.h
UPD version_gen.h
DEP /var/tmp/patchew-tester-tmp-r7vd2rsz/src/dtc/util.c
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_overlay.o
CC libfdt/fdt_addresses.o
AR libfdt/libfdt.a
ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
AR libcapstone.a
ar: creating /var/tmp/patchew-tester-tmp-r7vd2rsz/src/build/capstone/libcapstone.a
mkdir -p dtc/libfdt
mkdir -p dtc/tests
make[1]: `/var/tmp/patchew-tester-tmp-r7vd2rsz/src/build/capstone/libcapstone.a' is up to date.
CC tests/qemu-iotests/socket_scm_helper.o
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qmp-marshal.c
CC qmp-introspect.o
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/string-input-visitor.o
CC qapi/qmp-dispatch.o
CC qapi/qmp-registry.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-clone-visitor.o
CC qobject/qstring.o
CC qobject/qnum.o
CC qobject/qdict.o
CC qobject/qnull.o
CC qobject/qlist.o
CC qobject/qbool.o
CC qobject/qlit.o
CC qobject/qjson.o
CC qapi/qapi-util.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
CC trace/control.o
CC trace/qmp.o
CC util/cutils.o
CC util/unicode.o
CC util/osdep.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/aio-posix.o
CC util/qemu-timer.o
CC util/compatfd.o
CC util/mmap-alloc.o
CC util/event_notifier-posix.o
CC util/main-loop.o
CC util/iohandler.o
CC util/oslib-posix.o
CC util/qemu-openpty.o
CC util/qemu-thread-posix.o
CC util/memfd.o
CC util/module.o
CC util/host-utils.o
CC util/path.o
CC util/envlist.o
CC util/bitmap.o
CC util/hbitmap.o
CC util/bitops.o
CC util/fifo8.o
CC util/acl.o
CC util/cacheinfo.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/uri.o
CC util/qemu-sockets.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-ucontext.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/pagesize.o
CC util/qdist.o
CC util/log.o
CC util/qht.o
CC util/stats64.o
CC util/range.o
CC trace-root.o
CC util/systemd.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC chardev/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/misc/trace.o
CC hw/usb/trace.o
CC hw/scsi/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sparc64/trace.o
CC hw/sparc/trace.o
CC hw/sd/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC ui/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/ide/trace.o
CC audio/trace.o
CC hw/xen/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/mips/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC accel/tcg/trace.o
CC accel/kvm/trace.o
CC nbd/trace.o
CC scsi/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/is-daemonized.o
CC stubs/iothread-lock.o
CC stubs/linux-aio.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/change-state-handler.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/tpm.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/qmp_pc_dimm.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
CC stubs/pci-host-piix.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-server/main.o
CC qemu-nbd.o
CC blockjob.o
CC block.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qcow2-bitmap.o
CC block/qed.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/file-posix.o
CC block/linux-aio.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/write-threshold.o
CC block/dirty-bitmap.o
CC block/backup.o
CC block/replication.o
CC block/throttle.o
CC block/crypto.o
CC nbd/server.o
CC nbd/common.o
CC nbd/client.o
CC scsi/utils.o
CC scsi/pr-manager.o
CC scsi/pr-manager-helper.o
CC block/curl.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hmac.o
CC crypto/hash-nettle.o
CC crypto/hmac-nettle.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/tlscreds.o
CC crypto/cipher.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/secret.o
CC crypto/tlssession.o
CC crypto/random-gnutls.o
CC crypto/pbkdf.o
CC crypto/pbkdf-nettle.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/xts.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/net-listener.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
CC qemu-io.o
GEN qemu-img-cmds.h
CC fsdev/virtfs-proxy-helper.o
CC fsdev/9p-marshal.o
CC fsdev/9p-iov-marshal.o
CC scsi/qemu-pr-helper.o
CC qemu-bridge-helper.o
CC blockdev.o
CC blockdev-nbd.o
CC bootdevice.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC device_tree.o
CC vl.o
CC tpm.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/rng-random.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/hostmem-file.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC block/stream.o
CC chardev/msmouse.o
CC chardev/wctablet.o
CC chardev/testdev.o
CC disas/alpha.o
CC disas/arm.o
CC disas/cris.o
CXX disas/arm-a64.o
CC disas/hppa.o
CC disas/i386.o
CC disas/m68k.o
CC disas/microblaze.o
CC disas/mips.o
CC disas/nios2.o
CC disas/moxie.o
CC disas/ppc.o
CC disas/s390.o
CC disas/sh4.o
CC disas/sparc.o
CC disas/lm32.o
CC disas/xtensa.o
CXX disas/libvixl/vixl/utils.o
CXX disas/libvixl/vixl/compiler-intrinsics.o
CXX disas/libvixl/vixl/a64/instructions-a64.o
CXX disas/libvixl/vixl/a64/decoder-a64.o
CXX disas/libvixl/vixl/a64/disasm-a64.o
CC fsdev/qemu-fsdev.o
CC fsdev/qemu-fsdev-opts.o
CC fsdev/qemu-fsdev-throttle.o
CC fsdev/qemu-fsdev-dummy.o
CC hw/9pfs/9p.o
CC hw/9pfs/9p-util.o
CC hw/9pfs/9p-local.o
CC hw/9pfs/9p-xattr.o
CC hw/9pfs/9p-xattr-user.o
CC hw/9pfs/9p-posix-acl.o
CC hw/9pfs/coth.o
CC hw/9pfs/cofs.o
CC hw/9pfs/codir.o
CC hw/9pfs/cofile.o
CC hw/9pfs/coxattr.o
CC hw/9pfs/9p-synth.o
CC hw/9pfs/9p-handle.o
CC hw/9pfs/9p-proxy.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/tco.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/vmgenid.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/acpi/acpi-stub.o
CC hw/audio/sb16.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/cs4231.o
CC hw/audio/marvell_88w8618.o
CC hw/audio/milkymist-ac97.o
CC hw/audio/soundhw.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/escc.o
CC hw/char/pl011.o
CC hw/char/parallel.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/xilinx_uartlite.o
CC hw/char/cadence_uart.o
CC hw/char/cmsdk-apb-uart.o
CC hw/char/etraxfs_ser.o
CC hw/char/debugcon.o
CC hw/char/grlib_apbuart.o
CC hw/char/imx_serial.o
CC hw/char/lm32_juart.o
CC hw/char/lm32_uart.o
CC hw/char/milkymist-uart.o
CC hw/char/sclpconsole.o
CC hw/char/sclpconsole-lm.o
CC hw/core/qdev.o
CC hw/core/bus.o
CC hw/core/qdev-properties.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/nmi.o
CC hw/core/empty_slot.o
CC hw/core/stream.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/loader-fit.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/cpu/core.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/g364fb.o
CC hw/display/jazz_led.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vga-isa-mm.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/framebuffer.o
CC hw/display/exynos4210_fimd.o
CC hw/display/milkymist-vgafb.o
CC hw/display/tc6393xb.o
CC hw/dma/puv3_dma.o
CC hw/dma/rc4030.o
CC hw/dma/pl330.o
CC hw/dma/pl080.o
CC hw/dma/i82374.o
CC hw/dma/i8257.o
CC hw/dma/xilinx_axidma.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/dma/etraxfs_dma.o
CC hw/dma/sparc32_dma.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/puv3_gpio.o
CC hw/gpio/zaurus.o
CC hw/gpio/mpc8xxx.o
CC hw/gpio/gpio_key.o
CC hw/i2c/smbus.o
CC hw/i2c/core.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/cmd646.o
CC hw/ide/mmio.o
CC hw/ide/macio.o
CC hw/ide/via.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/ide/ahci-allwinner.o
CC hw/ide/sii3112.o
CC hw/input/adb.o
CC hw/input/adb-mouse.o
CC hw/input/adb-kbd.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input-host.o
CC hw/intc/heathrow_pic.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/puv3_intc.o
CC hw/intc/xilinx_intc.o
CC hw/intc/etraxfs_pic.o
CC hw/intc/imx_avic.o
CC hw/intc/lm32_pic.o
CC hw/intc/realview_gic.o
CC hw/intc/slavio_intctl.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/openpic.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/isa/i82378.o
CC hw/isa/pc87312.o
CC hw/isa/piix4.o
CC hw/isa/vt82c686.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/tmp421.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/edu.o
CC hw/misc/unimp.o
CC hw/misc/vmcoreinfo.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/misc/puv3_pm.o
CC hw/misc/macio/macio.o
CC hw/misc/macio/cuda.o
CC hw/misc/macio/mac_dbdma.o
CC hw/net/dp8393x.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_rx_pkt.o
CC hw/net/net_tx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/opencores_eth.o
CC hw/net/xgmac.o
CC hw/net/mipsnet.o
CC hw/net/xilinx_axienet.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/stellaris_enet.o
CC hw/net/cadence_gem.o
CC hw/net/lance.o
CC hw/net/sunhme.o
CC hw/net/ftgmac100.o
CC hw/net/sungem.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/ds1225y.o
CC hw/nvram/eeprom_at24c.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/nvram/mac_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pcie_pci_bridge.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-bridge/dec.o
CC hw/pci-host/pam.o
CC hw/pci-host/prep.o
CC hw/pci-host/grackle.o
CC hw/pci-host/uninorth.o
CC hw/pci-host/ppce500.o
CC hw/pci-host/versatile.o
CC hw/pci-host/apb.o
CC hw/pci-host/bonito.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci-host/xilinx-pcie.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios-stub.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/ssi/xilinx_spi.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/ssi/mss-spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/armv7m_systick.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/m48t59-isa.o
CC hw/timer/pl031.o
CC hw/timer/m48t59.o
CC hw/timer/puv3_ost.o
CC hw/timer/twl92230.o
CC hw/timer/xilinx_timer.o
CC hw/timer/etraxfs_timer.o
CC hw/timer/slavio_timer.o
CC hw/timer/grlib_gptimer.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/lm32_timer.o
CC hw/timer/milkymist-sysctl.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/aspeed_timer.o
CC hw/timer/sun4v-rtc.o
CC hw/timer/cmsdk-apb-timer.o
CC hw/timer/mss-timer.o
CC hw/tpm/tpm_util.o
CC hw/tpm/tpm_tis.o
CC hw/tpm/tpm_emulator.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/desc.o
CC hw/usb/libhw.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-xhci-nec.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/host-libusb.o
CC hw/usb/dev-mtp.o
CC hw/usb/host-legacy.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/virtio/vhost-stub.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC hw/watchdog/wdt_diag288.o
CC hw/watchdog/wdt_aspeed.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/channel.o
CC migration/savevm.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/vmstate-types.o
CC migration/page_cache.o
CC migration/qemu-file.o
CC migration/global_state.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/rdma.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/l2tpv3.o
CC net/vhost-user.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC net/tap.o
CC qom/cpu.o
CC net/tap-linux.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
CC replay/replay-net.o
CC replay/replay-audio.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip6_output.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_input.o
CC slirp/tcp_output.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/udp6.o
CC slirp/bootp.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC slirp/ncsi.o
CC ui/keymaps.o
CC ui/console.o
CC ui/cursor.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-legacy.o
CC ui/input-linux.o
CC ui/sdl_zoom.o
CC ui/sdl.o
CC ui/x_keymap.o
CC ui/curses.o
CC ui/vnc-enc-zlib.o
CC ui/vnc.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-auth-sasl.o
CC ui/vnc-ws.o
CC ui/vnc-jobs.o
CC ui/gtk.o
CC chardev/char.o
CC chardev/char-fd.o
CC chardev/char-fe.o
CC chardev/char-file.o
CC chardev/char-io.o
CC chardev/char-mux.o
CC chardev/char-null.o
CC chardev/char-parallel.o
CC chardev/char-pipe.o
CC chardev/char-pty.o
CC chardev/char-ringbuf.o
CC chardev/char-serial.o
CC chardev/char-socket.o
CC chardev/char-udp.o
CC chardev/char-stdio.o
CCAS spapr-rtas/spapr-rtas.o
LINK tests/qemu-iotests/socket_scm_helper
CC qga/commands.o
Building spapr-rtas/spapr-rtas.img
CC qga/guest-agent-command-state.o
CC qga/main.o
CC qga/commands-posix.o
Building spapr-rtas/spapr-rtas.bin
CC qga/qapi-generated/qga-qapi-types.o
CC qga/channel-posix.o
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qmp-marshal.o
CC qemu-img.o
rm spapr-rtas.img spapr-rtas.o
AR libqemuutil.a
LINK qemu-ga
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
LINK qemu-img
LINK qemu-io
LINK fsdev/virtfs-proxy-helper
LINK scsi/qemu-pr-helper
LINK qemu-bridge-helper
GEN armeb-linux-user/config-target.h
GEN m68k-linux-user/config-target.h
GEN alpha-linux-user/config-target.h
GEN or1k-linux-user/config-target.h
CC armeb-linux-user/exec.o
CC armeb-linux-user/tcg/tcg.o
CC armeb-linux-user/tcg/tcg-op.o
GEN arm-linux-user/config-target.h
CC armeb-linux-user/tcg/tcg-op-vec.o
GEN mipsel-linux-user/config-target.h
GEN cris-linux-user/config-target.h
CC alpha-linux-user/tcg/tcg-op.o
CC alpha-linux-user/tcg/tcg.o
GEN aarch64_be-linux-user/config-target.h
CC alpha-linux-user/exec.o
CC armeb-linux-user/tcg/tcg-op-gvec.o
CC alpha-linux-user/tcg/tcg-op-vec.o
CC armeb-linux-user/tcg/optimize.o
CC armeb-linux-user/fpu/softfloat.o
CC armeb-linux-user/tcg/tcg-common.o
CC alpha-linux-user/tcg/tcg-common.o
CC alpha-linux-user/tcg/tcg-op-gvec.o
CC alpha-linux-user/tcg/optimize.o
CC alpha-linux-user/fpu/softfloat.o
CC armeb-linux-user/disas.o
GEN armeb-linux-user/gdbstub-xml.c
CC alpha-linux-user/disas.o
CC or1k-linux-user/exec.o
GEN microblazeel-linux-user/config-target.h
CC alpha-linux-user/gdbstub.o
CC alpha-linux-user/thunk.o
CC armeb-linux-user/gdbstub.o
CC or1k-linux-user/tcg/tcg.o
CC alpha-linux-user/accel/stubs/hax-stub.o
CC armeb-linux-user/accel/stubs/hax-stub.o
CC armeb-linux-user/accel/stubs/hvf-stub.o
CC armeb-linux-user/thunk.o
GEN ppc64abi32-linux-user/config-target.h
CC armeb-linux-user/accel/stubs/kvm-stub.o
GEN ppc64-linux-user/config-target.h
CC alpha-linux-user/accel/stubs/kvm-stub.o
CC m68k-linux-user/tcg/tcg-op.o
CC m68k-linux-user/exec.o
CC or1k-linux-user/tcg/tcg-op-vec.o
CC arm-linux-user/exec.o
CC m68k-linux-user/tcg/tcg.o
CC arm-linux-user/tcg/tcg.o
CC armeb-linux-user/accel/tcg/tcg-runtime.o
CC cris-linux-user/exec.o
CC s390x-linux-user/gen-features
CC m68k-linux-user/tcg/tcg-op-gvec.o
GEN s390x-linux-user/config-target.h
CC alpha-linux-user/accel/tcg/tcg-runtime.o
CC m68k-linux-user/tcg/tcg-op-vec.o
CC alpha-linux-user/accel/stubs/hvf-stub.o
CC or1k-linux-user/tcg/tcg-op-gvec.o
CC or1k-linux-user/tcg/tcg-op.o
CC mipsel-linux-user/exec.o
CC armeb-linux-user/accel/tcg/tcg-runtime-gvec.o
CC aarch64_be-linux-user/exec.o
CC microblazeel-linux-user/exec.o
GEN mips64-linux-user/config-target.h
GEN hppa-linux-user/config-target.h
CC ppc64abi32-linux-user/exec.o
CC cris-linux-user/tcg/tcg.o
GEN aarch64-linux-user/config-target.h
CC ppc64-linux-user/exec.o
GEN mips64el-linux-user/config-target.h
GEN microblaze-linux-user/config-target.h
GEN sh4eb-linux-user/config-target.h
GEN sparc32plus-linux-user/config-target.h
CC mips64-linux-user/exec.o
CC microblaze-linux-user/exec.o
CC hppa-linux-user/exec.o
CC aarch64-linux-user/exec.o
CC sh4eb-linux-user/exec.o
GEN ppc64le-linux-user/config-target.h
GEN mips-linux-user/config-target.h
CC mips64el-linux-user/exec.o
CC sparc32plus-linux-user/exec.o
GEN ppc-linux-user/config-target.h
GEN tilegx-linux-user/config-target.h
GEN x86_64-linux-user/config-target.h
GEN mipsn32el-linux-user/config-target.h
GEN mipsn32-linux-user/config-target.h
CC ppc64le-linux-user/exec.o
GEN sh4-linux-user/config-target.h
CC mips-linux-user/exec.o
GEN i386-linux-user/config-target.h
GEN nios2-linux-user/config-target.h
GEN s390x-linux-user/gen-features.h
CC x86_64-linux-user/exec.o
CC mipsn32el-linux-user/exec.o
CC mipsn32-linux-user/exec.o
CC tilegx-linux-user/exec.o
CC ppc-linux-user/exec.o
CC i386-linux-user/exec.o
CC s390x-linux-user/exec.o
CC nios2-linux-user/exec.o
CC sh4-linux-user/exec.o
GEN sparc-linux-user/config-target.h
GEN sparc64-linux-user/config-target.h
CC sparc-linux-user/exec.o
CC x86_64-linux-user/tcg/tcg.o
CC sparc64-linux-user/exec.o
CC cris-linux-user/tcg/tcg-op.o
CC mips64el-linux-user/tcg/tcg.o
CC cris-linux-user/tcg/tcg-op-vec.o
CC mips-linux-user/tcg/tcg.o
GEN cris-softmmu/hmp-commands.h
GEN nios2-softmmu/hmp-commands.h
GEN nios2-softmmu/hmp-commands-info.h
CC sparc64-linux-user/tcg/tcg.o
CC alpha-linux-user/accel/tcg/tcg-runtime-gvec.o
GEN or1k-softmmu/hmp-commands.h
CC i386-linux-user/tcg/tcg.o
CC arm-linux-user/tcg/tcg-op.o
GEN lm32-softmmu/hmp-commands.h
GEN nios2-softmmu/config-target.h
GEN microblazeel-softmmu/hmp-commands.h
GEN m68k-softmmu/hmp-commands.h
GEN moxie-softmmu/hmp-commands.h
CC nios2-softmmu/exec.o
GEN unicore32-softmmu/hmp-commands.h
CC nios2-softmmu/tcg/tcg.o
GEN tricore-softmmu/hmp-commands.h
GEN alpha-softmmu/hmp-commands.h
CC ppc64le-linux-user/tcg/tcg.o
GEN cris-softmmu/hmp-commands-info.h
GEN or1k-softmmu/hmp-commands-info.h
GEN xtensaeb-softmmu/hmp-commands.h
GEN xtensa-softmmu/hmp-commands.h
GEN or1k-softmmu/config-target.h
GEN microblaze-softmmu/hmp-commands.h
CC mipsel-linux-user/tcg/tcg.o
CC mips64el-linux-user/tcg/tcg-op.o
CC microblazeel-linux-user/tcg/tcg.o
GEN s390x-softmmu/hmp-commands.h
GEN mips64-softmmu/hmp-commands.h
CC mipsn32el-linux-user/tcg/tcg.o
GEN lm32-softmmu/hmp-commands-info.h
GEN moxie-softmmu/hmp-commands-info.h
CC or1k-softmmu/exec.o
GEN m68k-softmmu/hmp-commands-info.h
GEN microblazeel-softmmu/hmp-commands-info.h
GEN cris-softmmu/config-target.h
CC sparc-linux-user/tcg/tcg.o
GEN sparc-softmmu/hmp-commands.h
GEN tricore-softmmu/hmp-commands-info.h
GEN s390x-softmmu/hmp-commands-info.h
CC mips64-linux-user/tcg/tcg.o
CC arm-linux-user/tcg/tcg-op-vec.o
GEN lm32-softmmu/config-target.h
CC tilegx-linux-user/tcg/tcg.o
CC sh4eb-linux-user/tcg/tcg.o
CC cris-softmmu/exec.o
GEN microblazeel-softmmu/config-target.h
CC lm32-softmmu/exec.o
GEN moxie-softmmu/config-target.h
CC microblaze-linux-user/tcg/tcg.o
CC nios2-softmmu/tcg/tcg-op.o
CC mipsn32-linux-user/tcg/tcg.o
CC ppc64abi32-linux-user/tcg/tcg.o
GEN xtensaeb-softmmu/hmp-commands-info.h
CC aarch64_be-linux-user/tcg/tcg.o
GEN sparc-softmmu/hmp-commands-info.h
GEN microblaze-softmmu/hmp-commands-info.h
GEN unicore32-softmmu/hmp-commands-info.h
GEN alpha-softmmu/hmp-commands-info.h
CC moxie-softmmu/exec.o
GEN microblaze-softmmu/config-target.h
GEN tricore-softmmu/config-target.h
CC armeb-linux-user/accel/tcg/cpu-exec.o
GEN m68k-softmmu/config-target.h
CC microblazeel-softmmu/exec.o
CC sh4-linux-user/tcg/tcg.o
CC hppa-linux-user/tcg/tcg.o
CC s390x-softmmu/gen-features
GEN mips64-softmmu/hmp-commands-info.h
CC alpha-linux-user/accel/tcg/cpu-exec.o
GEN xtensa-softmmu/hmp-commands-info.h
GEN sh4eb-softmmu/hmp-commands.h
CC nios2-linux-user/tcg/tcg.o
CC microblazeel-softmmu/tcg/tcg.o
CC armeb-linux-user/accel/tcg/cpu-exec-common.o
GEN sh4-softmmu/hmp-commands.h
CC m68k-softmmu/exec.o
CC tricore-softmmu/exec.o
CC nios2-linux-user/tcg/tcg-op.o
CC sparc32plus-linux-user/tcg/tcg.o
CC sparc64-linux-user/tcg/tcg-op.o
GEN mips64-softmmu/config-target.h
CC ppc-linux-user/tcg/tcg.o
CC nios2-softmmu/tcg/tcg-op-vec.o
CC ppc64-linux-user/tcg/tcg.o
CC ppc64-linux-user/tcg/tcg-op.o
GEN xtensaeb-softmmu/config-target.h
CC mips64-softmmu/exec.o
GEN unicore32-softmmu/config-target.h
GEN ppcemb-softmmu/hmp-commands.h
CC microblaze-softmmu/exec.o
GEN sparc64-softmmu/hmp-commands.h
GEN ppc64-softmmu/hmp-commands.h
CC xtensaeb-softmmu/exec.o
GEN sparc64-softmmu/hmp-commands-info.h
CC aarch64-linux-user/tcg/tcg.o
GEN sparc-softmmu/config-target.h
GEN alpha-softmmu/config-target.h
CC sparc32plus-linux-user/tcg/tcg-op.o
CC unicore32-softmmu/exec.o
GEN ppc-softmmu/hmp-commands.h
CC mipsn32el-linux-user/tcg/tcg-op.o
GEN xtensa-softmmu/config-target.h
CC alpha-softmmu/exec.o
CC sparc64-linux-user/tcg/tcg-op-vec.o
GEN arm-softmmu/hmp-commands.h
CC sparc-softmmu/exec.o
GEN s390x-softmmu/config-target.h
CC xtensa-softmmu/exec.o
CC sparc32plus-linux-user/tcg/tcg-op-vec.o
GEN s390x-softmmu/gen-features.h
GEN i386-softmmu/hmp-commands.h
GEN ppc-softmmu/hmp-commands-info.h
GEN sh4-softmmu/hmp-commands-info.h
GEN sh4eb-softmmu/hmp-commands-info.h
CC s390x-linux-user/tcg/tcg.o
GEN ppcemb-softmmu/hmp-commands-info.h
GEN sparc64-softmmu/config-target.h
CC s390x-softmmu/exec.o
CC sparc64-softmmu/exec.o
GEN sh4-softmmu/config-target.h
CC s390x-softmmu/tcg/tcg.o
GEN ppc64-softmmu/hmp-commands-info.h
CC microblaze-linux-user/tcg/tcg-op.o
CC xtensaeb-softmmu/tcg/tcg.o
GEN x86_64-softmmu/hmp-commands.h
GEN sh4eb-softmmu/config-target.h
GEN ppc-softmmu/config-target.h
CC sh4eb-softmmu/exec.o
CC sh4-softmmu/exec.o
GEN x86_64-softmmu/hmp-commands-info.h
GEN ppcemb-softmmu/config-target.h
GEN i386-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/hmp-commands.h
CC ppc-softmmu/exec.o
GEN mips64el-softmmu/hmp-commands.h
CC ppcemb-softmmu/exec.o
GEN mipsel-softmmu/hmp-commands.h
GEN arm-softmmu/hmp-commands-info.h
GEN mips-softmmu/hmp-commands.h
GEN i386-softmmu/config-target.h
GEN ppc64-softmmu/config-target.h
CC aarch64-linux-user/tcg/tcg-op.o
CC microblaze-softmmu/tcg/tcg.o
CC i386-softmmu/exec.o
GEN x86_64-softmmu/config-target.h
CC ppc64-softmmu/exec.o
CC x86_64-softmmu/exec.o
GEN arm-softmmu/config-target.h
GEN aarch64-softmmu/hmp-commands-info.h
CC i386-linux-user/tcg/tcg-op.o
CC arm-softmmu/exec.o
GEN mipsel-softmmu/hmp-commands-info.h
GEN mips64el-softmmu/hmp-commands-info.h
GEN mips-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/config-target.h
GEN mips64el-softmmu/config-target.h
GEN mipsel-softmmu/config-target.h
CC aarch64-softmmu/exec.o
CC mipsn32-linux-user/tcg/tcg-op.o
CC mipsel-softmmu/exec.o
CC mips64el-softmmu/exec.o
GEN mips-softmmu/config-target.h
CC mips-softmmu/exec.o
CC nios2-linux-user/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC lm32-softmmu/tcg/tcg.o
CC mips64-softmmu/tcg/tcg.o
CC mips64-linux-user/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mips64el-linux-user/tcg/tcg-op-vec.o
CC ppc64-softmmu/tcg/tcg.o
CC mipsel-softmmu/tcg/tcg.o
CC aarch64-linux-user/tcg/tcg-op-vec.o
CC aarch64-linux-user/tcg/tcg-op-gvec.o
CC mipsn32el-linux-user/tcg/tcg-op-vec.o
CC hppa-linux-user/tcg/tcg-op.o
CC mipsn32-linux-user/tcg/tcg-op-vec.o
CC or1k-linux-user/tcg/tcg-common.o
CC microblaze-linux-user/tcg/tcg-op-vec.o
CC ppc64-linux-user/tcg/tcg-op-vec.o
CC hppa-linux-user/tcg/tcg-op-vec.o
CC microblazeel-softmmu/tcg/tcg-op.o
CC tilegx-linux-user/tcg/tcg-op.o
CC mipsn32-linux-user/tcg/tcg-op-gvec.o
CC ppc64abi32-linux-user/tcg/tcg-op.o
Preprocessed source stored into /tmp/ccVSpZ3R.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppc64abi32-linux-user/tcg/tcg-op-vec.o
CC alpha-softmmu/tcg/tcg.o
CC ppc-softmmu/tcg/tcg.o
CC sparc32plus-linux-user/tcg/tcg-op-gvec.o
CC microblazeel-softmmu/tcg/tcg-op-vec.o
CC ppcemb-softmmu/tcg/tcg.o
CC mips64-linux-user/tcg/tcg-op-vec.o
CC sparc-linux-user/tcg/tcg-op.o
CC m68k-softmmu/tcg/tcg.o
CC m68k-softmmu/tcg/tcg-op.o
CC x86_64-linux-user/tcg/tcg-op.o
CC or1k-linux-user/tcg/optimize.o
Preprocessed source stored into /tmp/ccWQjwp5.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC m68k-softmmu/tcg/tcg-op-vec.o
CC x86_64-softmmu/tcg/tcg.o
CC s390x-softmmu/tcg/tcg-op.o
CC lm32-softmmu/tcg/tcg-op.o
CC i386-linux-user/tcg/tcg-op-vec.o
CC sh4eb-linux-user/tcg/tcg-op.o
CC x86_64-softmmu/tcg/tcg-op.o
CC moxie-softmmu/tcg/tcg.o
CC sparc32plus-linux-user/tcg/tcg-common.o
CC cris-linux-user/tcg/tcg-op-gvec.o
CC sh4eb-softmmu/tcg/tcg.o
CC alpha-softmmu/tcg/tcg-op.o
CC microblazeel-linux-user/tcg/tcg-op.o
CC arm-linux-user/tcg/tcg-op-gvec.o
CC i386-softmmu/tcg/tcg.o
CC m68k-linux-user/tcg/tcg-common.o
CC mips-linux-user/tcg/tcg-op.o
CC nios2-linux-user/tcg/tcg-op-gvec.o
CC microblazeel-linux-user/tcg/tcg-op-vec.o
CC mips-linux-user/tcg/tcg-op-vec.o
CC mips64el-linux-user/tcg/tcg-op-gvec.o
CC mips64el-linux-user/tcg/tcg-common.o
CC sparc-linux-user/tcg/tcg-op-vec.o
CC sparc64-linux-user/tcg/tcg-op-gvec.o
CC mipsel-softmmu/tcg/tcg-op.o
CC sparc-linux-user/tcg/tcg-op-gvec.o
CC mipsel-linux-user/tcg/tcg-op.o
CC alpha-softmmu/tcg/tcg-op-vec.o
CC alpha-softmmu/tcg/tcg-op-gvec.o
CC ppcemb-softmmu/tcg/tcg-op.o
CC sh4-linux-user/tcg/tcg-op.o
CC m68k-linux-user/tcg/optimize.o
CC aarch64_be-linux-user/tcg/tcg-op.o
CC cris-softmmu/tcg/tcg.o
CC aarch64-softmmu/tcg/tcg.o
CC mipsel-softmmu/tcg/tcg-op-vec.o
CC mipsel-softmmu/tcg/tcg-op-gvec.o
CC microblaze-linux-user/tcg/tcg-op-gvec.o
CC aarch64-softmmu/tcg/tcg-op.o
CC s390x-linux-user/tcg/tcg-op.o
CC ppc64le-linux-user/tcg/tcg-op.o
CC ppc64-linux-user/tcg/tcg-op-gvec.o
CC ppcemb-softmmu/tcg/tcg-op-vec.o
CC or1k-linux-user/fpu/softfloat.o
CC mips64el-linux-user/tcg/optimize.o
CC xtensaeb-softmmu/tcg/tcg-op.o
CC ppc-softmmu/tcg/tcg-op.o
CC ppc64abi32-linux-user/tcg/tcg-op-gvec.o
CC x86_64-linux-user/tcg/tcg-op-vec.o
CC microblazeel-linux-user/tcg/tcg-op-gvec.o
CC lm32-softmmu/tcg/tcg-op-vec.o
CC ppc-linux-user/tcg/tcg-op.o
CC i386-softmmu/tcg/tcg-op.o
CC microblaze-linux-user/tcg/tcg-common.o
CC ppc64-linux-user/tcg/tcg-common.o
CC mips-linux-user/tcg/tcg-op-gvec.o
CC aarch64-linux-user/tcg/tcg-common.o
CC i386-linux-user/tcg/tcg-op-gvec.o
CC tricore-softmmu/tcg/tcg.o
CC mipsn32-linux-user/tcg/tcg-common.o
CC m68k-linux-user/fpu/softfloat.o
CC microblaze-softmmu/tcg/tcg-op.o
CC aarch64_be-linux-user/tcg/tcg-op-vec.o
CC mipsn32el-linux-user/tcg/tcg-op-gvec.o
make: *** [subdir-alpha-linux-user] Error 2
make: *** Waiting for unfinished jobs....
CC nios2-softmmu/tcg/tcg-op-gvec.o
CC mips-softmmu/tcg/tcg.o
CC aarch64-linux-user/tcg/optimize.o
CC nios2-linux-user/tcg/tcg-common.o
CC sparc-linux-user/tcg/tcg-common.o
CC sh4-softmmu/tcg/tcg.o
CC xtensa-softmmu/tcg/tcg.o
make: *** [subdir-armeb-linux-user] Error 2
CC xtensa-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/tcg/tcg-op-vec.o
CC sparc64-softmmu/tcg/tcg.o
CC ppc64-softmmu/tcg/tcg-op.o
CC arm-softmmu/tcg/tcg.o
CC sh4-softmmu/tcg/tcg-op.o
CC mips-softmmu/tcg/tcg-op.o
CC s390x-softmmu/tcg/tcg-op-vec.o
CC mips64-linux-user/tcg/tcg-op-gvec.o
CC microblazeel-softmmu/tcg/tcg-op-gvec.o
CC or1k-softmmu/tcg/tcg.o
CC ppc64abi32-linux-user/tcg/tcg-common.o
CC aarch64-linux-user/fpu/softfloat.o
CC ppc64le-linux-user/tcg/tcg-op-vec.o
CC microblazeel-linux-user/tcg/tcg-common.o
CC arm-linux-user/tcg/tcg-common.o
CC mips64el-softmmu/tcg/tcg.o
CC arm-linux-user/tcg/optimize.o
CC alpha-softmmu/tcg/tcg-common.o
CC m68k-linux-user/disas.o
CC sparc-softmmu/tcg/tcg.o
CC hppa-linux-user/tcg/tcg-op-gvec.o
CC unicore32-softmmu/tcg/tcg.o
CC ppc-linux-user/tcg/tcg-op-vec.o
CC mips-softmmu/tcg/tcg-op-vec.o
CC arm-linux-user/fpu/softfloat.o
CC sparc32plus-linux-user/tcg/optimize.o
CC sparc32plus-linux-user/fpu/softfloat.o
GEN m68k-linux-user/gdbstub-xml.c
CC arm-softmmu/tcg/tcg-op.o
CC sh4eb-linux-user/tcg/tcg-op-vec.o
CC arm-linux-user/disas.o
CC s390x-linux-user/tcg/tcg-op-vec.o
CC microblazeel-softmmu/tcg/tcg-common.o
CC microblaze-linux-user/tcg/optimize.o
CC tilegx-linux-user/tcg/tcg-op-vec.o
CC sparc-linux-user/tcg/optimize.o
CC alpha-softmmu/tcg/optimize.o
CC xtensa-softmmu/tcg/tcg-op-vec.o
CC cris-linux-user/tcg/tcg-common.o
CC arm-softmmu/tcg/tcg-op-vec.o
CC microblazeel-softmmu/tcg/optimize.o
CC cris-softmmu/tcg/tcg-op.o
CC ppcemb-softmmu/tcg/tcg-op-gvec.o
CC aarch64_be-linux-user/tcg/tcg-op-gvec.o
CC ppc64abi32-linux-user/tcg/optimize.o
CC mips64-softmmu/tcg/tcg-op.o
CC sh4-softmmu/tcg/tcg-op-vec.o
CC mips64el-softmmu/tcg/tcg-op.o
CC sh4-linux-user/tcg/tcg-op-vec.o
CC ppcemb-softmmu/tcg/tcg-common.o
CC tricore-softmmu/tcg/tcg-op.o
CC cris-softmmu/tcg/tcg-op-vec.o
CC mips-linux-user/tcg/tcg-common.o
CC ppcemb-softmmu/tcg/optimize.o
CC lm32-softmmu/tcg/tcg-op-gvec.o
GEN arm-linux-user/gdbstub-xml.c
CC arm-linux-user/gdbstub.o
CC arm-linux-user/thunk.o
CC tilegx-linux-user/tcg/tcg-op-gvec.o
CC mipsn32-linux-user/tcg/optimize.o
CC mipsel-softmmu/tcg/tcg-common.o
CC microblaze-softmmu/tcg/tcg-op-vec.o
CC ppc-softmmu/tcg/tcg-op-vec.o
CC or1k-linux-user/disas.o
CC lm32-softmmu/tcg/tcg-common.o
CC xtensaeb-softmmu/tcg/tcg-op-vec.o
CC sparc64-linux-user/tcg/tcg-common.o
CC cris-softmmu/tcg/tcg-op-gvec.o
CC s390x-softmmu/tcg/tcg-op-gvec.o
CC hppa-linux-user/tcg/tcg-common.o
CC mipsel-softmmu/tcg/optimize.o
CC sparc-softmmu/tcg/tcg-op.o
CC xtensa-softmmu/tcg/tcg-op-gvec.o
CC sh4eb-linux-user/tcg/tcg-op-gvec.o
CC tricore-softmmu/tcg/tcg-op-vec.o
CC microblaze-linux-user/fpu/softfloat.o
CC or1k-linux-user/gdbstub.o
CC tilegx-linux-user/tcg/tcg-common.o
CC s390x-softmmu/tcg/tcg-common.o
CC nios2-linux-user/tcg/optimize.o
CC alpha-softmmu/fpu/softfloat.o
CC mipsel-softmmu/fpu/softfloat.o
CC sparc64-linux-user/tcg/optimize.o
CC cris-linux-user/tcg/optimize.o
CC s390x-softmmu/tcg/optimize.o
CC mips64el-linux-user/fpu/softfloat.o
CC mips64-softmmu/tcg/tcg-op-vec.o
CC microblazeel-linux-user/tcg/optimize.o
CC sh4eb-softmmu/tcg/tcg-op.o
CC mipsel-softmmu/disas.o
CC m68k-softmmu/tcg/tcg-op-gvec.o
CC sparc64-softmmu/tcg/tcg-op.o
CC i386-softmmu/tcg/tcg-op-vec.o
CC x86_64-linux-user/tcg/tcg-op-gvec.o
CC sh4-linux-user/tcg/tcg-op-gvec.o
CC hppa-linux-user/tcg/optimize.o
CC hppa-linux-user/fpu/softfloat.o
CC mips64-softmmu/tcg/tcg-op-gvec.o
CC ppc-softmmu/tcg/tcg-op-gvec.o
CC i386-linux-user/tcg/tcg-common.o
CC s390x-linux-user/tcg/tcg-op-gvec.o
CC mipsel-softmmu/arch_init.o
CC sparc-linux-user/fpu/softfloat.o
CC xtensaeb-softmmu/tcg/tcg-op-gvec.o
CC sh4-softmmu/tcg/tcg-op-gvec.o
CC moxie-softmmu/tcg/tcg-op.o
CC mips64el-linux-user/disas.o
CC mipsel-linux-user/tcg/tcg-op-vec.o
CC mipsel-softmmu/cpus.o
CC i386-linux-user/tcg/optimize.o
CC xtensa-softmmu/tcg/tcg-common.o
CC microblazeel-linux-user/fpu/softfloat.o
CC s390x-softmmu/fpu/softfloat.o
CC ppc-softmmu/tcg/tcg-common.o
CC x86_64-softmmu/tcg/tcg-op-vec.o
CC x86_64-softmmu/tcg/tcg-op-gvec.o
CC mipsel-softmmu/monitor.o
CC sparc64-linux-user/fpu/softfloat.o
CC tricore-softmmu/tcg/tcg-op-gvec.o
CC or1k-softmmu/tcg/tcg-op.o
CC ppc64le-linux-user/tcg/tcg-op-gvec.o
CC sparc-linux-user/disas.o
CC microblaze-softmmu/tcg/tcg-op-gvec.o
CC x86_64-softmmu/tcg/tcg-common.o
CC or1k-softmmu/tcg/tcg-op-vec.o
CC mipsn32-linux-user/fpu/softfloat.o
CC ppc64abi32-linux-user/fpu/softfloat.o
CC mipsn32el-linux-user/tcg/tcg-common.o
CC ppc64abi32-linux-user/disas.o
CC sparc32plus-linux-user/disas.o
CC i386-linux-user/fpu/softfloat.o
CC sh4eb-softmmu/tcg/tcg-op-vec.o
CC ppc64-linux-user/tcg/optimize.o
CC mips64-softmmu/tcg/tcg-common.o
CC sh4-softmmu/tcg/tcg-common.o
CC aarch64-linux-user/disas.o
CC ppc64-softmmu/tcg/tcg-op-vec.o
CC hppa-linux-user/disas.o
CC nios2-softmmu/tcg/tcg-common.o
CC i386-linux-user/disas.o
CC cris-linux-user/fpu/softfloat.o
CC unicore32-softmmu/tcg/tcg-op.o
CC alpha-softmmu/disas.o
CC i386-softmmu/tcg/tcg-op-gvec.o
CC sh4eb-linux-user/tcg/tcg-common.o
CC mipsn32el-linux-user/tcg/optimize.o
CC mipsn32el-linux-user/fpu/softfloat.o
CC nios2-linux-user/fpu/softfloat.o
CC mips-linux-user/tcg/optimize.o
CC moxie-softmmu/tcg/tcg-op-vec.o
CC cris-linux-user/disas.o
CC mipsn32-linux-user/disas.o
CC m68k-softmmu/tcg/tcg-common.o
CC alpha-softmmu/arch_init.o
CC unicore32-softmmu/tcg/tcg-op-vec.o
CC cris-softmmu/tcg/tcg-common.o
CC mips-softmmu/tcg/tcg-op-gvec.o
CC tricore-softmmu/tcg/tcg-common.o
CC nios2-softmmu/tcg/optimize.o
GEN i386-linux-user/gdbstub-xml.c
CC arm-linux-user/accel/stubs/hax-stub.o
CC unicore32-softmmu/tcg/tcg-op-gvec.o
CC sh4eb-softmmu/tcg/tcg-op-gvec.o
CC mips-softmmu/tcg/tcg-common.o
CC tricore-softmmu/tcg/optimize.o
CC or1k-linux-user/thunk.o
CC aarch64-softmmu/tcg/tcg-op-gvec.o
CC ppc-linux-user/tcg/tcg-op-gvec.o
CC s390x-softmmu/disas.o
CC sparc64-softmmu/tcg/tcg-op-vec.o
GEN s390x-softmmu/gdbstub-xml.c
CC or1k-linux-user/accel/stubs/hax-stub.o
CC microblazeel-softmmu/fpu/softfloat.o
CC xtensaeb-softmmu/tcg/tcg-common.o
CC arm-softmmu/tcg/tcg-op-gvec.o
CC s390x-softmmu/arch_init.o
CC sh4eb-linux-user/tcg/optimize.o
CC ppc64-softmmu/tcg/tcg-op-gvec.o
CC m68k-linux-user/gdbstub.o
CC mipsel-linux-user/tcg/tcg-op-gvec.o
CC mips64-softmmu/tcg/optimize.o
CC ppc-softmmu/tcg/optimize.o
CC mips64-linux-user/tcg/tcg-common.o
CC ppc-softmmu/fpu/softfloat.o
CC x86_64-softmmu/tcg/optimize.o
CC ppc-softmmu/disas.o
CC i386-softmmu/tcg/tcg-common.o
CC mipsn32el-linux-user/disas.o
CC m68k-linux-user/thunk.o
CC or1k-softmmu/tcg/tcg-op-gvec.o
CC cris-softmmu/tcg/optimize.o
CC mips-softmmu/tcg/optimize.o
CC ppc64-softmmu/tcg/tcg-common.o
GEN aarch64-linux-user/gdbstub-xml.c
CC sparc64-linux-user/disas.o
CC microblaze-linux-user/disas.o
CC sparc64-softmmu/tcg/tcg-op-gvec.o
CC mips64-linux-user/tcg/optimize.o
CC or1k-linux-user/accel/stubs/hvf-stub.o
CC arm-linux-user/accel/stubs/hvf-stub.o
CC sparc64-linux-user/gdbstub.o
CC aarch64-softmmu/tcg/tcg-common.o
CC ppc64le-linux-user/tcg/tcg-common.o
CC mips64-linux-user/fpu/softfloat.o
CC unicore32-softmmu/tcg/tcg-common.o
CC sparc32plus-linux-user/gdbstub.o
CC mips-linux-user/fpu/softfloat.o
CC sparc64-linux-user/thunk.o
CC ppc-linux-user/tcg/tcg-common.o
CC sh4-linux-user/tcg/tcg-common.o
CC arm-linux-user/accel/stubs/kvm-stub.o
CC aarch64_be-linux-user/tcg/tcg-common.o
CC i386-linux-user/gdbstub.o
CC sh4-softmmu/tcg/optimize.o
CC m68k-softmmu/tcg/optimize.o
CC or1k-linux-user/accel/stubs/kvm-stub.o
CC microblazeel-softmmu/disas.o
CC microblazeel-softmmu/arch_init.o
CC sparc32plus-linux-user/thunk.o
CC arm-softmmu/tcg/tcg-common.o
CC xtensaeb-softmmu/tcg/optimize.o
CC mips64el-softmmu/tcg/tcg-op-vec.o
CC unicore32-softmmu/tcg/optimize.o
CC moxie-softmmu/tcg/tcg-op-gvec.o
CC sparc-linux-user/gdbstub.o
CC ppc-linux-user/tcg/optimize.o
CC hppa-linux-user/gdbstub.o
CC mips64-softmmu/fpu/softfloat.o
CC mips-softmmu/fpu/softfloat.o
CC m68k-linux-user/accel/stubs/hax-stub.o
CC s390x-linux-user/tcg/tcg-common.o
CC aarch64_be-linux-user/tcg/optimize.o
CC or1k-linux-user/accel/tcg/tcg-runtime.o
CC x86_64-softmmu/fpu/softfloat.o
CC mipsn32-linux-user/gdbstub.o
CC arm-softmmu/tcg/optimize.o
CC sh4-softmmu/fpu/softfloat.o
CC sparc32plus-linux-user/accel/stubs/hax-stub.o
CC ppcemb-softmmu/fpu/softfloat.o
CC sparc32plus-linux-user/accel/stubs/hvf-stub.o
CC cris-linux-user/gdbstub.o
CC sparc64-softmmu/tcg/tcg-common.o
CC hppa-linux-user/thunk.o
CC ppc64-linux-user/fpu/softfloat.o
CC ppc-linux-user/fpu/softfloat.o
CC ppcemb-softmmu/disas.o
CC or1k-linux-user/accel/tcg/tcg-runtime-gvec.o
CC tilegx-linux-user/tcg/optimize.o
CC lm32-softmmu/tcg/optimize.o
CC xtensa-softmmu/tcg/optimize.o
CC nios2-softmmu/fpu/softfloat.o
CC unicore32-softmmu/fpu/softfloat.o
CC microblaze-softmmu/tcg/tcg-common.o
CC x86_64-linux-user/tcg/tcg-common.o
CC cris-softmmu/fpu/softfloat.o
CC cris-linux-user/thunk.o
CC m68k-linux-user/accel/stubs/hvf-stub.o
CC sh4eb-linux-user/fpu/softfloat.o
CC mips-softmmu/disas.o
CC mips-softmmu/arch_init.o
CC ppc64-softmmu/tcg/optimize.o
CC aarch64-linux-user/gdbstub.o
CC aarch64_be-linux-user/fpu/softfloat.o
CC aarch64_be-linux-user/disas.o
CC mips64el-linux-user/gdbstub.o
CC cris-linux-user/accel/stubs/hax-stub.o
CC mips64-softmmu/disas.o
CC sparc-softmmu/tcg/tcg-op-vec.o
GEN ppc64abi32-linux-user/gdbstub-xml.c
CC m68k-linux-user/accel/stubs/kvm-stub.o
CC mips64el-softmmu/tcg/tcg-op-gvec.o
CC sh4-linux-user/tcg/optimize.o
CC hppa-linux-user/accel/stubs/hax-stub.o
GEN aarch64_be-linux-user/gdbstub-xml.c
CC cris-softmmu/disas.o
CC ppc64le-linux-user/tcg/optimize.o
CC cris-softmmu/arch_init.o
CC sparc32plus-linux-user/accel/stubs/kvm-stub.o
CC i386-linux-user/thunk.o
GEN ppcemb-softmmu/gdbstub-xml.c
CC ppc64abi32-linux-user/gdbstub.o
CC ppc64abi32-linux-user/thunk.o
CC ppc64abi32-linux-user/accel/stubs/hax-stub.o
CC mips64-softmmu/arch_init.o
CC s390x-softmmu/cpus.o
CC cris-softmmu/cpus.o
CC m68k-softmmu/fpu/softfloat.o
CC ppc64-linux-user/disas.o
CC m68k-linux-user/accel/tcg/tcg-runtime.o
CC x86_64-linux-user/tcg/optimize.o
CC microblazeel-linux-user/disas.o
CC ppc-linux-user/disas.o
CC unicore32-softmmu/disas.o
CC ppc64le-linux-user/fpu/softfloat.o
CC xtensaeb-softmmu/fpu/softfloat.o
CC microblaze-softmmu/tcg/optimize.o
CC sparc-linux-user/thunk.o
CC mips-softmmu/cpus.o
CC microblaze-softmmu/fpu/softfloat.o
CC arm-linux-user/accel/tcg/tcg-runtime.o
CC sparc-linux-user/accel/stubs/hax-stub.o
CC ppcemb-softmmu/arch_init.o
CC s390x-linux-user/tcg/optimize.o
CC m68k-softmmu/disas.o
CC tricore-softmmu/fpu/softfloat.o
CC mipsel-softmmu/gdbstub.o
CC aarch64-linux-user/thunk.o
CC sparc32plus-linux-user/accel/tcg/tcg-runtime.o
CC sh4-softmmu/disas.o
CC arm-linux-user/accel/tcg/tcg-runtime-gvec.o
CC x86_64-linux-user/fpu/softfloat.o
CC i386-linux-user/accel/stubs/hax-stub.o
CC sh4eb-softmmu/tcg/tcg-common.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC sparc-softmmu/tcg/tcg-op-gvec.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC s390x-softmmu/monitor.o
CC aarch64-softmmu/tcg/optimize.o
CC mips64-linux-user/disas.o
CC xtensa-softmmu/fpu/softfloat.o
CC m68k-linux-user/accel/tcg/tcg-runtime-gvec.o
CC mips-linux-user/disas.o
CC mipsel-linux-user/tcg/tcg-common.o
CC sh4-softmmu/arch_init.o
CC cris-linux-user/accel/stubs/hvf-stub.o
CC sh4-softmmu/cpus.o
CC sparc-softmmu/tcg/tcg-common.o
CC arm-softmmu/fpu/softfloat.o
CC ppc64-softmmu/fpu/softfloat.o
CC ppc64-softmmu/disas.o
CC moxie-softmmu/tcg/tcg-common.o
CC arm-linux-user/accel/tcg/cpu-exec.o
CC i386-linux-user/accel/stubs/hvf-stub.o
CC lm32-softmmu/fpu/softfloat.o
CC xtensaeb-softmmu/disas.o
CC sparc32plus-linux-user/accel/tcg/tcg-runtime-gvec.o
CC tilegx-linux-user/fpu/softfloat.o
CC nios2-linux-user/disas.o
CC moxie-softmmu/tcg/optimize.o
CC moxie-softmmu/fpu/softfloat.o
CC aarch64-linux-user/accel/stubs/hax-stub.o
CC mipsel-linux-user/tcg/optimize.o
CC ppcemb-softmmu/cpus.o
CC aarch64_be-linux-user/gdbstub.o
GEN ppc-linux-user/gdbstub-xml.c
CC ppc-linux-user/gdbstub.o
CC microblaze-linux-user/gdbstub.o
CC hppa-linux-user/accel/stubs/hvf-stub.o
CC aarch64_be-linux-user/thunk.o
CC sparc64-linux-user/accel/stubs/hax-stub.o
GEN ppc64-linux-user/gdbstub-xml.c
GEN ppc64-softmmu/gdbstub-xml.c
CC mipsel-softmmu/balloon.o
CC mipsel-softmmu/ioport.o
CC microblazeel-softmmu/cpus.o
CC nios2-softmmu/disas.o
CC mips64-linux-user/gdbstub.o
CC mips64-linux-user/thunk.o
CC alpha-softmmu/cpus.o
CC sh4-linux-user/fpu/softfloat.o
CC aarch64-linux-user/accel/stubs/hvf-stub.o
CC aarch64-linux-user/accel/stubs/kvm-stub.o
CC ppc-linux-user/thunk.o
GEN m68k-softmmu/gdbstub-xml.c
CC ppc-linux-user/accel/stubs/hax-stub.o
CC ppc-linux-user/accel/stubs/hvf-stub.o
CC moxie-softmmu/disas.o
CC sh4eb-softmmu/tcg/optimize.o
GEN ppc-softmmu/gdbstub-xml.c
CC i386-softmmu/tcg/optimize.o
CC alpha-softmmu/monitor.o
CC microblaze-softmmu/disas.o
CC sparc64-softmmu/tcg/optimize.o
CC sh4eb-softmmu/fpu/softfloat.o
CC hppa-linux-user/accel/stubs/kvm-stub.o
CC ppc-softmmu/arch_init.o
CC cris-linux-user/accel/stubs/kvm-stub.o
CC nios2-linux-user/gdbstub.o
CC tricore-softmmu/disas.o
CC s390x-softmmu/gdbstub.o
CC sh4-softmmu/monitor.o
CC ppc64-linux-user/gdbstub.o
CC sparc64-linux-user/accel/stubs/hvf-stub.o
CC sh4-softmmu/gdbstub.o
CC i386-softmmu/fpu/softfloat.o
CC mipsn32-linux-user/thunk.o
CC xtensaeb-softmmu/arch_init.o
CC s390x-softmmu/balloon.o
CC aarch64-linux-user/accel/tcg/tcg-runtime.o
CC mips-softmmu/monitor.o
CC sh4-softmmu/balloon.o
CC sparc-softmmu/tcg/optimize.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC ppc-softmmu/cpus.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC nios2-linux-user/thunk.o
CC mips64-linux-user/accel/stubs/hax-stub.o
CC ppc-linux-user/accel/stubs/kvm-stub.o
CC sh4-linux-user/disas.o
CC xtensa-softmmu/disas.o
CC ppc-softmmu/monitor.o
CC sparc64-linux-user/accel/stubs/kvm-stub.o
CC sparc32plus-linux-user/accel/tcg/cpu-exec.o
CC sh4eb-linux-user/disas.o
CC or1k-softmmu/tcg/tcg-common.o
CC sparc-softmmu/fpu/softfloat.o
CC x86_64-linux-user/disas.o
CC s390x-linux-user/fpu/softfloat.o
CC nios2-softmmu/arch_init.o
CC sh4-softmmu/ioport.o
CC aarch64-linux-user/accel/tcg/tcg-runtime-gvec.o
CC nios2-softmmu/cpus.o
CC tilegx-linux-user/disas.o
CC tilegx-linux-user/gdbstub.o
CC i386-linux-user/accel/stubs/kvm-stub.o
CC mipsn32-linux-user/accel/stubs/hax-stub.o
CC mipsn32el-linux-user/gdbstub.o
CC xtensa-softmmu/arch_init.o
CC or1k-linux-user/accel/tcg/cpu-exec.o
CC ppc64le-linux-user/disas.o
CC mipsel-linux-user/fpu/softfloat.o
CC ppc64abi32-linux-user/accel/stubs/hvf-stub.o
CC tricore-softmmu/arch_init.o
CC microblaze-linux-user/thunk.o
CC or1k-softmmu/tcg/optimize.o
CC or1k-softmmu/fpu/softfloat.o
CC microblazeel-softmmu/monitor.o
CC i386-linux-user/accel/tcg/tcg-runtime.o
CC mips64el-linux-user/thunk.o
CC aarch64-softmmu/fpu/softfloat.o
CC sh4eb-softmmu/disas.o
CC microblaze-linux-user/accel/stubs/hax-stub.o
CC arm-linux-user/accel/tcg/cpu-exec-common.o
CC sparc64-linux-user/accel/tcg/tcg-runtime.o
CC mipsel-softmmu/numa.o
CC xtensa-softmmu/cpus.o
CC or1k-linux-user/accel/tcg/cpu-exec-common.o
CC sh4-softmmu/numa.o
CC cris-linux-user/accel/tcg/tcg-runtime.o
CC ppcemb-softmmu/monitor.o
CC sh4eb-softmmu/arch_init.o
CC mipsel-softmmu/qtest.o
CC or1k-softmmu/disas.o
CC aarch64-linux-user/accel/tcg/cpu-exec.o
CC microblazeel-softmmu/gdbstub.o
CC microblazeel-softmmu/balloon.o
CC alpha-softmmu/gdbstub.o
CC ppc64abi32-linux-user/accel/stubs/kvm-stub.o
CC moxie-softmmu/arch_init.o
CC sh4-linux-user/gdbstub.o
CC ppc64-softmmu/arch_init.o
CC sparc-linux-user/accel/stubs/hvf-stub.o
CC aarch64-softmmu/disas.o
CC sparc-softmmu/disas.o
CC x86_64-softmmu/disas.o
CC arm-linux-user/accel/tcg/translate-all.o
CC mips64-softmmu/cpus.o
CC microblaze-linux-user/accel/stubs/hvf-stub.o
CC s390x-linux-user/disas.o
CC arm-linux-user/accel/tcg/translator.o
CC mipsn32-linux-user/accel/stubs/hvf-stub.o
CC i386-linux-user/accel/tcg/tcg-runtime-gvec.o
CC arm-linux-user/accel/tcg/user-exec.o
CC hppa-linux-user/accel/tcg/tcg-runtime.o
CC mips-softmmu/gdbstub.o
CC ppc64-linux-user/thunk.o
CC mips64el-linux-user/accel/stubs/hax-stub.o
CC tricore-softmmu/cpus.o
CC ppc64abi32-linux-user/accel/tcg/tcg-runtime.o
CC mips64-softmmu/monitor.o
CC unicore32-softmmu/arch_init.o
CC arm-softmmu/disas.o
CC mipsn32-linux-user/accel/stubs/kvm-stub.o
CC sparc64-linux-user/accel/tcg/tcg-runtime-gvec.o
CC ppc64-linux-user/accel/stubs/hax-stub.o
CC i386-softmmu/disas.o
CC microblaze-linux-user/accel/stubs/kvm-stub.o
CC sparc-linux-user/accel/stubs/kvm-stub.o
CC microblazeel-linux-user/gdbstub.o
CC or1k-linux-user/accel/tcg/translate-all.o
CC ppc64abi32-linux-user/accel/tcg/tcg-runtime-gvec.o
CC mips64el-linux-user/accel/stubs/hvf-stub.o
CC sparc32plus-linux-user/accel/tcg/cpu-exec-common.o
CC mips64-softmmu/gdbstub.o
CC sparc-linux-user/accel/tcg/tcg-runtime.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC sparc-linux-user/accel/tcg/tcg-runtime-gvec.o
CC aarch64-linux-user/accel/tcg/cpu-exec-common.o
CC hppa-linux-user/accel/tcg/tcg-runtime-gvec.o
CC hppa-linux-user/accel/tcg/cpu-exec.o
CC mips64-linux-user/accel/stubs/hvf-stub.o
CC xtensa-softmmu/monitor.o
CC nios2-linux-user/accel/stubs/hax-stub.o
CC sparc64-linux-user/accel/tcg/cpu-exec.o
CC microblaze-linux-user/accel/tcg/tcg-runtime.o
CC sparc64-softmmu/fpu/softfloat.o
CC xtensa-softmmu/gdbstub.o
CC mipsn32el-linux-user/thunk.o
CC aarch64-linux-user/accel/tcg/translate-all.o
CC mips64el-linux-user/accel/stubs/kvm-stub.o
CC mips-softmmu/balloon.o
CC ppc-linux-user/accel/tcg/tcg-runtime.o
GEN s390x-linux-user/gdbstub-xml.c
CC mipsn32el-linux-user/accel/stubs/hax-stub.o
Preprocessed source stored into /tmp/ccv73SEN.out file, please attach this to your bugreport.
CC mipsn32-linux-user/accel/tcg/tcg-runtime.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4-softmmu/qtest.o
CC nios2-linux-user/accel/stubs/hvf-stub.o
GEN i386-softmmu/gdbstub-xml.c
CC arm-linux-user/accel/tcg/user-exec-stub.o
CC nios2-softmmu/monitor.o
CC nios2-softmmu/gdbstub.o
CC tilegx-linux-user/thunk.o
CC unicore32-softmmu/cpus.o
CC sh4eb-softmmu/cpus.o
CC mipsel-softmmu/memory.o
CC sh4eb-softmmu/monitor.o
CC mips64el-linux-user/accel/tcg/tcg-runtime.o
CC mips64-linux-user/accel/stubs/kvm-stub.o
CC alpha-softmmu/balloon.o
CC mips-softmmu/ioport.o
CC lm32-softmmu/disas.o
CC s390x-softmmu/ioport.o
CC i386-linux-user/accel/tcg/cpu-exec.o
CC mipsn32el-linux-user/accel/stubs/hvf-stub.o
CC tricore-softmmu/monitor.o
CC mips64el-linux-user/accel/tcg/tcg-runtime-gvec.o
GEN x86_64-linux-user/gdbstub-xml.c
CC nios2-linux-user/accel/stubs/kvm-stub.o
CC microblazeel-linux-user/thunk.o
CC cris-linux-user/accel/tcg/tcg-runtime-gvec.o
GEN ppc64le-linux-user/gdbstub-xml.c
CC mips-linux-user/gdbstub.o
CC ppc64le-linux-user/gdbstub.o
CC nios2-linux-user/accel/tcg/tcg-runtime.o
CC lm32-softmmu/arch_init.o
CC microblaze-linux-user/accel/tcg/tcg-runtime-gvec.o
CC m68k-softmmu/arch_init.o
CC m68k-softmmu/cpus.o
CC mips64el-softmmu/tcg/tcg-common.o
GEN x86_64-softmmu/gdbstub-xml.c
CC mipsn32el-linux-user/accel/stubs/kvm-stub.o
CC microblazeel-linux-user/accel/stubs/hax-stub.o
GEN arm-softmmu/gdbstub-xml.c
CC ppc-softmmu/gdbstub.o
CC nios2-softmmu/balloon.o
CC sh4-softmmu/memory.o
CC x86_64-linux-user/gdbstub.o
CC xtensa-softmmu/balloon.o
CC microblaze-linux-user/accel/tcg/cpu-exec.o
CC tilegx-linux-user/accel/stubs/hax-stub.o
CC mips64-linux-user/accel/tcg/tcg-runtime.o
CC mipsn32-linux-user/accel/tcg/tcg-runtime-gvec.o
CC mipsn32-linux-user/accel/tcg/cpu-exec.o
CC sh4eb-softmmu/gdbstub.o
GEN aarch64-softmmu/gdbstub-xml.c
CC aarch64-softmmu/arch_init.o
CC sh4eb-softmmu/balloon.o
CC ppc64-softmmu/cpus.o
CC mips64el-softmmu/tcg/optimize.o
CC mipsn32el-linux-user/accel/tcg/tcg-runtime.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC m68k-softmmu/monitor.o
CC s390x-softmmu/numa.o
CC nios2-linux-user/accel/tcg/tcg-runtime-gvec.o
Preprocessed source stored into /tmp/ccErb2ii.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC cris-linux-user/accel/tcg/cpu-exec.o
CC tricore-softmmu/gdbstub.o
CC i386-softmmu/arch_init.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC microblaze-linux-user/accel/tcg/cpu-exec-common.o
CC sparc64-softmmu/disas.o
CC mipsel-linux-user/disas.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC ppc64abi32-linux-user/accel/tcg/cpu-exec.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC sh4eb-linux-user/gdbstub.o
CC xtensaeb-softmmu/cpus.o
make: *** [subdir-arm-linux-user] Error 2
CC mipsn32-linux-user/accel/tcg/cpu-exec-common.o
CC alpha-softmmu/ioport.o
make: *** [subdir-or1k-linux-user] Error 2
CC sh4-linux-user/thunk.o
CC ppc-linux-user/accel/tcg/tcg-runtime-gvec.o
CC i386-linux-user/accel/tcg/cpu-exec-common.o
CC s390x-softmmu/qtest.o
CC x86_64-softmmu/arch_init.o
CC i386-softmmu/cpus.o
CC sparc-linux-user/accel/tcg/cpu-exec.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC nios2-softmmu/ioport.o
Preprocessed source stored into /tmp/ccAdwccl.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make: *** [subdir-m68k-linux-user] Error 2
CC ppc-softmmu/balloon.o
CC mips64-linux-user/accel/tcg/tcg-runtime-gvec.o
CC cris-softmmu/monitor.o
CC sparc32plus-linux-user/accel/tcg/translate-all.o
CC sparc-linux-user/accel/tcg/cpu-exec-common.o
CC moxie-softmmu/cpus.o
CC i386-linux-user/accel/tcg/translate-all.o
CC sparc-linux-user/accel/tcg/translate-all.o
CC tilegx-linux-user/accel/stubs/hvf-stub.o
Preprocessed source stored into /tmp/cc55kJwr.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC xtensa-softmmu/ioport.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC microblazeel-linux-user/accel/stubs/hvf-stub.o
CC mips64el-linux-user/accel/tcg/cpu-exec.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mipsn32-linux-user/accel/tcg/translate-all.o
CC s390x-softmmu/memory.o
CC ppc-softmmu/ioport.o
CC microblaze-linux-user/accel/tcg/translate-all.o
CC i386-linux-user/accel/tcg/translator.o
CC mipsn32el-linux-user/accel/tcg/tcg-runtime-gvec.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mipsn32-linux-user/accel/tcg/translator.o
CC ppc-linux-user/accel/tcg/cpu-exec.o
CC tilegx-linux-user/accel/stubs/kvm-stub.o
CC aarch64_be-linux-user/accel/stubs/hax-stub.o
CC xtensaeb-softmmu/monitor.o
CC mips64-softmmu/balloon.o
CC aarch64-linux-user/accel/tcg/translator.o
CC microblaze-softmmu/arch_init.o
CC mips64-softmmu/ioport.o
CC microblazeel-linux-user/accel/stubs/kvm-stub.o
CC alpha-softmmu/numa.o
CC mips-softmmu/numa.o
CC ppc64-linux-user/accel/stubs/hvf-stub.o
CC aarch64_be-linux-user/accel/stubs/hvf-stub.o
CC i386-linux-user/accel/tcg/user-exec.o
CC mipsel-softmmu/memory_mapping.o
CC moxie-softmmu/monitor.o
CC microblazeel-softmmu/ioport.o
CC s390x-softmmu/memory_mapping.o
CC arm-softmmu/arch_init.o
CC mips-linux-user/thunk.o
CC x86_64-softmmu/cpus.o
CC microblazeel-linux-user/accel/tcg/tcg-runtime.o
CC sh4eb-linux-user/thunk.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC sparc-softmmu/arch_init.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC ppc-softmmu/numa.o
CC cris-softmmu/gdbstub.o
CC mipsn32-linux-user/accel/tcg/user-exec.o
CC aarch64-softmmu/cpus.o
CC cris-softmmu/balloon.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC x86_64-softmmu/monitor.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC tilegx-linux-user/accel/tcg/tcg-runtime.o
CC sh4-softmmu/memory_mapping.o
CC aarch64_be-linux-user/accel/stubs/kvm-stub.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC nios2-linux-user/accel/tcg/cpu-exec.o
CC mips-softmmu/qtest.o
CC ppc64-linux-user/accel/stubs/kvm-stub.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC aarch64-softmmu/monitor.o
CC sh4-softmmu/dump.o
CC sh4-softmmu/migration/ram.o
CC aarch64_be-linux-user/accel/tcg/tcg-runtime.o
CC tricore-softmmu/balloon.o
CC unicore32-softmmu/monitor.o
CC or1k-softmmu/arch_init.o
CC aarch64_be-linux-user/accel/tcg/tcg-runtime-gvec.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC aarch64_be-linux-user/accel/tcg/cpu-exec.o
CC aarch64_be-linux-user/accel/tcg/cpu-exec-common.o
CC ppc64abi32-linux-user/accel/tcg/cpu-exec-common.o
make: *** [subdir-sparc32plus-linux-user] Error 2
CC ppc64abi32-linux-user/accel/tcg/translate-all.o
CC tricore-softmmu/ioport.o
CC i386-softmmu/monitor.o
CC tricore-softmmu/numa.o
CC microblazeel-linux-user/accel/tcg/tcg-runtime-gvec.o
CC sh4-linux-user/accel/stubs/hax-stub.o
CC microblazeel-softmmu/numa.o
CC ppc-softmmu/qtest.o
CC ppc-linux-user/accel/tcg/cpu-exec-common.o
CC arm-softmmu/cpus.o
CC nios2-softmmu/numa.o
CC aarch64-linux-user/accel/tcg/user-exec.o
CC nios2-softmmu/qtest.o
CC m68k-softmmu/gdbstub.o
CC microblaze-softmmu/cpus.o
CC sparc-linux-user/accel/tcg/translator.o
CC ppc64-linux-user/accel/tcg/tcg-runtime.o
CC sparc64-softmmu/arch_init.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC mipsn32-linux-user/accel/tcg/user-exec-stub.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mips-linux-user/accel/stubs/hax-stub.o
CC ppc64-softmmu/monitor.o
CC sparc-linux-user/accel/tcg/user-exec.o
CC ppcemb-softmmu/gdbstub.o
CC alpha-softmmu/qtest.o
CC sparc-linux-user/accel/tcg/user-exec-stub.o
CC i386-softmmu/gdbstub.o
CC sparc-softmmu/cpus.o
CC sh4eb-softmmu/ioport.o
CC cris-softmmu/ioport.o
CC x86_64-softmmu/gdbstub.o
CC mips-softmmu/memory.o
CC alpha-softmmu/memory.o
CC mips-linux-user/accel/stubs/hvf-stub.o
CC aarch64_be-linux-user/accel/tcg/translate-all.o
CC sh4eb-linux-user/accel/stubs/hax-stub.o
CC microblazeel-softmmu/qtest.o
CC unicore32-softmmu/gdbstub.o
CC arm-softmmu/monitor.o
CC sh4eb-linux-user/accel/stubs/hvf-stub.o
CC mips64el-linux-user/accel/tcg/cpu-exec-common.o
CC mips64el-linux-user/accel/tcg/translate-all.o
CC sh4eb-softmmu/numa.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC x86_64-linux-user/thunk.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC sh4-softmmu/accel/accel.o
CC sh4-softmmu/accel/stubs/hax-stub.o
CC hppa-linux-user/accel/tcg/cpu-exec-common.o
CC cris-linux-user/accel/tcg/cpu-exec-common.o
CC mipsel-linux-user/gdbstub.o
CC ppc64-linux-user/accel/tcg/tcg-runtime-gvec.o
CC aarch64_be-linux-user/accel/tcg/translator.o
CC ppc-linux-user/accel/tcg/translate-all.o
CC sh4eb-linux-user/accel/stubs/kvm-stub.o
Preprocessed source stored into /tmp/ccmUcPJJ.out file, please attach this to your bugreport.
CC mips-linux-user/accel/stubs/kvm-stub.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4-softmmu/accel/stubs/hvf-stub.o
CC ppcemb-softmmu/balloon.o
CC nios2-linux-user/accel/tcg/cpu-exec-common.o
CC xtensaeb-softmmu/gdbstub.o
CC mipsel-softmmu/dump.o
CC nios2-softmmu/memory.o
CC mips64-softmmu/numa.o
CC sh4-linux-user/accel/stubs/hvf-stub.o
CC microblazeel-linux-user/accel/tcg/cpu-exec.o
CC x86_64-linux-user/accel/stubs/hax-stub.o
CC x86_64-linux-user/accel/stubs/hvf-stub.o
CC unicore32-softmmu/balloon.o
CC ppc64-linux-user/accel/tcg/cpu-exec.o
CC nios2-softmmu/memory_mapping.o
CC sparc64-linux-user/accel/tcg/cpu-exec-common.o
CC i386-linux-user/accel/tcg/user-exec-stub.o
CC microblaze-linux-user/accel/tcg/translator.o
CC mips-linux-user/accel/tcg/tcg-runtime.o
CC sparc64-linux-user/accel/tcg/translate-all.o
CC mips64el-softmmu/fpu/softfloat.o
CC moxie-softmmu/gdbstub.o
CC sh4eb-linux-user/accel/tcg/tcg-runtime.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC aarch64_be-linux-user/accel/tcg/user-exec.o
CC xtensa-softmmu/numa.o
CC aarch64_be-linux-user/accel/tcg/user-exec-stub.o
CC ppc64le-linux-user/thunk.o
CC sh4-linux-user/accel/stubs/kvm-stub.o
CC microblazeel-softmmu/memory.o
CC ppc64le-linux-user/accel/stubs/hax-stub.o
CC ppc64-linux-user/accel/tcg/cpu-exec-common.o
CC sh4eb-linux-user/accel/tcg/tcg-runtime-gvec.o
CC i386-linux-user/linux-user/main.o
CC sh4eb-linux-user/accel/tcg/cpu-exec.o
CC lm32-softmmu/cpus.o
CC ppc-softmmu/memory.o
CC sh4eb-softmmu/qtest.o
CC mipsn32-linux-user/linux-user/main.o
CC xtensa-softmmu/qtest.o
CC sparc-linux-user/linux-user/main.o
CC xtensaeb-softmmu/balloon.o
CC arm-softmmu/gdbstub.o
Preprocessed source stored into /tmp/ccE57Isz.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC tricore-softmmu/qtest.o
CC tilegx-linux-user/accel/tcg/tcg-runtime-gvec.o
CC ppcemb-softmmu/ioport.o
CC xtensa-softmmu/memory.o
CC x86_64-softmmu/balloon.o
CC sh4-linux-user/accel/tcg/tcg-runtime.o
CC x86_64-softmmu/ioport.o
Preprocessed source stored into /tmp/ccau9G1Z.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
CC aarch64_be-linux-user/linux-user/main.o
make: *** [subdir-hppa-linux-user] Error 2
CC ppc64-linux-user/accel/tcg/translate-all.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mipsel-softmmu/migration/ram.o
CC or1k-softmmu/cpus.o
CC microblaze-softmmu/monitor.o
CC ppc-softmmu/memory_mapping.o
CC mips-linux-user/accel/tcg/tcg-runtime-gvec.o
CC x86_64-linux-user/accel/stubs/kvm-stub.o
Preprocessed source stored into /tmp/ccN9ydCX.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64el-linux-user/accel/tcg/translator.o
CC lm32-softmmu/monitor.o
CC mipsel-softmmu/accel/accel.o
CC mips64-softmmu/qtest.o
CC alpha-softmmu/memory_mapping.o
CC microblaze-linux-user/accel/tcg/user-exec.o
CC mips-linux-user/accel/tcg/cpu-exec.o
CC xtensaeb-softmmu/ioport.o
CC mips-softmmu/memory_mapping.o
CC ppc64abi32-linux-user/accel/tcg/translator.o
CC mips64el-softmmu/disas.o
CC ppc64-linux-user/accel/tcg/translator.o
CC i386-softmmu/balloon.o
CC mips-linux-user/accel/tcg/cpu-exec-common.o
CC mips-linux-user/accel/tcg/translate-all.o
make: *** [subdir-aarch64-linux-user] Error 2
CC tricore-softmmu/memory.o
CC nios2-linux-user/accel/tcg/translate-all.o
CC xtensa-softmmu/memory_mapping.o
CC cris-softmmu/numa.o
CC x86_64-linux-user/accel/tcg/tcg-runtime.o
CC sh4eb-linux-user/accel/tcg/cpu-exec-common.o
CC mips64el-linux-user/accel/tcg/user-exec.o
CC ppc64le-linux-user/accel/stubs/hvf-stub.o
CC mips64-linux-user/accel/tcg/cpu-exec.o
CC tilegx-linux-user/accel/tcg/cpu-exec.o
CC tricore-softmmu/memory_mapping.o
Preprocessed source stored into /tmp/cc1dW6xK.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC microblazeel-linux-user/accel/tcg/cpu-exec-common.o
CC ppc64-linux-user/accel/tcg/user-exec.o
CC ppc64-linux-user/accel/tcg/user-exec-stub.o
CC ppc64abi32-linux-user/accel/tcg/user-exec.o
CC microblaze-linux-user/accel/tcg/user-exec-stub.o
Preprocessed source stored into /tmp/cc6Tkt1U.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mipsel-softmmu/accel/stubs/hax-stub.o
CC sh4-linux-user/accel/tcg/tcg-runtime-gvec.o
CC sparc-softmmu/monitor.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC x86_64-linux-user/accel/tcg/tcg-runtime-gvec.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC ppc64le-linux-user/accel/stubs/kvm-stub.o
CC sparc64-softmmu/cpus.o
CC ppcemb-softmmu/numa.o
CC ppc64-linux-user/linux-user/main.o
CC microblaze-linux-user/linux-user/main.o
CC ppc-linux-user/accel/tcg/translator.o
CC microblaze-linux-user/linux-user/syscall.o
CC ppcemb-softmmu/qtest.o
CC xtensa-softmmu/dump.o
CC lm32-softmmu/gdbstub.o
CC microblazeel-linux-user/accel/tcg/translate-all.o
CC x86_64-linux-user/accel/tcg/cpu-exec.o
CC m68k-softmmu/balloon.o
CC sh4-softmmu/accel/stubs/kvm-stub.o
CC x86_64-linux-user/accel/tcg/cpu-exec-common.o
Preprocessed source stored into /tmp/ccBJWmnm.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make: *** [subdir-cris-linux-user] Error 2
CC tilegx-linux-user/accel/tcg/cpu-exec-common.o
CC unicore32-softmmu/ioport.o
CC lm32-softmmu/balloon.o
CC s390x-softmmu/dump.o
make: *** [subdir-sparc64-linux-user] Error 2
CC sh4-linux-user/accel/tcg/cpu-exec.o
CC ppc64-softmmu/gdbstub.o
CC ppc-softmmu/dump.o
CC microblazeel-softmmu/memory_mapping.o
CC xtensaeb-softmmu/numa.o
CC s390x-linux-user/gdbstub.o
make: *** [subdir-sparc-linux-user] Error 2
CC tricore-softmmu/dump.o
CC tricore-softmmu/migration/ram.o
CC sh4eb-softmmu/memory.o
CC lm32-softmmu/ioport.o
CC sh4eb-softmmu/memory_mapping.o
CC unicore32-softmmu/numa.o
CC ppc64le-linux-user/accel/tcg/tcg-runtime.o
CC unicore32-softmmu/qtest.o
CC microblazeel-softmmu/dump.o
CC microblaze-linux-user/linux-user/strace.o
CC mips64-softmmu/memory.o
make: *** [subdir-i386-linux-user] Error 2
CC sh4-linux-user/accel/tcg/cpu-exec-common.o
Preprocessed source stored into /tmp/ccO1e6F9.out file, please attach this to your bugreport.
CC mipsn32-linux-user/linux-user/syscall.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppc64le-linux-user/accel/tcg/tcg-runtime-gvec.o
CC microblazeel-linux-user/accel/tcg/translator.o
CC ppc64-linux-user/linux-user/syscall.o
Preprocessed source stored into /tmp/cc1Q9q8U.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC cris-softmmu/qtest.o
CC aarch64_be-linux-user/linux-user/syscall.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC ppc64-softmmu/balloon.o
CC m68k-softmmu/ioport.o
CC sh4-linux-user/accel/tcg/translate-all.o
CC mips64el-linux-user/accel/tcg/user-exec-stub.o
CC sh4-softmmu/accel/tcg/tcg-all.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC aarch64-softmmu/gdbstub.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC x86_64-softmmu/numa.o
CC unicore32-softmmu/memory.o
CC aarch64-softmmu/balloon.o
CC tilegx-linux-user/accel/tcg/translate-all.o
CC mipsn32el-linux-user/accel/tcg/cpu-exec.o
CC sh4-linux-user/accel/tcg/translator.o
CC tricore-softmmu/accel/accel.o
CC mips64-softmmu/memory_mapping.o
CC ppcemb-softmmu/memory.o
Preprocessed source stored into /tmp/ccxEDXOD.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mipsel-softmmu/accel/stubs/hvf-stub.o
CC or1k-softmmu/monitor.o
CC aarch64-softmmu/ioport.o
CC microblazeel-linux-user/accel/tcg/user-exec.o
CC microblazeel-linux-user/accel/tcg/user-exec-stub.o
Preprocessed source stored into /tmp/ccFlOTd0.out file, please attach this to your bugreport.
CC sh4eb-linux-user/accel/tcg/translate-all.o
CC tricore-softmmu/accel/stubs/hax-stub.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC unicore32-softmmu/memory_mapping.o
CC lm32-softmmu/numa.o
CC sh4-softmmu/accel/tcg/cputlb.o
CC lm32-softmmu/qtest.o
make: *** [subdir-nios2-linux-user] Error 2
CC x86_64-linux-user/accel/tcg/translate-all.o
CC sparc64-softmmu/monitor.o
CC microblazeel-linux-user/linux-user/main.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC arm-softmmu/balloon.o
CC ppcemb-softmmu/memory_mapping.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mips64-linux-user/accel/tcg/cpu-exec-common.o
CC x86_64-softmmu/qtest.o
CC ppc64le-linux-user/accel/tcg/cpu-exec.o
CC x86_64-softmmu/memory.o
CC aarch64-softmmu/numa.o
CC aarch64-softmmu/qtest.o
CC ppc64-softmmu/ioport.o
CC sh4eb-linux-user/accel/tcg/translator.o
CC microblazeel-linux-user/linux-user/syscall.o
Preprocessed source stored into /tmp/ccAPc5PY.out file, please attach this to your bugreport.
CC xtensa-softmmu/migration/ram.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC unicore32-softmmu/dump.o
CC moxie-softmmu/balloon.o
CC mips64el-softmmu/arch_init.o
CC mips64-softmmu/dump.o
CC mipsel-softmmu/accel/stubs/kvm-stub.o
CC sparc64-softmmu/gdbstub.o
CC mipsel-linux-user/thunk.o
CC mips64-softmmu/migration/ram.o
CC mips64-softmmu/accel/accel.o
CC xtensaeb-softmmu/qtest.o
CC tilegx-linux-user/accel/tcg/translator.o
CC aarch64_be-linux-user/linux-user/strace.o
CC xtensa-softmmu/accel/accel.o
make: *** [subdir-ppc-linux-user] Error 2
CC nios2-softmmu/dump.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC ppc64le-linux-user/accel/tcg/cpu-exec-common.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
make: *** [subdir-mips64el-linux-user] Error 2
CC mipsn32el-linux-user/accel/tcg/cpu-exec-common.o
CC ppcemb-softmmu/dump.o
CC m68k-softmmu/numa.o
CC sparc64-softmmu/balloon.o
CC i386-softmmu/ioport.o
Preprocessed source stored into /tmp/ccWgGirn.out file, please attach this to your bugreport.
CC i386-softmmu/numa.o
CC nios2-softmmu/migration/ram.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC cris-softmmu/memory.o
CC aarch64_be-linux-user/linux-user/mmap.o
CC ppc64-linux-user/linux-user/strace.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC xtensa-softmmu/accel/stubs/hax-stub.o
CC lm32-softmmu/memory.o
CC sh4-linux-user/accel/tcg/user-exec.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC sh4-linux-user/accel/tcg/user-exec-stub.o
CC sparc64-softmmu/ioport.o
CC unicore32-softmmu/migration/ram.o
make: *** [subdir-ppc64abi32-linux-user] Error 2
CC mips-softmmu/dump.o
CC nios2-softmmu/accel/accel.o
CC moxie-softmmu/ioport.o
CC moxie-softmmu/numa.o
CC xtensaeb-softmmu/memory.o
CC sh4-softmmu/accel/tcg/tcg-runtime.o
CC mips64el-softmmu/cpus.o
CC nios2-softmmu/accel/stubs/hax-stub.o
CC mips64-linux-user/accel/tcg/translate-all.o
CC mips64-linux-user/accel/tcg/translator.o
CC aarch64-softmmu/memory.o
CC microblaze-softmmu/gdbstub.o
CC sparc64-softmmu/numa.o
CC ppc-softmmu/migration/ram.o
CC mipsel-linux-user/accel/stubs/hax-stub.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
make: *** [subdir-mipsn32el-linux-user] Error 2
CC ppcemb-softmmu/migration/ram.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC aarch64_be-linux-user/linux-user/signal.o
CC xtensa-softmmu/accel/stubs/hvf-stub.o
Preprocessed source stored into /tmp/ccv6mJG4.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppc64le-linux-user/accel/tcg/translate-all.o
CC mips-softmmu/migration/ram.o
CC x86_64-softmmu/memory_mapping.o
CC mips64el-softmmu/monitor.o
CC unicore32-softmmu/accel/accel.o
CC mips64el-softmmu/gdbstub.o
CC ppcemb-softmmu/accel/accel.o
CC ppc64le-linux-user/accel/tcg/translator.o
CC alpha-softmmu/dump.o
CC sh4-softmmu/accel/tcg/tcg-runtime-gvec.o
CC m68k-softmmu/qtest.o
CC microblazeel-softmmu/migration/ram.o
CC ppc64-softmmu/numa.o
CC arm-softmmu/ioport.o
CC microblazeel-linux-user/linux-user/strace.o
CC ppcemb-softmmu/accel/kvm/kvm-all.o
CC s390x-softmmu/migration/ram.o
CC s390x-linux-user/thunk.o
CC mipsel-softmmu/accel/tcg/tcg-all.o
CC or1k-softmmu/gdbstub.o
CC i386-softmmu/qtest.o
CC s390x-linux-user/accel/stubs/hax-stub.o
CC ppcemb-softmmu/accel/stubs/hax-stub.o
CC microblazeel-linux-user/linux-user/mmap.o
CC ppc-softmmu/accel/accel.o
CC sparc-softmmu/gdbstub.o
CC mips64-softmmu/accel/stubs/hax-stub.o
CC mipsel-linux-user/accel/stubs/hvf-stub.o
CC sparc64-softmmu/qtest.o
CC moxie-softmmu/qtest.o
CC microblazeel-linux-user/linux-user/signal.o
Preprocessed source stored into /tmp/ccAbtKeu.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC unicore32-softmmu/accel/stubs/hax-stub.o
CC tilegx-linux-user/accel/tcg/user-exec.o
CC mips64-softmmu/accel/stubs/hvf-stub.o
CC mips64-softmmu/accel/stubs/kvm-stub.o
CC alpha-softmmu/migration/ram.o
Preprocessed source stored into /tmp/cccLQzvn.out file, please attach this to your bugreport.
CC sh4-softmmu/accel/tcg/cpu-exec.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc64-softmmu/memory.o
CC tilegx-linux-user/accel/tcg/user-exec-stub.o
CC mips-linux-user/accel/tcg/translator.o
CC sh4-softmmu/accel/tcg/cpu-exec-common.o
CC microblazeel-softmmu/accel/accel.o
CC s390x-linux-user/accel/stubs/hvf-stub.o
CC s390x-softmmu/accel/accel.o
CC mipsel-softmmu/accel/tcg/cputlb.o
CC sh4-linux-user/linux-user/main.o
CC moxie-softmmu/memory.o
CC alpha-softmmu/accel/accel.o
CC mipsel-linux-user/accel/stubs/kvm-stub.o
CC xtensaeb-softmmu/memory_mapping.o
CC sh4-linux-user/linux-user/syscall.o
CC mips-linux-user/accel/tcg/user-exec.o
CC sh4-linux-user/linux-user/strace.o
CC unicore32-softmmu/accel/stubs/hvf-stub.o
CC ppc-softmmu/accel/kvm/kvm-all.o
CC sh4eb-linux-user/accel/tcg/user-exec.o
CC aarch64-softmmu/memory_mapping.o
CC moxie-softmmu/memory_mapping.o
CC m68k-softmmu/memory.o
CC mips-softmmu/accel/accel.o
CC arm-softmmu/numa.o
CC mips-softmmu/accel/stubs/hax-stub.o
CC mips-linux-user/accel/tcg/user-exec-stub.o
CC s390x-linux-user/accel/stubs/kvm-stub.o
CC x86_64-softmmu/dump.o
CC moxie-softmmu/dump.o
CC alpha-softmmu/accel/stubs/hax-stub.o
CC mipsel-linux-user/accel/tcg/tcg-runtime.o
CC alpha-softmmu/accel/stubs/hvf-stub.o
CC ppc64-softmmu/qtest.o
CC mips64-softmmu/accel/tcg/tcg-all.o
CC microblazeel-softmmu/accel/stubs/hax-stub.o
CC ppcemb-softmmu/accel/stubs/hvf-stub.o
CC s390x-softmmu/accel/stubs/hax-stub.o
CC sh4-softmmu/accel/tcg/translate-all.o
CC x86_64-softmmu/migration/ram.o
CC sh4-softmmu/accel/tcg/translator.o
CC moxie-softmmu/migration/ram.o
CC xtensaeb-softmmu/dump.o
CC m68k-softmmu/memory_mapping.o
CC mips-linux-user/linux-user/main.o
CC xtensa-softmmu/accel/stubs/kvm-stub.o
CC microblaze-softmmu/balloon.o
CC nios2-softmmu/accel/stubs/hvf-stub.o
CC s390x-linux-user/accel/tcg/tcg-runtime.o
CC lm32-softmmu/memory_mapping.o
CC xtensa-softmmu/accel/tcg/tcg-all.o
CC arm-softmmu/qtest.o
CC mips64-softmmu/accel/tcg/cputlb.o
CC nios2-softmmu/accel/stubs/kvm-stub.o
CC ppc64-softmmu/memory.o
make: *** [subdir-mips64-linux-user] Error 2
CC cris-softmmu/memory_mapping.o
CC mipsel-softmmu/accel/tcg/tcg-runtime.o
CC arm-softmmu/memory.o
CC tricore-softmmu/accel/stubs/hvf-stub.o
CC ppc64le-linux-user/accel/tcg/user-exec.o
CC s390x-softmmu/accel/stubs/hvf-stub.o
CC i386-softmmu/memory.o
CC mips-softmmu/accel/stubs/hvf-stub.o
CC nios2-softmmu/accel/tcg/tcg-all.o
CC arm-softmmu/memory_mapping.o
CC s390x-linux-user/accel/tcg/tcg-runtime-gvec.o
CC sh4-softmmu/hw/9pfs/virtio-9p-device.o
CC mips-softmmu/accel/stubs/kvm-stub.o
CC mipsel-linux-user/accel/tcg/tcg-runtime-gvec.o
CC mips64-softmmu/accel/tcg/tcg-runtime.o
CC nios2-softmmu/accel/tcg/cputlb.o
CC sparc64-softmmu/memory_mapping.o
CC tricore-softmmu/accel/stubs/kvm-stub.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC sh4eb-linux-user/accel/tcg/user-exec-stub.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC xtensa-softmmu/accel/tcg/cputlb.o
CC arm-softmmu/dump.o
CC sh4eb-softmmu/dump.o
CC ppc64-linux-user/linux-user/mmap.o
CC m68k-softmmu/dump.o
CC sparc-softmmu/balloon.o
CC xtensaeb-softmmu/migration/ram.o
CC xtensa-softmmu/accel/tcg/tcg-runtime.o
CC xtensaeb-softmmu/accel/accel.o
CC ppc64le-linux-user/accel/tcg/user-exec-stub.o
CC sh4eb-softmmu/migration/ram.o
CC tricore-softmmu/accel/tcg/tcg-all.o
CC nios2-softmmu/accel/tcg/tcg-runtime.o
CC sparc-softmmu/ioport.o
CC s390x-linux-user/accel/tcg/cpu-exec.o
CC ppc64-linux-user/linux-user/signal.o
CC sh4-linux-user/linux-user/mmap.o
CC mipsel-softmmu/accel/tcg/tcg-runtime-gvec.o
CC microblaze-softmmu/ioport.o
CC s390x-softmmu/accel/stubs/kvm-stub.o
CC mipsel-softmmu/accel/tcg/cpu-exec.o
CC ppc64-softmmu/memory_mapping.o
CC sh4eb-softmmu/accel/accel.o
CC mipsel-softmmu/accel/tcg/cpu-exec-common.o
CC unicore32-softmmu/accel/stubs/kvm-stub.o
Preprocessed source stored into /tmp/cct7SF4r.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC arm-softmmu/migration/ram.o
CC microblaze-softmmu/numa.o
Preprocessed source stored into /tmp/ccv68tWR.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64el-softmmu/balloon.o
CC ppc64-softmmu/dump.o
CC sh4-linux-user/linux-user/signal.o
CC sh4-softmmu/hw/block/tc58128.o
CC ppc64-softmmu/migration/ram.o
CC x86_64-softmmu/accel/accel.o
CC s390x-softmmu/accel/tcg/tcg-all.o
CC i386-softmmu/memory_mapping.o
CC sh4-softmmu/hw/block/virtio-blk.o
CC mipsel-linux-user/accel/tcg/cpu-exec.o
CC cris-softmmu/dump.o
Preprocessed source stored into /tmp/ccWU1Ae8.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make: *** [subdir-tilegx-linux-user] Error 2
CC cris-softmmu/migration/ram.o
CC ppc-softmmu/accel/stubs/hax-stub.o
CC sparc64-softmmu/dump.o
CC ppc-softmmu/accel/stubs/hvf-stub.o
CC tricore-softmmu/accel/tcg/cputlb.o
CC lm32-softmmu/dump.o
CC m68k-softmmu/migration/ram.o
CC sh4eb-softmmu/accel/stubs/hax-stub.o
CC mips-softmmu/accel/tcg/tcg-all.o
CC x86_64-softmmu/accel/stubs/hax-stub.o
CC unicore32-softmmu/accel/tcg/tcg-all.o
CC x86_64-softmmu/accel/stubs/hvf-stub.o
CC cris-softmmu/accel/accel.o
CC cris-softmmu/accel/stubs/hax-stub.o
CC ppcemb-softmmu/accel/tcg/tcg-all.o
CC tricore-softmmu/accel/tcg/tcg-runtime.o
CC nios2-softmmu/accel/tcg/tcg-runtime-gvec.o
CC nios2-softmmu/accel/tcg/cpu-exec.o
CC sh4-softmmu/hw/block/dataplane/virtio-blk.o
CC sh4-softmmu/hw/char/sh_serial.o
Preprocessed source stored into /tmp/ccNxweQM.out file, please attach this to your bugreport.
CC ppc64-softmmu/accel/accel.o
CC s390x-softmmu/accel/tcg/cputlb.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppcemb-softmmu/accel/tcg/cputlb.o
CC ppc-softmmu/accel/tcg/tcg-all.o
CC x86_64-softmmu/accel/stubs/kvm-stub.o
CC or1k-softmmu/balloon.o
CC mips64el-softmmu/ioport.o
CC mips-softmmu/accel/tcg/cputlb.o
CC s390x-softmmu/accel/tcg/tcg-runtime.o
CC mips64el-softmmu/numa.o
CC xtensa-softmmu/accel/tcg/tcg-runtime-gvec.o
CC m68k-softmmu/accel/accel.o
CC m68k-softmmu/accel/stubs/hax-stub.o
CC ppc64-softmmu/accel/kvm/kvm-all.o
make: *** [subdir-sh4eb-linux-user] Error 2
CC i386-softmmu/dump.o
CC or1k-softmmu/ioport.o
CC unicore32-softmmu/accel/tcg/cputlb.o
CC x86_64-softmmu/accel/tcg/tcg-all.o
CC x86_64-softmmu/accel/tcg/cputlb.o
CC sparc64-softmmu/migration/ram.o
Preprocessed source stored into /tmp/ccxZttxc.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make: *** [subdir-mips-linux-user] Error 2
CC xtensa-softmmu/accel/tcg/cpu-exec.o
CC alpha-softmmu/accel/stubs/kvm-stub.o
CC mips64-softmmu/accel/tcg/tcg-runtime-gvec.o
CC sparc64-softmmu/accel/accel.o
CC microblazeel-softmmu/accel/stubs/hvf-stub.o
CC alpha-softmmu/accel/tcg/tcg-all.o
CC mipsel-linux-user/accel/tcg/cpu-exec-common.o
CC mipsel-softmmu/accel/tcg/translate-all.o
CC sh4eb-softmmu/accel/stubs/hvf-stub.o
CC sparc-softmmu/numa.o
CC xtensa-softmmu/accel/tcg/cpu-exec-common.o
CC m68k-softmmu/accel/stubs/hvf-stub.o
CC xtensa-softmmu/accel/tcg/translate-all.o
CC moxie-softmmu/accel/accel.o
CC x86_64-linux-user/accel/tcg/translator.o
CC ppc64-softmmu/accel/stubs/hax-stub.o
CC s390x-softmmu/accel/tcg/tcg-runtime-gvec.o
CC mipsel-softmmu/accel/tcg/translator.o
CC ppc64-softmmu/accel/stubs/hvf-stub.o
CC x86_64-softmmu/accel/tcg/tcg-runtime.o
CC ppc64le-linux-user/linux-user/main.o
CC ppc64le-linux-user/linux-user/syscall.o
CC mips-softmmu/accel/tcg/tcg-runtime.o
CC mips64-softmmu/accel/tcg/cpu-exec.o
CC microblaze-softmmu/qtest.o
CC ppc-softmmu/accel/tcg/cputlb.o
CC tricore-softmmu/accel/tcg/tcg-runtime-gvec.o
CC nios2-softmmu/accel/tcg/cpu-exec-common.o
CC ppc64le-linux-user/linux-user/strace.o
CC microblazeel-softmmu/accel/stubs/kvm-stub.o
CC x86_64-softmmu/accel/tcg/tcg-runtime-gvec.o
CC unicore32-softmmu/accel/tcg/tcg-runtime.o
CC microblaze-softmmu/memory.o
Preprocessed source stored into /tmp/cc3QqNIr.out file, please attach this to your bugreport.
CC ppcemb-softmmu/accel/tcg/tcg-runtime.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC x86_64-softmmu/accel/tcg/cpu-exec.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC x86_64-softmmu/accel/tcg/cpu-exec-common.o
CC m68k-softmmu/accel/stubs/kvm-stub.o
CC sparc-softmmu/qtest.o
CC ppc64le-linux-user/linux-user/mmap.o
CC tricore-softmmu/accel/tcg/cpu-exec.o
CC mips-softmmu/accel/tcg/tcg-runtime-gvec.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC sh4-softmmu/hw/char/virtio-serial-bus.o
CC sparc64-softmmu/accel/stubs/hax-stub.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mips-softmmu/accel/tcg/cpu-exec.o
CC mips-softmmu/accel/tcg/cpu-exec-common.o
CC sparc-softmmu/memory.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
Preprocessed source stored into /tmp/ccmM7v2L.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4eb-softmmu/accel/stubs/kvm-stub.o
CC sh4-softmmu/hw/core/generic-loader.o
CC cris-softmmu/accel/stubs/hvf-stub.o
CC arm-softmmu/accel/accel.o
CC xtensa-softmmu/accel/tcg/translator.o
CC aarch64-softmmu/dump.o
CC sparc64-softmmu/accel/stubs/hvf-stub.o
CC nios2-softmmu/accel/tcg/translate-all.o
CC cris-softmmu/accel/stubs/kvm-stub.o
CC ppcemb-softmmu/accel/tcg/tcg-runtime-gvec.o
CC mips64-softmmu/accel/tcg/cpu-exec-common.o
CC sparc-softmmu/memory_mapping.o
CC alpha-softmmu/accel/tcg/cputlb.o
CC ppcemb-softmmu/accel/tcg/cpu-exec.o
CC s390x-softmmu/accel/tcg/cpu-exec.o
CC microblazeel-softmmu/accel/tcg/tcg-all.o
CC m68k-softmmu/accel/tcg/tcg-all.o
CC xtensaeb-softmmu/accel/stubs/hax-stub.o
CC or1k-softmmu/numa.o
CC sparc64-softmmu/accel/stubs/kvm-stub.o
CC s390x-linux-user/accel/tcg/cpu-exec-common.o
CC xtensa-softmmu/hw/core/generic-loader.o
CC microblazeel-softmmu/accel/tcg/cputlb.o
CC i386-softmmu/migration/ram.o
CC ppc64-softmmu/accel/tcg/tcg-all.o
CC moxie-softmmu/accel/stubs/hax-stub.o
CC mips64el-softmmu/qtest.o
CC sh4eb-softmmu/accel/tcg/tcg-all.o
CC aarch64-softmmu/migration/ram.o
CC microblazeel-softmmu/accel/tcg/tcg-runtime.o
CC ppcemb-softmmu/accel/tcg/cpu-exec-common.o
CC nios2-softmmu/accel/tcg/translator.o
CC moxie-softmmu/accel/stubs/hvf-stub.o
CC mips-softmmu/accel/tcg/translate-all.o
CC sparc64-softmmu/accel/tcg/tcg-all.o
CC ppc64-softmmu/accel/tcg/cputlb.o
CC xtensa-softmmu/hw/core/null-machine.o
CC sh4-softmmu/hw/core/null-machine.o
CC m68k-softmmu/accel/tcg/cputlb.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
CC i386-softmmu/accel/accel.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC s390x-linux-user/accel/tcg/translate-all.o
CC mips64-softmmu/accel/tcg/translate-all.o
CC lm32-softmmu/migration/ram.o
CC moxie-softmmu/accel/stubs/kvm-stub.o
CC lm32-softmmu/accel/accel.o
CC xtensa-softmmu/hw/misc/mmio_interface.o
CC m68k-softmmu/accel/tcg/tcg-runtime.o
CC arm-softmmu/accel/stubs/hax-stub.o
CC tricore-softmmu/accel/tcg/cpu-exec-common.o
CC mips64-softmmu/accel/tcg/translator.o
CC x86_64-softmmu/accel/tcg/translate-all.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC sparc-softmmu/dump.o
make: *** [subdir-x86_64-linux-user] Error 2
CC xtensa-softmmu/hw/net/vhost_net.o
CC mips-softmmu/accel/tcg/translator.o
CC tricore-softmmu/accel/tcg/translate-all.o
CC sparc64-softmmu/accel/tcg/cputlb.o
CC ppc64-softmmu/accel/tcg/tcg-runtime.o
CC m68k-softmmu/accel/tcg/tcg-runtime-gvec.o
CC tricore-softmmu/accel/tcg/translator.o
CC mipsel-softmmu/hw/9pfs/virtio-9p-device.o
CC cris-softmmu/accel/tcg/tcg-all.o
CC lm32-softmmu/accel/stubs/hax-stub.o
CC s390x-softmmu/accel/tcg/cpu-exec-common.o
CC xtensa-softmmu/hw/net/rocker/qmp-norocker.o
CC i386-softmmu/accel/stubs/hax-stub.o
CC i386-softmmu/accel/stubs/hvf-stub.o
CC arm-softmmu/accel/stubs/hvf-stub.o
CC ppcemb-softmmu/accel/tcg/translate-all.o
CC lm32-softmmu/accel/stubs/hvf-stub.o
CC or1k-softmmu/qtest.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC sparc-softmmu/migration/ram.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC microblazeel-softmmu/accel/tcg/tcg-runtime-gvec.o
CC i386-softmmu/accel/stubs/kvm-stub.o
CC xtensaeb-softmmu/accel/stubs/hvf-stub.o
CC moxie-softmmu/accel/tcg/tcg-all.o
CC ppcemb-softmmu/accel/tcg/translator.o
CC arm-softmmu/accel/stubs/kvm-stub.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC lm32-softmmu/accel/stubs/kvm-stub.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC x86_64-softmmu/accel/tcg/translator.o
CC i386-softmmu/accel/tcg/tcg-all.o
CC s390x-softmmu/accel/tcg/translate-all.o
CC microblaze-softmmu/memory_mapping.o
CC moxie-softmmu/accel/tcg/cputlb.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC mipsel-softmmu/hw/block/virtio-blk.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC moxie-softmmu/accel/tcg/tcg-runtime.o
CC i386-softmmu/accel/tcg/cputlb.o
CC s390x-linux-user/accel/tcg/translator.o
CC tricore-softmmu/hw/core/generic-loader.o
CC microblazeel-softmmu/accel/tcg/cpu-exec.o
CC lm32-softmmu/accel/tcg/tcg-all.o
CC sh4-softmmu/hw/display/sm501.o
CC xtensa-softmmu/hw/vfio/common.o
CC xtensa-softmmu/hw/vfio/platform.o
CC xtensa-softmmu/hw/vfio/spapr.o
CC ppc64-softmmu/accel/tcg/tcg-runtime-gvec.o
CC sh4eb-softmmu/accel/tcg/cputlb.o
CC mips64-softmmu/hw/9pfs/virtio-9p-device.o
CC sh4eb-softmmu/accel/tcg/tcg-runtime.o
CC mipsel-softmmu/hw/block/dataplane/virtio-blk.o
CC xtensa-softmmu/hw/xtensa/pic_cpu.o
CC sh4eb-softmmu/accel/tcg/tcg-runtime-gvec.o
CC mipsel-softmmu/hw/char/virtio-serial-bus.o
CC microblaze-softmmu/dump.o
CC sparc-softmmu/accel/accel.o
Preprocessed source stored into /tmp/ccTNuKmd.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC arm-softmmu/accel/tcg/tcg-all.o
CC xtensaeb-softmmu/accel/stubs/kvm-stub.o
CC cris-softmmu/accel/tcg/cputlb.o
CC ppc64-softmmu/accel/tcg/cpu-exec.o
CC sparc64-softmmu/accel/tcg/tcg-runtime.o
CC sparc64-softmmu/accel/tcg/tcg-runtime-gvec.o
CC microblazeel-softmmu/accel/tcg/cpu-exec-common.o
CC microblaze-softmmu/migration/ram.o
CC ppcemb-softmmu/hw/9pfs/virtio-9p-device.o
CC or1k-softmmu/memory.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC cris-softmmu/accel/tcg/tcg-runtime.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC microblazeel-softmmu/accel/tcg/translate-all.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC arm-softmmu/accel/tcg/cputlb.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC or1k-softmmu/memory_mapping.o
CC s390x-linux-user/accel/tcg/user-exec.o
CC mips64el-softmmu/memory.o
CC mips-softmmu/hw/9pfs/virtio-9p-device.o
CC lm32-softmmu/accel/tcg/cputlb.o
CC moxie-softmmu/accel/tcg/tcg-runtime-gvec.o
CC mips64el-softmmu/memory_mapping.o
CC or1k-softmmu/dump.o
CC mips-softmmu/hw/block/virtio-blk.o
CC xtensaeb-softmmu/accel/tcg/tcg-all.o
CC mips64-softmmu/hw/block/virtio-blk.o
CC mips-softmmu/hw/block/dataplane/virtio-blk.o
CC ppc64-softmmu/accel/tcg/cpu-exec-common.o
CC aarch64-softmmu/accel/accel.o
CC ppc64-softmmu/accel/tcg/translate-all.o
CC s390x-linux-user/accel/tcg/user-exec-stub.o
CC mips64el-softmmu/dump.o
CC s390x-softmmu/accel/tcg/translator.o
CC mips64-softmmu/hw/block/dataplane/virtio-blk.o
CC mipsel-linux-user/accel/tcg/translate-all.o
CC nios2-softmmu/hw/core/generic-loader.o
CC xtensaeb-softmmu/accel/tcg/cputlb.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC s390x-softmmu/hw/9pfs/virtio-9p-device.o
CC nios2-softmmu/hw/core/null-machine.o
CC x86_64-softmmu/hw/9pfs/virtio-9p-device.o
CC sparc-softmmu/accel/stubs/hax-stub.o
CC ppcemb-softmmu/hw/block/virtio-blk.o
CC mipsel-softmmu/hw/core/generic-loader.o
CC s390x-linux-user/linux-user/main.o
CC s390x-linux-user/linux-user/syscall.o
CC sparc-softmmu/accel/stubs/hvf-stub.o
CC cris-softmmu/accel/tcg/tcg-runtime-gvec.o
CC sparc-softmmu/accel/stubs/kvm-stub.o
CC sparc64-softmmu/accel/tcg/cpu-exec.o
CC alpha-softmmu/accel/tcg/tcg-runtime.o
CC sparc-softmmu/accel/tcg/tcg-all.o
CC xtensaeb-softmmu/accel/tcg/tcg-runtime.o
CC nios2-softmmu/hw/intc/nios2_iic.o
CC sparc64-softmmu/accel/tcg/cpu-exec-common.o
CC arm-softmmu/accel/tcg/tcg-runtime.o
CC arm-softmmu/accel/tcg/tcg-runtime-gvec.o
CC x86_64-softmmu/hw/block/virtio-blk.o
CC xtensa-softmmu/hw/xtensa/sim.o
CC mips-softmmu/hw/char/virtio-serial-bus.o
CC mipsel-linux-user/accel/tcg/translator.o
CC alpha-softmmu/accel/tcg/tcg-runtime-gvec.o
CC ppc64-softmmu/accel/tcg/translator.o
CC aarch64-softmmu/accel/stubs/hax-stub.o
CC aarch64-softmmu/accel/stubs/hvf-stub.o
CC tricore-softmmu/hw/core/null-machine.o
CC mipsel-linux-user/accel/tcg/user-exec.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC i386-softmmu/accel/tcg/tcg-runtime.o
CC sh4eb-softmmu/accel/tcg/cpu-exec.o
CC microblaze-softmmu/accel/accel.o
CC or1k-softmmu/migration/ram.o
CC moxie-softmmu/accel/tcg/cpu-exec.o
CC aarch64-softmmu/accel/stubs/kvm-stub.o
CC mipsel-softmmu/hw/core/null-machine.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mipsel-softmmu/hw/display/vga.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC mipsel-linux-user/accel/tcg/user-exec-stub.o
CC lm32-softmmu/accel/tcg/tcg-runtime.o
CC alpha-softmmu/accel/tcg/cpu-exec.o
CC sparc-softmmu/accel/tcg/cputlb.o
CC sparc64-softmmu/accel/tcg/translate-all.o
CC sparc64-softmmu/accel/tcg/translator.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC unicore32-softmmu/accel/tcg/tcg-runtime-gvec.o
Preprocessed source stored into /tmp/ccB26PzQ.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC xtensaeb-softmmu/accel/tcg/tcg-runtime-gvec.o
CC moxie-softmmu/accel/tcg/cpu-exec-common.o
CC mips64-softmmu/hw/char/virtio-serial-bus.o
CC sparc-softmmu/accel/tcg/tcg-runtime.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC sparc-softmmu/accel/tcg/tcg-runtime-gvec.o
CC s390x-softmmu/hw/block/virtio-blk.o
make: *** [subdir-sh4-softmmu] Error 2
CC ppc-softmmu/accel/tcg/tcg-runtime.o
CC lm32-softmmu/accel/tcg/tcg-runtime-gvec.o
CC microblazeel-softmmu/accel/tcg/translator.o
CC mips-softmmu/hw/core/generic-loader.o
CC xtensaeb-softmmu/accel/tcg/cpu-exec.o
CC ppc64-softmmu/hw/9pfs/virtio-9p-device.o
CC microblazeel-softmmu/hw/core/generic-loader.o
CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o
CC xtensaeb-softmmu/accel/tcg/cpu-exec-common.o
CC aarch64-softmmu/accel/tcg/tcg-all.o
CC microblazeel-softmmu/hw/core/null-machine.o
CC sh4eb-softmmu/accel/tcg/cpu-exec-common.o
CC ppcemb-softmmu/hw/block/dataplane/virtio-blk.o
CC s390x-softmmu/hw/block/dataplane/virtio-blk.o
CC microblaze-softmmu/accel/stubs/hax-stub.o
CC mips-softmmu/hw/core/null-machine.o
CC ppc-softmmu/accel/tcg/tcg-runtime-gvec.o
CC x86_64-softmmu/hw/char/virtio-serial-bus.o
Preprocessed source stored into /tmp/ccvhqd93.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC microblazeel-softmmu/hw/misc/mmio_interface.o
CC sh4eb-softmmu/accel/tcg/translate-all.o
CC mips64el-softmmu/migration/ram.o
CC ppc-softmmu/accel/tcg/cpu-exec.o
CC xtensaeb-softmmu/accel/tcg/translate-all.o
CC microblazeel-softmmu/hw/net/xilinx_ethlite.o
CC microblaze-softmmu/accel/stubs/hvf-stub.o
CC arm-softmmu/accel/tcg/cpu-exec.o
Preprocessed source stored into /tmp/ccc7ki8M.out file, please attach this to your bugreport.
CC alpha-softmmu/accel/tcg/cpu-exec-common.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC microblaze-softmmu/accel/stubs/kvm-stub.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC ppc-softmmu/accel/tcg/cpu-exec-common.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC sh4eb-softmmu/accel/tcg/translator.o
CC microblazeel-softmmu/hw/net/vhost_net.o
CC xtensa-softmmu/hw/xtensa/xtfpga.o
CC xtensaeb-softmmu/accel/tcg/translator.o
CC moxie-softmmu/accel/tcg/translate-all.o
CC ppc-softmmu/accel/tcg/translate-all.o
CC sparc64-softmmu/hw/9pfs/virtio-9p-device.o
CC xtensaeb-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/accel/tcg/cputlb.o
CC or1k-softmmu/accel/accel.o
CC xtensaeb-softmmu/hw/core/null-machine.o
CC tricore-softmmu/hw/misc/mmio_interface.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC alpha-softmmu/accel/tcg/translate-all.o
CC lm32-softmmu/accel/tcg/cpu-exec.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC aarch64-softmmu/accel/tcg/tcg-runtime.o
CC sh4eb-softmmu/hw/9pfs/virtio-9p-device.o
CC nios2-softmmu/hw/misc/mmio_interface.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC m68k-softmmu/accel/tcg/cpu-exec.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC alpha-softmmu/accel/tcg/translator.o
CC ppc64-softmmu/hw/block/virtio-blk.o
CC ppcemb-softmmu/hw/char/virtio-serial-bus.o
CC sh4eb-softmmu/hw/block/tc58128.o
CC moxie-softmmu/accel/tcg/translator.o
CC ppc-softmmu/accel/tcg/translator.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC cris-softmmu/accel/tcg/cpu-exec.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC alpha-softmmu/hw/9pfs/virtio-9p-device.o
CC s390x-softmmu/hw/char/virtio-serial-bus.o
CC xtensa-softmmu/target/xtensa/xtensa-semi.o
CC arm-softmmu/accel/tcg/cpu-exec-common.o
CC sh4eb-softmmu/hw/block/virtio-blk.o
CC mips64el-softmmu/accel/accel.o
CC sparc-softmmu/accel/tcg/cpu-exec.o
CC ppc-softmmu/hw/9pfs/virtio-9p-device.o
CC sparc-softmmu/accel/tcg/cpu-exec-common.o
CC xtensa-softmmu/target/xtensa/core-dc232b.o
CC xtensaeb-softmmu/hw/misc/mmio_interface.o
Preprocessed source stored into /tmp/ccN3BYDR.out file, please attach this to your bugreport.
CC xtensa-softmmu/target/xtensa/core-dc233c.o
Preprocessed source stored into /tmp/cc9K6dl8.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC arm-softmmu/accel/tcg/translate-all.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC m68k-softmmu/accel/tcg/cpu-exec-common.o
CC ppc-softmmu/hw/block/virtio-blk.o
CC xtensa-softmmu/target/xtensa/core-fsf.o
CC arm-softmmu/accel/tcg/translator.o
CC s390x-softmmu/hw/char/terminal3270.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC microblaze-softmmu/accel/tcg/tcg-all.o
CC sh4eb-softmmu/hw/block/dataplane/virtio-blk.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
make: *** [subdir-nios2-softmmu] Error 2
CC ppcemb-softmmu/hw/core/generic-loader.o
CC i386-softmmu/accel/tcg/tcg-runtime-gvec.o
CC or1k-softmmu/accel/stubs/hax-stub.o
CC mips-softmmu/hw/display/vga.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC moxie-softmmu/hw/core/generic-loader.o
CC unicore32-softmmu/accel/tcg/cpu-exec.o
CC ppc-softmmu/hw/block/dataplane/virtio-blk.o
CC sparc64-softmmu/hw/block/virtio-blk.o
Preprocessed source stored into /tmp/ccFmJRox.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
Preprocessed source stored into /tmp/ccYCVjRx.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc-softmmu/accel/tcg/translate-all.o
CC ppc-softmmu/hw/char/virtio-serial-bus.o
CC i386-softmmu/accel/tcg/cpu-exec.o
CC sh4eb-softmmu/hw/char/sh_serial.o
CC ppc-softmmu/hw/core/generic-loader.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC m68k-softmmu/accel/tcg/translate-all.o
make: *** [subdir-mipsel-linux-user] Error 2
CC m68k-softmmu/accel/tcg/translator.o
CC x86_64-softmmu/hw/core/generic-loader.o
CC sh4eb-softmmu/hw/char/virtio-serial-bus.o
CC or1k-softmmu/accel/stubs/hvf-stub.o
CC aarch64-softmmu/accel/tcg/tcg-runtime-gvec.o
CC xtensaeb-softmmu/hw/net/vhost_net.o
CC mips64el-softmmu/accel/stubs/hax-stub.o
CC tricore-softmmu/hw/net/vhost_net.o
CC i386-softmmu/accel/tcg/cpu-exec-common.o
Preprocessed source stored into /tmp/ccKsH5ik.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppc-softmmu/hw/core/null-machine.o
CC microblazeel-softmmu/hw/net/rocker/qmp-norocker.o
make: *** [subdir-mips64-softmmu] Error 2
CC x86_64-softmmu/hw/core/null-machine.o
CC sparc64-softmmu/hw/block/dataplane/virtio-blk.o
CC m68k-softmmu/hw/char/mcf_uart.o
CC or1k-softmmu/accel/stubs/kvm-stub.o
CC microblazeel-softmmu/hw/vfio/common.o
CC microblaze-softmmu/accel/tcg/cputlb.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC microblazeel-softmmu/hw/vfio/platform.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC ppc-softmmu/hw/display/sm501.o
CC alpha-softmmu/hw/block/virtio-blk.o
CC sparc64-softmmu/hw/char/virtio-serial-bus.o
CC lm32-softmmu/accel/tcg/cpu-exec-common.o
CC ppcemb-softmmu/hw/core/null-machine.o
CC sparc64-softmmu/hw/core/generic-loader.o
CC sparc-softmmu/accel/tcg/translator.o
CC arm-softmmu/hw/9pfs/virtio-9p-device.o
make: *** [subdir-tricore-softmmu] Error 2
CC ppc64-softmmu/hw/block/dataplane/virtio-blk.o
CC xtensaeb-softmmu/hw/net/rocker/qmp-norocker.o
CC moxie-softmmu/hw/core/null-machine.o
CC sparc-softmmu/hw/core/generic-loader.o
CC ppc64-softmmu/hw/char/spapr_vty.o
CC microblazeel-softmmu/hw/vfio/spapr.o
CC sh4eb-softmmu/hw/core/generic-loader.o
CC or1k-softmmu/accel/tcg/tcg-all.o
CC x86_64-softmmu/hw/display/vga.o
CC sparc-softmmu/hw/core/null-machine.o
CC ppc-softmmu/hw/display/vga.o
CC xtensaeb-softmmu/hw/vfio/common.o
CC m68k-softmmu/hw/core/generic-loader.o
CC alpha-softmmu/hw/block/dataplane/virtio-blk.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC ppc-softmmu/hw/display/virtio-gpu.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC sh4eb-softmmu/hw/core/null-machine.o
CC or1k-softmmu/accel/tcg/cputlb.o
CC microblaze-softmmu/accel/tcg/tcg-runtime.o
CC unicore32-softmmu/accel/tcg/cpu-exec-common.o
CC alpha-softmmu/hw/char/virtio-serial-bus.o
CC microblazeel-softmmu/hw/microblaze/petalogix_s3adsp1800_mmu.o
CC lm32-softmmu/accel/tcg/translate-all.o
CC aarch64-softmmu/accel/tcg/cpu-exec.o
CC moxie-softmmu/hw/display/vga.o
CC or1k-softmmu/accel/tcg/tcg-runtime.o
CC ppc64-softmmu/hw/char/virtio-serial-bus.o
CC sh4eb-softmmu/hw/display/sm501.o
CC x86_64-softmmu/hw/display/virtio-gpu.o
CC m68k-softmmu/hw/core/null-machine.o
CC mips-softmmu/hw/display/virtio-gpu.o
CC moxie-softmmu/hw/misc/mmio_interface.o
CC microblaze-softmmu/accel/tcg/tcg-runtime-gvec.o
CC i386-softmmu/accel/tcg/translate-all.o
CC or1k-softmmu/accel/tcg/tcg-runtime-gvec.o
CC sparc-softmmu/hw/display/tcx.o
CC i386-softmmu/accel/tcg/translator.o
CC sh4eb-softmmu/hw/display/vga.o
CC sh4eb-softmmu/hw/display/virtio-gpu.o
CC arm-softmmu/hw/adc/stm32f2xx_adc.o
CC lm32-softmmu/accel/tcg/translator.o
make: *** [subdir-s390x-softmmu] Error 2
CC xtensaeb-softmmu/hw/vfio/platform.o
CC mips64el-softmmu/accel/stubs/hvf-stub.o
CC arm-softmmu/hw/block/virtio-blk.o
Preprocessed source stored into /tmp/ccCEY5j5.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC moxie-softmmu/hw/net/vhost_net.o
CC m68k-softmmu/hw/misc/mmio_interface.o
Preprocessed source stored into /tmp/cciSGNKm.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppcemb-softmmu/hw/display/sm501.o
CC sh4eb-softmmu/hw/display/virtio-gpu-3d.o
CC sh4eb-softmmu/hw/display/virtio-gpu-pci.o
Preprocessed source stored into /tmp/ccC0dGbV.out file, please attach this to your bugreport.
CC sh4eb-softmmu/hw/intc/sh_intc.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc64-softmmu/hw/core/null-machine.o
CC aarch64-softmmu/accel/tcg/cpu-exec-common.o
Preprocessed source stored into /tmp/cc3StA4x.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64el-softmmu/accel/stubs/kvm-stub.o
CC m68k-softmmu/hw/net/mcf_fec.o
CC sparc64-softmmu/hw/display/vga.o
CC moxie-softmmu/hw/net/rocker/qmp-norocker.o
make: *** [subdir-mipsel-softmmu] Error 2
CC moxie-softmmu/hw/timer/mc146818rtc.o
CC moxie-softmmu/hw/vfio/common.o
CC mips64el-softmmu/accel/tcg/tcg-all.o
CC i386-softmmu/hw/9pfs/virtio-9p-device.o
CC lm32-softmmu/hw/core/generic-loader.o
CC alpha-softmmu/hw/core/generic-loader.o
CC sparc-softmmu/hw/display/cg3.o
CC alpha-softmmu/hw/core/null-machine.o
CC or1k-softmmu/accel/tcg/cpu-exec.o
CC cris-softmmu/accel/tcg/cpu-exec-common.o
CC arm-softmmu/hw/block/dataplane/virtio-blk.o
CC sh4eb-softmmu/hw/misc/ivshmem.o
CC mips64el-softmmu/accel/tcg/cputlb.o
CC sparc-softmmu/hw/intc/grlib_irqmp.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC moxie-softmmu/hw/vfio/platform.o
CC mips64el-softmmu/accel/tcg/tcg-runtime.o
CC unicore32-softmmu/accel/tcg/translate-all.o
CC ppc-softmmu/hw/display/virtio-gpu-3d.o
CC moxie-softmmu/hw/vfio/spapr.o
CC moxie-softmmu/hw/moxie/moxiesim.o
CC m68k-softmmu/hw/net/vhost_net.o
CC moxie-softmmu/target/moxie/translate.o
CC arm-softmmu/hw/char/exynos4210_uart.o
CC ppc64-softmmu/hw/core/generic-loader.o
CC sparc64-softmmu/hw/display/virtio-gpu.o
CC sh4eb-softmmu/hw/misc/mmio_interface.o
CC aarch64-softmmu/accel/tcg/translate-all.o
CC microblaze-softmmu/accel/tcg/cpu-exec.o
CC lm32-softmmu/hw/core/null-machine.o
Preprocessed source stored into /tmp/cci2mp0M.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC i386-softmmu/hw/block/virtio-blk.o
CC or1k-softmmu/accel/tcg/cpu-exec-common.o
CC mips64el-softmmu/accel/tcg/tcg-runtime-gvec.o
CC sh4eb-softmmu/hw/net/virtio-net.o
Preprocessed source stored into /tmp/ccraiGVn.out file, please attach this to your bugreport.
CC cris-softmmu/accel/tcg/translate-all.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC moxie-softmmu/target/moxie/helper.o
Preprocessed source stored into /tmp/ccx3sc5o.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC microblaze-softmmu/accel/tcg/cpu-exec-common.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC alpha-softmmu/hw/display/vga.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC alpha-softmmu/hw/display/virtio-gpu.o
CC sparc-softmmu/hw/misc/eccmemctl.o
CC arm-softmmu/hw/char/omap_uart.o
CC lm32-softmmu/hw/input/milkymist-softusb.o
CC microblaze-softmmu/accel/tcg/translate-all.o
CC ppc-softmmu/hw/display/virtio-gpu-pci.o
CC i386-softmmu/hw/block/dataplane/virtio-blk.o
CC xtensaeb-softmmu/hw/vfio/spapr.o
CC sparc-softmmu/hw/misc/slavio_misc.o
CC moxie-softmmu/target/moxie/machine.o
CC cris-softmmu/accel/tcg/translator.o
CC unicore32-softmmu/accel/tcg/translator.o
CC sparc-softmmu/hw/misc/mmio_interface.o
CC cris-softmmu/hw/core/generic-loader.o
CC lm32-softmmu/hw/misc/milkymist-hpdmc.o
CC lm32-softmmu/hw/misc/milkymist-pfpu.o
CC i386-softmmu/hw/char/virtio-serial-bus.o
CC lm32-softmmu/hw/misc/mmio_interface.o
Preprocessed source stored into /tmp/ccHyj63V.out file, please attach this to your bugreport.
CC cris-softmmu/hw/core/null-machine.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC xtensaeb-softmmu/hw/xtensa/pic_cpu.o
make: *** [subdir-microblazeel-softmmu] Error 2
CC or1k-softmmu/accel/tcg/translate-all.o
CC i386-softmmu/hw/core/generic-loader.o
make: *** [subdir-m68k-softmmu] Error 2
CC arm-softmmu/hw/char/digic-uart.o
CC mips64el-softmmu/accel/tcg/cpu-exec.o
CC moxie-softmmu/target/moxie/cpu.o
CC moxie-softmmu/target/moxie/mmu.o
CC lm32-softmmu/hw/net/milkymist-minimac2.o
CC lm32-softmmu/hw/net/vhost_net.o
CC unicore32-softmmu/hw/core/generic-loader.o
CC or1k-softmmu/accel/tcg/translator.o
CC microblaze-softmmu/accel/tcg/translator.o
CC i386-softmmu/hw/core/null-machine.o
CC or1k-softmmu/hw/core/generic-loader.o
CC i386-softmmu/hw/display/vga.o
CC mips64el-softmmu/accel/tcg/cpu-exec-common.o
CC ppc-softmmu/hw/i2c/ppc4xx_i2c.o
CC or1k-softmmu/hw/core/null-machine.o
CC cris-softmmu/hw/misc/mmio_interface.o
GEN trace/generated-helpers.c
CC sparc-softmmu/hw/net/vhost_net.o
make: *** [subdir-ppc64-softmmu] Error 2
CC or1k-softmmu/hw/intc/ompic.o
CC i386-softmmu/hw/display/virtio-gpu.o
CC xtensaeb-softmmu/hw/xtensa/sim.o
CC moxie-softmmu/trace/control-target.o
CC alpha-softmmu/hw/display/virtio-gpu-3d.o
CC lm32-softmmu/hw/net/rocker/qmp-norocker.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC unicore32-softmmu/hw/core/null-machine.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Preprocessed source stored into /tmp/cc6MDk9L.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC cris-softmmu/hw/net/etraxfs_eth.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC unicore32-softmmu/hw/misc/mmio_interface.o
CC mips64el-softmmu/accel/tcg/translate-all.o
CC microblaze-softmmu/hw/core/generic-loader.o
CC xtensaeb-softmmu/hw/xtensa/xtfpga.o
CC i386-softmmu/hw/display/virtio-gpu-3d.o
make: *** [subdir-aarch64_be-linux-user] Error 2
CC microblaze-softmmu/hw/core/null-machine.o
CC microblaze-softmmu/hw/misc/mmio_interface.o
CC ppc-softmmu/hw/intc/openpic_kvm.o
CC i386-softmmu/hw/display/virtio-gpu-pci.o
CC ppc-softmmu/hw/misc/ivshmem.o
CC microblaze-softmmu/hw/net/xilinx_ethlite.o
CC unicore32-softmmu/hw/net/vhost_net.o
CC xtensaeb-softmmu/target/xtensa/xtensa-semi.o
CC microblaze-softmmu/hw/net/vhost_net.o
CC cris-softmmu/hw/net/vhost_net.o
CC i386-softmmu/hw/display/virtio-vga.o
CC lm32-softmmu/hw/sd/milkymist-memcard.o
CC ppc-softmmu/hw/misc/mmio_interface.o
CC cris-softmmu/hw/net/rocker/qmp-norocker.o
CC alpha-softmmu/hw/display/virtio-gpu-pci.o
CC i386-softmmu/hw/intc/apic.o
CC or1k-softmmu/hw/misc/mmio_interface.o
CC unicore32-softmmu/hw/net/rocker/qmp-norocker.o
CC arm-softmmu/hw/char/stm32f2xx_usart.o
CC aarch64-softmmu/accel/tcg/translator.o
CC cris-softmmu/hw/vfio/common.o
CC sparc-softmmu/hw/net/rocker/qmp-norocker.o
CC unicore32-softmmu/hw/vfio/common.o
CC xtensaeb-softmmu/target/xtensa/core-dc232b.o
CC i386-softmmu/hw/intc/apic_common.o
CC microblaze-softmmu/hw/net/rocker/qmp-norocker.o
Preprocessed source stored into /tmp/ccMtIJ6V.out file, please attach this to your bugreport.
CC or1k-softmmu/hw/net/vhost_net.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC aarch64-softmmu/hw/9pfs/virtio-9p-device.o
CC or1k-softmmu/hw/vfio/common.o
CC or1k-softmmu/hw/net/rocker/qmp-norocker.o
CC ppc-softmmu/hw/net/xilinx_ethlite.o
CC lm32-softmmu/hw/vfio/common.o
make: *** [subdir-ppcemb-softmmu] Error 2
CC mips64el-softmmu/accel/tcg/translator.o
CC microblaze-softmmu/hw/vfio/common.o
CC or1k-softmmu/hw/vfio/platform.o
CC mips64el-softmmu/hw/9pfs/virtio-9p-device.o
CC ppc-softmmu/hw/net/virtio-net.o
CC microblaze-softmmu/hw/vfio/platform.o
Preprocessed source stored into /tmp/ccyqwOGy.out file, please attach this to your bugreport.
CC i386-softmmu/hw/intc/ioapic.o
CC microblaze-softmmu/hw/vfio/spapr.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc-softmmu/hw/vfio/common.o
CC unicore32-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o
CC i386-softmmu/hw/isa/lpc_ich9.o
CC lm32-softmmu/hw/vfio/platform.o
CC microblaze-softmmu/hw/microblaze/petalogix_s3adsp1800_mmu.o
CC xtensaeb-softmmu/target/xtensa/core-dc233c.o
make: *** [subdir-mips-softmmu] Error 2
CC or1k-softmmu/hw/vfio/spapr.o
CC unicore32-softmmu/hw/vfio/spapr.o
CC aarch64-softmmu/hw/block/virtio-blk.o
CC xtensaeb-softmmu/target/xtensa/core-fsf.o
CC mips64el-softmmu/hw/block/virtio-blk.o
CC mips64el-softmmu/hw/block/dataplane/virtio-blk.o
CC xtensaeb-softmmu/target/xtensa/monitor.o
CC arm-softmmu/hw/char/bcm2835_aux.o
CC i386-softmmu/hw/misc/ivshmem.o
CC mips64el-softmmu/hw/char/virtio-serial-bus.o
CC ppc-softmmu/hw/net/vhost_net.o
CC microblaze-softmmu/hw/microblaze/petalogix_ml605_mmu.o
CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o
Preprocessed source stored into /tmp/ccSWuAL0.out file, please attach this to your bugreport.
CC microblaze-softmmu/hw/microblaze/boot.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC arm-softmmu/hw/char/virtio-serial-bus.o
CC sparc-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/hw/char/exynos4210_uart.o
CC unicore32-softmmu/hw/unicore32/puv3.o
CC or1k-softmmu/hw/openrisc/pic_cpu.o
Preprocessed source stored into /tmp/ccNQICQz.out file, please attach this to your bugreport.
CC microblaze-softmmu/target/microblaze/translate.o
CC i386-softmmu/hw/misc/pvpanic.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC arm-softmmu/hw/core/generic-loader.o
CC lm32-softmmu/hw/vfio/spapr.o
CC arm-softmmu/hw/core/null-machine.o
CC lm32-softmmu/hw/lm32/lm32_boards.o
CC microblaze-softmmu/target/microblaze/op_helper.o
CC or1k-softmmu/hw/openrisc/cputimer.o
CC or1k-softmmu/hw/openrisc/openrisc_sim.o
Preprocessed source stored into /tmp/ccxevd5f.out file, please attach this to your bugreport.
CC or1k-softmmu/target/openrisc/machine.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64el-softmmu/hw/core/generic-loader.o
CC lm32-softmmu/hw/lm32/milkymist.o
CC i386-softmmu/hw/misc/mmio_interface.o
CC ppc-softmmu/hw/net/fsl_etsec/etsec.o
CC aarch64-softmmu/hw/char/omap_uart.o
CC ppc-softmmu/hw/net/fsl_etsec/registers.o
CC aarch64-softmmu/hw/char/digic-uart.o
CC ppc-softmmu/hw/net/fsl_etsec/rings.o
CC ppc-softmmu/hw/net/fsl_etsec/miim.o
CC aarch64-softmmu/hw/char/stm32f2xx_usart.o
CC i386-softmmu/hw/net/virtio-net.o
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC aarch64-softmmu/hw/char/bcm2835_aux.o
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC aarch64-softmmu/hw/char/virtio-serial-bus.o
make: *** [subdir-ppc64-linux-user] Error 2
CC mips64el-softmmu/hw/core/null-machine.o
CC or1k-softmmu/target/openrisc/cpu.o
Preprocessed source stored into /tmp/ccVMSTsN.out file, please attach this to your bugreport.
CC i386-softmmu/hw/net/vhost_net.o
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC or1k-softmmu/target/openrisc/exception.o
CC aarch64-softmmu/hw/core/generic-loader.o
CC sparc-softmmu/hw/vfio/spapr.o
CC sparc-softmmu/hw/sparc/sun4m_iommu.o
CC or1k-softmmu/target/openrisc/interrupt.o
CC aarch64-softmmu/hw/core/null-machine.o
make: *** [subdir-x86_64-softmmu] Error 2
CC ppc-softmmu/hw/scsi/virtio-scsi.o
CC aarch64-softmmu/hw/cpu/arm11mpcore.o
CC microblaze-softmmu/target/microblaze/helper.o
CC or1k-softmmu/target/openrisc/mmu.o
CC sparc-softmmu/hw/sparc/sun4m.o
CC mips64el-softmmu/hw/display/vga.o
CC aarch64-softmmu/hw/cpu/realview_mpcore.o
CC i386-softmmu/hw/scsi/virtio-scsi.o
CC mips64el-softmmu/hw/display/virtio-gpu.o
CC ppc-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC i386-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC ppc-softmmu/hw/scsi/vhost-scsi-common.o
CC aarch64-softmmu/hw/cpu/a9mpcore.o
CC microblaze-softmmu/target/microblaze/cpu.o
CC i386-softmmu/hw/scsi/vhost-scsi-common.o
CC i386-softmmu/hw/scsi/vhost-scsi.o
CC microblaze-softmmu/target/microblaze/gdbstub.o
CC mips64el-softmmu/hw/display/virtio-gpu-3d.o
CC or1k-softmmu/target/openrisc/translate.o
CC microblaze-softmmu/target/microblaze/mmu.o
CC i386-softmmu/hw/scsi/vhost-user-scsi.o
CC i386-softmmu/hw/timer/mc146818rtc.o
CC sparc-softmmu/hw/sparc/leon3.o
CC aarch64-softmmu/hw/cpu/a15mpcore.o
make: *** [subdir-mipsn32-linux-user] Error 2
CC or1k-softmmu/target/openrisc/exception_helper.o
GEN trace/generated-helpers.c
CC ppc-softmmu/hw/scsi/vhost-scsi.o
CC i386-softmmu/hw/vfio/common.o
CC microblaze-softmmu/trace/control-target.o
CC aarch64-softmmu/hw/display/omap_dss.o
make: *** [subdir-sh4eb-softmmu] Error 2
CC sparc-softmmu/target/sparc/machine.o
CC ppc-softmmu/hw/scsi/vhost-user-scsi.o
CC ppc-softmmu/hw/timer/mc146818rtc.o
CC mips64el-softmmu/hw/display/virtio-gpu-pci.o
CC aarch64-softmmu/hw/display/omap_lcdc.o
CC or1k-softmmu/target/openrisc/fpu_helper.o
CC microblaze-softmmu/trace/generated-helpers.o
CC mips64el-softmmu/hw/intc/mips_gic.o
CC mips64el-softmmu/hw/misc/ivshmem.o
CC or1k-softmmu/target/openrisc/interrupt_helper.o
CC aarch64-softmmu/hw/display/pxa2xx_lcd.o
CC or1k-softmmu/target/openrisc/mmu_helper.o
CC sparc-softmmu/target/sparc/monitor.o
CC i386-softmmu/hw/vfio/pci.o
CC aarch64-softmmu/hw/display/bcm2835_fb.o
CC i386-softmmu/hw/vfio/pci-quirks.o
CC sparc-softmmu/target/sparc/translate.o
CC aarch64-softmmu/hw/display/vga.o
make: *** [subdir-moxie-softmmu] Error 2
CC aarch64-softmmu/hw/display/virtio-gpu.o
CC mips64el-softmmu/hw/misc/mips_cmgcr.o
CC i386-softmmu/hw/vfio/platform.o
CC i386-softmmu/hw/vfio/spapr.o
CC ppc-softmmu/hw/vfio/common.o
CC aarch64-softmmu/hw/display/virtio-gpu-3d.o
CC mips64el-softmmu/hw/misc/mips_cpc.o
CC i386-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/display/virtio-gpu-pci.o
CC sparc-softmmu/target/sparc/helper.o
Preprocessed source stored into /tmp/ccBuIAPU.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64el-softmmu/hw/misc/mips_itu.o
CC aarch64-softmmu/hw/display/xlnx_dp.o
CC aarch64-softmmu/hw/display/dpcd.o
CC sparc-softmmu/target/sparc/cpu.o
CC mips64el-softmmu/hw/misc/mmio_interface.o
CC aarch64-softmmu/hw/dma/xlnx_dpdma.o
CC mips64el-softmmu/hw/net/virtio-net.o
make: *** [subdir-cris-softmmu] Error 2
CC i386-softmmu/hw/virtio/virtio-balloon.o
CC sparc-softmmu/target/sparc/fop_helper.o
CC sparc-softmmu/target/sparc/cc_helper.o
CC mips64el-softmmu/hw/net/vhost_net.o
Preprocessed source stored into /tmp/ccYXuAxR.out file, please attach this to your bugreport.
CC or1k-softmmu/target/openrisc/sys_helper.o
make: *** [subdir-sparc64-softmmu] Error 2
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC i386-softmmu/hw/virtio/vhost.o
CC or1k-softmmu/target/openrisc/gdbstub.o
CC i386-softmmu/hw/virtio/vhost-backend.o
CC aarch64-softmmu/hw/dma/omap_dma.o
CC i386-softmmu/hw/virtio/vhost-user.o
CC mips64el-softmmu/hw/scsi/virtio-scsi.o
CC aarch64-softmmu/hw/dma/soc_dma.o
GEN trace/generated-helpers.c
CC or1k-softmmu/trace/control-target.o
CC i386-softmmu/hw/virtio/vhost-vsock.o
CC mips64el-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC aarch64-softmmu/hw/dma/pxa2xx_dma.o
CC mips64el-softmmu/hw/scsi/vhost-scsi-common.o
CC i386-softmmu/hw/virtio/virtio-crypto.o
CC aarch64-softmmu/hw/dma/bcm2835_dma.o
CC mips64el-softmmu/hw/scsi/vhost-scsi.o
CC aarch64-softmmu/hw/gpio/omap_gpio.o
CC i386-softmmu/hw/virtio/virtio-crypto-pci.o
CC mips64el-softmmu/hw/scsi/vhost-user-scsi.o
CC mips64el-softmmu/hw/timer/mips_gictimer.o
CC mips64el-softmmu/hw/timer/mc146818rtc.o
CC i386-softmmu/hw/i386/multiboot.o
CC aarch64-softmmu/hw/gpio/imx_gpio.o
CC aarch64-softmmu/hw/gpio/bcm2835_gpio.o
CC aarch64-softmmu/hw/i2c/omap_i2c.o
CC or1k-softmmu/trace/generated-helpers.o
CC mips64el-softmmu/hw/vfio/common.o
CC i386-softmmu/hw/i386/pc.o
CC mips64el-softmmu/hw/vfio/pci.o
CC mips64el-softmmu/hw/vfio/pci-quirks.o
CC aarch64-softmmu/hw/input/pxa2xx_keypad.o
CC aarch64-softmmu/hw/input/tsc210x.o
CC mips64el-softmmu/hw/vfio/platform.o
make: *** [subdir-lm32-softmmu] Error 2
CC mips64el-softmmu/hw/vfio/spapr.o
CC mips64el-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/intc/armv7m_nvic.o
CC i386-softmmu/hw/i386/pc_piix.o
make: *** [subdir-arm-softmmu] Error 2
CC aarch64-softmmu/hw/intc/exynos4210_gic.o
CC mips64el-softmmu/hw/virtio/virtio-balloon.o
CC mips64el-softmmu/hw/virtio/vhost.o
make: *** [subdir-unicore32-softmmu] Error 2
CC aarch64-softmmu/hw/intc/exynos4210_combiner.o
CC mips64el-softmmu/hw/virtio/vhost-backend.o
make: *** [subdir-xtensa-softmmu] Error 2
CC aarch64-softmmu/hw/intc/omap_intc.o
CC i386-softmmu/hw/i386/pc_q35.o
CC mips64el-softmmu/hw/virtio/vhost-user.o
CC i386-softmmu/hw/i386/pc_sysfw.o
make: *** [subdir-alpha-softmmu] Error 2
CC i386-softmmu/hw/i386/x86-iommu.o
CC aarch64-softmmu/hw/intc/bcm2835_ic.o
CC mips64el-softmmu/hw/virtio/vhost-vsock.o
CC mips64el-softmmu/hw/virtio/virtio-crypto.o
CC mips64el-softmmu/hw/virtio/virtio-crypto-pci.o
CC mips64el-softmmu/hw/mips/mips_r4k.o
CC mips64el-softmmu/hw/mips/mips_malta.o
CC i386-softmmu/hw/i386/intel_iommu.o
CC i386-softmmu/hw/i386/amd_iommu.o
CC aarch64-softmmu/hw/intc/bcm2836_control.o
CC mips64el-softmmu/hw/mips/mips_mipssim.o
CC i386-softmmu/hw/i386/vmport.o
CC mips64el-softmmu/hw/mips/addr.o
CC mips64el-softmmu/hw/mips/mips_int.o
CC i386-softmmu/hw/i386/vmmouse.o
CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o
CC i386-softmmu/hw/i386/kvmvapic.o
CC i386-softmmu/hw/i386/acpi-build.o
CC i386-softmmu/target/i386/helper.o
CC i386-softmmu/target/i386/cpu.o
CC aarch64-softmmu/hw/intc/aspeed_vic.o
CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o
CC mips64el-softmmu/hw/mips/mips_jazz.o
CC mips64el-softmmu/hw/mips/mips_fulong2e.o
CC i386-softmmu/target/i386/gdbstub.o
CC mips64el-softmmu/hw/mips/gt64xxx_pci.o
CC aarch64-softmmu/hw/misc/ivshmem.o
CC i386-softmmu/target/i386/xsave_helper.o
CC aarch64-softmmu/hw/misc/arm_sysctl.o
CC aarch64-softmmu/hw/misc/cbus.o
make: *** [subdir-microblazeel-linux-user] Error 2
CC i386-softmmu/target/i386/translate.o
CC i386-softmmu/target/i386/bpt_helper.o
CC i386-softmmu/target/i386/cc_helper.o
CC aarch64-softmmu/hw/misc/exynos4210_pmu.o
CC aarch64-softmmu/hw/misc/exynos4210_clk.o
CC mips64el-softmmu/hw/mips/cps.o
CC aarch64-softmmu/hw/misc/exynos4210_rng.o
CC i386-softmmu/target/i386/excp_helper.o
CC aarch64-softmmu/hw/misc/imx_ccm.o
CC aarch64-softmmu/hw/misc/imx31_ccm.o
CC i386-softmmu/target/i386/fpu_helper.o
CC aarch64-softmmu/hw/misc/imx25_ccm.o
CC mips64el-softmmu/hw/mips/boston.o
CC aarch64-softmmu/hw/misc/imx6_ccm.o
Preprocessed source stored into /tmp/ccHZDEoG.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC i386-softmmu/target/i386/int_helper.o
CC mips64el-softmmu/target/mips/translate.o
CC i386-softmmu/target/i386/mem_helper.o
CC mips64el-softmmu/target/mips/dsp_helper.o
Preprocessed source stored into /tmp/ccQbNyb7.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64el-softmmu/target/mips/op_helper.o
CC mips64el-softmmu/target/mips/lmi_helper.o
CC mips64el-softmmu/target/mips/helper.o
CC mips64el-softmmu/target/mips/cpu.o
CC mips64el-softmmu/target/mips/gdbstub.o
CC mips64el-softmmu/target/mips/msa_helper.o
CC mips64el-softmmu/target/mips/mips-semi.o
CC mips64el-softmmu/target/mips/machine.o
CC mips64el-softmmu/target/mips/cp0_timer.o
GEN trace/generated-helpers.c
CC mips64el-softmmu/trace/control-target.o
CC mips64el-softmmu/trace/generated-helpers.o
make: *** [subdir-sh4-linux-user] Error 2
Preprocessed source stored into /tmp/ccNK60T7.out file, please attach this to your bugreport.
Preprocessed source stored into /tmp/ccFdesQz.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [subdir-ppc-softmmu] Error 2
make: *** [subdir-microblaze-linux-user] Error 2
make: *** [subdir-or1k-softmmu] Error 2
Preprocessed source stored into /tmp/cc8d3Q16.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [subdir-aarch64-softmmu] Error 2
make: *** [subdir-microblaze-softmmu] Error 2
make: *** [subdir-xtensaeb-softmmu] Error 2
make: *** [subdir-sparc-softmmu] Error 2
make: *** [subdir-ppc64le-linux-user] Error 2
make: *** [subdir-s390x-linux-user] Error 2
make: *** [subdir-i386-softmmu] Error 2
make: *** [subdir-mips64el-softmmu] Error 2
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations
2018-01-16 3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
` (27 preceding siblings ...)
2018-01-16 4:27 ` no-reply
@ 2018-01-16 11:59 ` Peter Maydell
2018-01-16 15:50 ` Richard Henderson
28 siblings, 1 reply; 32+ messages in thread
From: Peter Maydell @ 2018-01-16 11:59 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, Fam Zheng
On 16 January 2018 at 03:33, Richard Henderson
<richard.henderson@linaro.org> wrote:
> I think this will be the last revision before queueing for pull.
>
> Peter, the target/arm patches here are primarily for testing,
> without having to go all the way through to SVE. It also shows
> how the generic vector interface ought to be used. I'm happy
> to drop the patches from the tcg pull and feed them through
> target-arm.next, or keep them here as you wish.
I see the ppc gcc that patchew uses doesn't like this:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:
In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26:
internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
Please submit a full bug report,
with preprocessed source if appropriate.
We need to either work around that or update the compiler in patchew's
setup or disable that build before we can merge this, or patchew will
start mailing complaints about every series that's sent to the list...
thanks
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations
2018-01-16 11:59 ` Peter Maydell
@ 2018-01-16 15:50 ` Richard Henderson
2018-01-17 5:36 ` Fam Zheng
0 siblings, 1 reply; 32+ messages in thread
From: Richard Henderson @ 2018-01-16 15:50 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Fam Zheng
On 01/16/2018 03:59 AM, Peter Maydell wrote:
> /var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26:
> internal compiler error: in emit_move_insn, at expr.c:3495
Bah. I remember seeing this myself on the gcc 4.8.x that is the system
compiler on the gcc compile farm machines. I forgot about it because I
immediately changed my path to select gcc 7.x. ;-P
> We need to either work around that or update the compiler in patchew's
> setup or disable that build before we can merge this, or patchew will
> start mailing complaints about every series that's sent to the list...
I can work around it in configure, but it might be worth updating the compiler
as well -- this bug has been fixed for years.
r~
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations
2018-01-16 15:50 ` Richard Henderson
@ 2018-01-17 5:36 ` Fam Zheng
0 siblings, 0 replies; 32+ messages in thread
From: Fam Zheng @ 2018-01-17 5:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: Peter Maydell, QEMU Developers, Fam Zheng
gcc-4.8.5-16.el7_4.1.ppc64le
On Tue, Jan 16, 2018 at 11:50 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 01/16/2018 03:59 AM, Peter Maydell wrote:
>> /var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26:
>> internal compiler error: in emit_move_insn, at expr.c:3495
>
> Bah. I remember seeing this myself on the gcc 4.8.x that is the system
> compiler on the gcc compile farm machines. I forgot about it because I
> immediately changed my path to select gcc 7.x. ;-P
>
>> We need to either work around that or update the compiler in patchew's
>> setup or disable that build before we can merge this, or patchew will
>> start mailing complaints about every series that's sent to the list...
>
> I can work around it in configure, but it might be worth updating the compiler
> as well -- this bug has been fixed for years.
This gcc is the CentOS 7 packaged version and an update (from
gcc-4.8.5-16.el7.ppc64le
to gcc-4.8.5-16.el7_4.1.ppc64le) doesn't fix it.
Fam
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