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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v9 01/26] tcg: Allow multiple word entries into the constant pool
Date: Mon, 15 Jan 2018 19:33:39 -0800	[thread overview]
Message-ID: <20180116033404.31532-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180116033404.31532-1-richard.henderson@linaro.org>

This will be required for storing vector constants.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg-pool.inc.c | 115 +++++++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 93 insertions(+), 22 deletions(-)

diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c
index 8a85131405..0f76e7bee3 100644
--- a/tcg/tcg-pool.inc.c
+++ b/tcg/tcg-pool.inc.c
@@ -22,39 +22,110 @@
 
 typedef struct TCGLabelPoolData {
     struct TCGLabelPoolData *next;
-    tcg_target_ulong data;
     tcg_insn_unit *label;
-    intptr_t addend;
-    int type;
+    int addend  : 32;
+    int rtype   : 16;
+    int nlong   : 16;
+    tcg_target_ulong data[];
 } TCGLabelPoolData;
 
 
-static void new_pool_label(TCGContext *s, tcg_target_ulong data, int type,
-                           tcg_insn_unit *label, intptr_t addend)
+static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype,
+                                        tcg_insn_unit *label, int addend)
 {
-    TCGLabelPoolData *n = tcg_malloc(sizeof(*n));
-    TCGLabelPoolData *i, **pp;
+    TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData)
+                                     + sizeof(tcg_target_ulong) * nlong);
 
-    n->data = data;
     n->label = label;
-    n->type = type;
     n->addend = addend;
+    n->rtype = rtype;
+    n->nlong = nlong;
+    return n;
+}
+
+static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n)
+{
+    TCGLabelPoolData *i, **pp;
+    int nlong = n->nlong;
 
     /* Insertion sort on the pool.  */
-    for (pp = &s->pool_labels; (i = *pp) && i->data < data; pp = &i->next) {
-        continue;
+    for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) {
+        if (nlong > i->nlong) {
+            break;
+        }
+        if (nlong < i->nlong) {
+            continue;
+        }
+        if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) {
+            break;
+        }
     }
     n->next = *pp;
     *pp = n;
 }
 
+/* The "usual" for generic integer code.  */
+static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype,
+                                  tcg_insn_unit *label, int addend)
+{
+    TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend);
+    n->data[0] = d;
+    new_pool_insert(s, n);
+}
+
+/* For v64 or v128, depending on the host.  */
+static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label,
+                               int addend, tcg_target_ulong d0,
+                               tcg_target_ulong d1)
+{
+    TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend);
+    n->data[0] = d0;
+    n->data[1] = d1;
+    new_pool_insert(s, n);
+}
+
+/* For v128 or v256, depending on the host.  */
+static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label,
+                               int addend, tcg_target_ulong d0,
+                               tcg_target_ulong d1, tcg_target_ulong d2,
+                               tcg_target_ulong d3)
+{
+    TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend);
+    n->data[0] = d0;
+    n->data[1] = d1;
+    n->data[2] = d2;
+    n->data[3] = d3;
+    new_pool_insert(s, n);
+}
+
+/* For v256, for 32-bit host.  */
+static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
+                               int addend, tcg_target_ulong d0,
+                               tcg_target_ulong d1, tcg_target_ulong d2,
+                               tcg_target_ulong d3, tcg_target_ulong d4,
+                               tcg_target_ulong d5, tcg_target_ulong d6,
+                               tcg_target_ulong d7)
+{
+    TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend);
+    n->data[0] = d0;
+    n->data[1] = d1;
+    n->data[2] = d2;
+    n->data[3] = d3;
+    n->data[4] = d4;
+    n->data[5] = d5;
+    n->data[6] = d6;
+    n->data[7] = d7;
+    new_pool_insert(s, n);
+}
+
 /* To be provided by cpu/tcg-target.inc.c.  */
 static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
 
 static bool tcg_out_pool_finalize(TCGContext *s)
 {
     TCGLabelPoolData *p = s->pool_labels;
-    tcg_target_ulong d, *a;
+    TCGLabelPoolData *l = NULL;
+    void *a;
 
     if (p == NULL) {
         return true;
@@ -62,24 +133,24 @@ static bool tcg_out_pool_finalize(TCGContext *s)
 
     /* ??? Round up to qemu_icache_linesize, but then do not round
        again when allocating the next TranslationBlock structure.  */
-    a = (void *)ROUND_UP((uintptr_t)s->code_ptr, sizeof(tcg_target_ulong));
+    a = (void *)ROUND_UP((uintptr_t)s->code_ptr,
+                         sizeof(tcg_target_ulong) * p->nlong);
     tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr);
     s->data_gen_ptr = a;
 
-    /* Ensure the first comparison fails.  */
-    d = p->data + 1;
-
     for (; p != NULL; p = p->next) {
-        if (p->data != d) {
-            d = p->data;
-            if (unlikely((void *)a > s->code_gen_highwater)) {
+        size_t size = sizeof(tcg_target_ulong) * p->nlong;
+        if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
+            if (unlikely(a > s->code_gen_highwater)) {
                 return false;
             }
-            *a++ = d;
+            memcpy(a, p->data, size);
+            a += size;
+            l = p;
         }
-        patch_reloc(p->label, p->type, (intptr_t)(a - 1), p->addend);
+        patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend);
     }
 
-    s->code_ptr = (void *)a;
+    s->code_ptr = a;
     return true;
 }
-- 
2.14.3

  reply	other threads:[~2018-01-16  3:34 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-16  3:33 [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations Richard Henderson
2018-01-16  3:33 ` Richard Henderson [this message]
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 02/26] tcg: Add types and basic operations for host vectors Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 03/26] tcg: Standardize integral arguments to expanders Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 04/26] tcg: Add generic vector expanders Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 05/26] tcg: Add generic vector ops for interleave Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 06/26] tcg: Add generic vector ops for constant shifts Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 07/26] tcg: Add generic vector ops for comparisons Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 08/26] tcg: Add generic vector ops for multiplication Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 09/26] tcg: Add generic vector ops for extension Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 10/26] tcg: Add generic helpers for saturating arithmetic Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 11/26] tcg: Loosen vec_gen_op* typecheck rules Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 12/26] tcg: Add generic vector helpers with a scalar immediate operand Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 13/26] tcg: Add generic vector helpers with a scalar variable operand Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 14/26] tcg/optimize: Handle vector opcodes during optimize Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 15/26] target/arm: Align vector registers Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 16/26] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 17/26] target/arm: Use vector infrastructure for aa64 mov/not/neg Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 18/26] target/arm: Use vector infrastructure for aa64 dup/movi Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 19/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 20/26] target/arm: Use vector infrastructure for aa64 constant shifts Richard Henderson
2018-01-16  3:33 ` [Qemu-devel] [PATCH v9 21/26] target/arm: Use vector infrastructure for aa64 compares Richard Henderson
2018-01-16  3:34 ` [Qemu-devel] [PATCH v9 22/26] target/arm: Use vector infrastructure for aa64 multiplies Richard Henderson
2018-01-16  3:34 ` [Qemu-devel] [PATCH v9 23/26] target/arm: Use vector infrastructure for aa64 widening shifts Richard Henderson
2018-01-16  3:34 ` [Qemu-devel] [PATCH v9 24/26] target/arm: Use vector infrastructure for aa64 orr/bic immediate Richard Henderson
2018-01-16  3:34 ` [Qemu-devel] [PATCH v9 25/26] tcg/i386: Add vector operations Richard Henderson
2018-01-16  3:34 ` [Qemu-devel] [PATCH v9 26/26] tcg/aarch64: " Richard Henderson
2018-01-16  4:02 ` [Qemu-devel] [PATCH v9 00/26] tcg: generic " no-reply
2018-01-16  4:27 ` no-reply
2018-01-16 11:59 ` Peter Maydell
2018-01-16 15:50   ` Richard Henderson
2018-01-17  5:36     ` Fam Zheng

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