* [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions
@ 2018-01-14 10:47 Mark Cave-Ayland
2018-01-14 10:47 ` [Qemu-devel] [PATCH 01/11] apb: split simba PCI bridge into hw/pci-bridge/simba.c Mark Cave-Ayland
` (11 more replies)
0 siblings, 12 replies; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
This patchset is the next round of sun4u tidy-ups mostly centered around the
APB (PCI host bridge). In its current form apb.c contains both the PCI host
bridge and the secondary PCI bridge, so we split the PCI bridge into a new
file and move it under hw/pci-bridge.
To order to avoid further confusion between PBM/APB naming I've gone for using
the Sun internal code names, sabre and simba for the two PCI bridges to keep
things consistent.
Finally there are a couple of conversions to trace-events for sabre and the
sparc CPU as used when debugging this patchset. Note that as hw/pci-host is
listed as having no maintainers, I've CCd the PCI bridge maintainers on the
hw/pci-host tracepoint conversion which I hope is reasonable.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland (11):
apb: split simba PCI bridge into hw/pci-bridge/simba.c
simba: rename PBMPCIBridge and QOM types to reflect simba naming
apb: rename APB functions to use sabre prefix
apb: change pbm_pci_host prefix functions to use sabre_pci prefix
apb: QOMify sabre PCI host bridge
apb: rename QOM type from TYPE_APB to TYPE_SABRE
sun4u: rename apb variables and constants
apb: rename apb.c to sabre.c
pci: add trace-events support for hw/pci-host
sabre: convert from SABRE_DPRINTF macro to trace-events
sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace
events
Makefile.objs | 1 +
default-configs/sparc64-softmmu.mak | 3 +-
hw/pci-bridge/Makefile.objs | 2 +
hw/pci-bridge/simba.c | 101 ++++++++++++
hw/pci-host/Makefile.objs | 2 +-
hw/pci-host/{apb.c => sabre.c} | 270 ++++++++++++---------------------
hw/pci-host/trace-events | 11 ++
hw/sparc64/sparc64.c | 85 +++++------
hw/sparc64/sun4u.c | 45 +++---
hw/sparc64/trace-events | 18 +++
include/hw/pci-bridge/simba.h | 38 +++++
include/hw/pci-host/{apb.h => sabre.h} | 26 ++--
12 files changed, 342 insertions(+), 260 deletions(-)
create mode 100644 hw/pci-bridge/simba.c
rename hw/pci-host/{apb.c => sabre.c} (62%)
create mode 100644 hw/pci-host/trace-events
create mode 100644 include/hw/pci-bridge/simba.h
rename include/hw/pci-host/{apb.h => sabre.h} (69%)
--
2.11.0
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 01/11] apb: split simba PCI bridge into hw/pci-bridge/simba.c
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:05 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 02/11] simba: rename PBMPCIBridge and QOM types to reflect simba naming Mark Cave-Ayland
` (10 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu
Cc: Mark Cave-Ayland, Michael S . Tsirkin, Marcel Apfelbaum
Move the QOM type and macros into a new include/hw/pci-bridge/simba.h
file, and add a new CONFIG_SIMBA Makefile.objs variable which is enabled
for sparc64-softmmu builds only.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Michael S. Tsirkin <mst@redhat.com>
CC: Marcel Apfelbaum <marcel@redhat.com>
---
default-configs/sparc64-softmmu.mak | 1 +
hw/pci-bridge/Makefile.objs | 2 +
hw/pci-bridge/simba.c | 101 ++++++++++++++++++++++++++++++++++++
hw/pci-host/apb.c | 62 +---------------------
include/hw/pci-bridge/simba.h | 38 ++++++++++++++
include/hw/pci-host/apb.h | 9 ----
6 files changed, 143 insertions(+), 70 deletions(-)
create mode 100644 hw/pci-bridge/simba.c
create mode 100644 include/hw/pci-bridge/simba.h
diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-softmmu.mak
index 3e177bbd7b..9b742a7b41 100644
--- a/default-configs/sparc64-softmmu.mak
+++ b/default-configs/sparc64-softmmu.mak
@@ -12,6 +12,7 @@ CONFIG_FDC=y
CONFIG_IDE_ISA=y
CONFIG_IDE_CMD646=y
CONFIG_PCI_APB=y
+CONFIG_SIMBA=y
CONFIG_SUNHME=y
CONFIG_MC146818RTC=y
CONFIG_ISA_TESTDEV=y
diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs
index 1b05023662..47065f87d9 100644
--- a/hw/pci-bridge/Makefile.objs
+++ b/hw/pci-bridge/Makefile.objs
@@ -6,3 +6,5 @@ common-obj-$(CONFIG_IOH3420) += ioh3420.o
common-obj-$(CONFIG_I82801B11) += i82801b11.o
# NewWorld PowerMac
common-obj-$(CONFIG_DEC_PCI) += dec.o
+# Sun4u
+common-obj-$(CONFIG_SIMBA) += simba.o
diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c
new file mode 100644
index 0000000000..05ba6f0f34
--- /dev/null
+++ b/hw/pci-bridge/simba.c
@@ -0,0 +1,101 @@
+/*
+ * QEMU Simba PCI bridge
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2012,2013 Artyom Tarasenko
+ * Copyright (c) 2018 Mark Cave-Ayland
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci-bridge/simba.h"
+
+/*
+ * Chipset docs:
+ * APB: "Advanced PCI Bridge (APB) User's Manual",
+ * http://www.sun.com/processors/manuals/805-1251.pdf
+ */
+
+static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
+{
+ /*
+ * command register:
+ * According to PCI bridge spec, after reset
+ * bus master bit is off
+ * memory space enable bit is off
+ * According to manual (805-1251.pdf).
+ * the reset value should be zero unless the boot pin is tied high
+ * (which is true) and thus it should be PCI_COMMAND_MEMORY.
+ */
+ PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);
+
+ pci_bridge_initfn(dev, TYPE_PCI_BUS);
+
+ pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);
+ pci_set_word(dev->config + PCI_STATUS,
+ PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
+ PCI_STATUS_DEVSEL_MEDIUM);
+
+ /* Allow 32-bit IO addresses */
+ pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);
+ pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);
+ pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);
+ pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);
+
+ pci_bridge_update_mappings(PCI_BRIDGE(br));
+}
+
+static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->realize = apb_pci_bridge_realize;
+ k->exit = pci_bridge_exitfn;
+ k->vendor_id = PCI_VENDOR_ID_SUN;
+ k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
+ k->revision = 0x11;
+ k->config_write = pci_bridge_write_config;
+ k->is_bridge = 1;
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->reset = pci_bridge_reset;
+ dc->vmsd = &vmstate_pci_device;
+}
+
+static const TypeInfo pbm_pci_bridge_info = {
+ .name = TYPE_PBM_PCI_BRIDGE,
+ .parent = TYPE_PCI_BRIDGE,
+ .class_init = pbm_pci_bridge_class_init,
+ .instance_size = sizeof(PBMPCIBridge),
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
+static void pbm_register_types(void)
+{
+ type_register_static(&pbm_pci_bridge_info);
+}
+
+type_init(pbm_register_types)
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index ec676f94b6..3a5c046794 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -33,6 +33,7 @@
#include "hw/pci/pci_host.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
+#include "hw/pci-bridge/simba.h"
#include "hw/pci-host/apb.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
@@ -53,9 +54,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
* Chipset docs:
* PBM: "UltraSPARC IIi User's Manual",
* http://www.sun.com/processors/manuals/805-0087.pdf
- *
- * APB: "Advanced PCI Bridge (APB) User's Manual",
- * http://www.sun.com/processors/manuals/805-1251.pdf
*/
#define PBM_PCI_IMR_MASK 0x7fffffff
@@ -348,35 +346,6 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
}
}
-static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
-{
- /*
- * command register:
- * According to PCI bridge spec, after reset
- * bus master bit is off
- * memory space enable bit is off
- * According to manual (805-1251.pdf).
- * the reset value should be zero unless the boot pin is tied high
- * (which is true) and thus it should be PCI_COMMAND_MEMORY.
- */
- PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);
-
- pci_bridge_initfn(dev, TYPE_PCI_BUS);
-
- pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);
- pci_set_word(dev->config + PCI_STATUS,
- PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
- PCI_STATUS_DEVSEL_MEDIUM);
-
- /* Allow 32-bit IO addresses */
- pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);
- pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);
- pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);
- pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);
-
- pci_bridge_update_mappings(PCI_BRIDGE(br));
-}
-
static void pci_pbm_reset(DeviceState *d)
{
APBState *s = APB_DEVICE(d);
@@ -564,39 +533,10 @@ static const TypeInfo pbm_host_info = {
.class_init = pbm_host_class_init,
};
-static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->realize = apb_pci_bridge_realize;
- k->exit = pci_bridge_exitfn;
- k->vendor_id = PCI_VENDOR_ID_SUN;
- k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
- k->revision = 0x11;
- k->config_write = pci_bridge_write_config;
- k->is_bridge = 1;
- set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
- dc->reset = pci_bridge_reset;
- dc->vmsd = &vmstate_pci_device;
-}
-
-static const TypeInfo pbm_pci_bridge_info = {
- .name = TYPE_PBM_PCI_BRIDGE,
- .parent = TYPE_PCI_BRIDGE,
- .class_init = pbm_pci_bridge_class_init,
- .instance_size = sizeof(PBMPCIBridge),
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
-};
-
static void pbm_register_types(void)
{
type_register_static(&pbm_host_info);
type_register_static(&pbm_pci_host_info);
- type_register_static(&pbm_pci_bridge_info);
}
type_init(pbm_register_types)
diff --git a/include/hw/pci-bridge/simba.h b/include/hw/pci-bridge/simba.h
new file mode 100644
index 0000000000..5ab1330236
--- /dev/null
+++ b/include/hw/pci-bridge/simba.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU Simba PCI bridge
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2012,2013 Artyom Tarasenko
+ * Copyright (c) 2017 Mark Cave-Ayland
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci/pci_bridge.h"
+
+
+typedef struct PBMPCIBridge {
+ /*< private >*/
+ PCIBridge parent_obj;
+} PBMPCIBridge;
+
+#define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
+#define PBM_PCI_BRIDGE(obj) \
+ OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h
index 604d899b1e..5e28f3e1f3 100644
--- a/include/hw/pci-host/apb.h
+++ b/include/hw/pci-host/apb.h
@@ -42,13 +42,4 @@ typedef struct APBState {
unsigned int nr_resets;
} APBState;
-typedef struct PBMPCIBridge {
- /*< private >*/
- PCIBridge parent_obj;
-} PBMPCIBridge;
-
-#define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
-#define PBM_PCI_BRIDGE(obj) \
- OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
-
#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 02/11] simba: rename PBMPCIBridge and QOM types to reflect simba naming
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
2018-01-14 10:47 ` [Qemu-devel] [PATCH 01/11] apb: split simba PCI bridge into hw/pci-bridge/simba.c Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:05 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 03/11] apb: rename APB functions to use sabre prefix Mark Cave-Ayland
` (9 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
Here we rename PBMPCIBridge to SimbaPCIBridge and the QOM type from
TYPE_PBM_PCI_BRIDGE to TYPE_SIMBA_PCI_BRIDGE in improve the clarity
of the device name.
Also touch up the relevant spots in apb.c and various other function
names as appropriate.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/pci-bridge/simba.c | 22 +++++++++++-----------
hw/pci-host/apb.c | 12 ++++++------
include/hw/pci-bridge/simba.h | 10 +++++-----
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c
index 05ba6f0f34..dea4c8c5e7 100644
--- a/hw/pci-bridge/simba.c
+++ b/hw/pci-bridge/simba.c
@@ -36,7 +36,7 @@
* http://www.sun.com/processors/manuals/805-1251.pdf
*/
-static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
+static void simba_pci_bridge_realize(PCIDevice *dev, Error **errp)
{
/*
* command register:
@@ -47,7 +47,7 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
* the reset value should be zero unless the boot pin is tied high
* (which is true) and thus it should be PCI_COMMAND_MEMORY.
*/
- PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);
+ SimbaPCIBridge *br = SIMBA_PCI_BRIDGE(dev);
pci_bridge_initfn(dev, TYPE_PCI_BUS);
@@ -65,12 +65,12 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
pci_bridge_update_mappings(PCI_BRIDGE(br));
}
-static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
+static void simba_pci_bridge_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->realize = apb_pci_bridge_realize;
+ k->realize = simba_pci_bridge_realize;
k->exit = pci_bridge_exitfn;
k->vendor_id = PCI_VENDOR_ID_SUN;
k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
@@ -82,20 +82,20 @@ static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_pci_device;
}
-static const TypeInfo pbm_pci_bridge_info = {
- .name = TYPE_PBM_PCI_BRIDGE,
+static const TypeInfo simba_pci_bridge_info = {
+ .name = TYPE_SIMBA_PCI_BRIDGE,
.parent = TYPE_PCI_BRIDGE,
- .class_init = pbm_pci_bridge_class_init,
- .instance_size = sizeof(PBMPCIBridge),
+ .class_init = simba_pci_bridge_class_init,
+ .instance_size = sizeof(SimbaPCIBridge),
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
};
-static void pbm_register_types(void)
+static void simba_register_types(void)
{
- type_register_static(&pbm_pci_bridge_info);
+ type_register_static(&simba_pci_bridge_info);
}
-type_init(pbm_register_types)
+type_init(simba_register_types)
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 3a5c046794..43ee42d170 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -293,7 +293,7 @@ static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
return irq_num;
}
-static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num)
{
/* The on-board devices have fixed (legacy) OBIO intnos */
switch (PCI_SLOT(pci_dev->devfn)) {
@@ -311,7 +311,7 @@ static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num)
return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
}
-static int pci_pbmB_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
{
return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
}
@@ -417,15 +417,15 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
/* APB secondary busses */
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
- TYPE_PBM_PCI_BRIDGE);
+ TYPE_SIMBA_PCI_BRIDGE);
s->bridgeB = PCI_BRIDGE(pci_dev);
- pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbmB_map_irq);
+ pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq);
qdev_init_nofail(&pci_dev->qdev);
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
- TYPE_PBM_PCI_BRIDGE);
+ TYPE_SIMBA_PCI_BRIDGE);
s->bridgeA = PCI_BRIDGE(pci_dev);
- pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbmA_map_irq);
+ pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq);
qdev_init_nofail(&pci_dev->qdev);
}
diff --git a/include/hw/pci-bridge/simba.h b/include/hw/pci-bridge/simba.h
index 5ab1330236..fac56ab1cf 100644
--- a/include/hw/pci-bridge/simba.h
+++ b/include/hw/pci-bridge/simba.h
@@ -28,11 +28,11 @@
#include "hw/pci/pci_bridge.h"
-typedef struct PBMPCIBridge {
+typedef struct SimbaPCIBridge {
/*< private >*/
PCIBridge parent_obj;
-} PBMPCIBridge;
+} SimbaPCIBridge;
-#define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
-#define PBM_PCI_BRIDGE(obj) \
- OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
+#define TYPE_SIMBA_PCI_BRIDGE "pbm-bridge"
+#define SIMBA_PCI_BRIDGE(obj) \
+ OBJECT_CHECK(SimbaPCIBridge, (obj), TYPE_SIMBA_PCI_BRIDGE)
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 03/11] apb: rename APB functions to use sabre prefix
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
2018-01-14 10:47 ` [Qemu-devel] [PATCH 01/11] apb: split simba PCI bridge into hw/pci-bridge/simba.c Mark Cave-Ayland
2018-01-14 10:47 ` [Qemu-devel] [PATCH 02/11] simba: rename PBMPCIBridge and QOM types to reflect simba naming Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:08 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 04/11] apb: change pbm_pci_host prefix functions to use sabre_pci prefix Mark Cave-Ayland
` (8 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
As hinted in the comment at the top of the file, the naming convention for the
APB types/QOM functions isn't correct. As a starting point we can at least
rename the APB type and related functions to improve the readability of apb.c.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/pci-host/apb.c | 109 +++++++++++++++++++++++-----------------------
include/hw/pci-host/apb.h | 1 -
2 files changed, 54 insertions(+), 56 deletions(-)
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 43ee42d170..d5c459a2df 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#define NO_IRQ_REQUEST (MAX_IVEC + 1)
-static inline void pbm_set_request(APBState *s, unsigned int irq_num)
+static inline void sabre_set_request(APBState *s, unsigned int irq_num)
{
APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
@@ -78,14 +78,13 @@ static inline void pbm_set_request(APBState *s, unsigned int irq_num)
qemu_set_irq(s->ivec_irqs[irq_num], 1);
}
-static inline void pbm_check_irqs(APBState *s)
+static inline void sabre_check_irqs(APBState *s)
{
-
unsigned int i;
/* Previous request is not acknowledged, resubmit */
if (s->irq_request != NO_IRQ_REQUEST) {
- pbm_set_request(s, s->irq_request);
+ sabre_set_request(s, s->irq_request);
return;
}
/* no request pending */
@@ -95,7 +94,7 @@ static inline void pbm_check_irqs(APBState *s)
for (i = 0; i < 32; i++) {
if (s->pci_irq_in & (1ULL << i)) {
if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
- pbm_set_request(s, i);
+ sabre_set_request(s, i);
return;
}
}
@@ -103,28 +102,28 @@ static inline void pbm_check_irqs(APBState *s)
for (i = 32; i < 64; i++) {
if (s->pci_irq_in & (1ULL << i)) {
if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
- pbm_set_request(s, i);
+ sabre_set_request(s, i);
break;
}
}
}
}
-static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
+static inline void sabre_clear_request(APBState *s, unsigned int irq_num)
{
APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
qemu_set_irq(s->ivec_irqs[irq_num], 0);
s->irq_request = NO_IRQ_REQUEST;
}
-static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
+static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
{
IOMMUState *is = opaque;
return &is->iommu_as;
}
-static void apb_config_writel (void *opaque, hwaddr addr,
+static void sabre_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@@ -141,9 +140,9 @@ static void apb_config_writel (void *opaque, hwaddr addr,
s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
- pbm_clear_request(s, ino);
+ sabre_clear_request(s, ino);
}
- pbm_check_irqs(s);
+ sabre_check_irqs(s);
}
break;
case 0x1000 ... 0x107f: /* OBIO interrupt control */
@@ -153,17 +152,17 @@ static void apb_config_writel (void *opaque, hwaddr addr,
s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
if ((s->irq_request == (ino | 0x20))
&& !(val & ~PBM_PCI_IMR_MASK)) {
- pbm_clear_request(s, ino | 0x20);
+ sabre_clear_request(s, ino | 0x20);
}
- pbm_check_irqs(s);
+ sabre_check_irqs(s);
}
break;
case 0x1400 ... 0x14ff: /* PCI interrupt clear */
if (addr & 4) {
unsigned int ino = (addr & 0xff) >> 5;
if ((s->irq_request / 4) == ino) {
- pbm_clear_request(s, s->irq_request);
- pbm_check_irqs(s);
+ sabre_clear_request(s, s->irq_request);
+ sabre_check_irqs(s);
}
}
break;
@@ -171,8 +170,8 @@ static void apb_config_writel (void *opaque, hwaddr addr,
if (addr & 4) {
unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
if (s->irq_request == ino) {
- pbm_clear_request(s, ino);
- pbm_check_irqs(s);
+ sabre_clear_request(s, ino);
+ sabre_check_irqs(s);
}
}
break;
@@ -202,7 +201,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
}
}
-static uint64_t apb_config_readl (void *opaque,
+static uint64_t sabre_config_read(void *opaque,
hwaddr addr, unsigned size)
{
APBState *s = opaque;
@@ -258,14 +257,14 @@ static uint64_t apb_config_readl (void *opaque,
return val;
}
-static const MemoryRegionOps apb_config_ops = {
- .read = apb_config_readl,
- .write = apb_config_writel,
+static const MemoryRegionOps sabre_config_ops = {
+ .read = sabre_config_read,
+ .write = sabre_config_write,
.endianness = DEVICE_BIG_ENDIAN,
};
-static void apb_pci_config_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned size)
+static void sabre_pci_config_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
{
APBState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
@@ -274,8 +273,8 @@ static void apb_pci_config_write(void *opaque, hwaddr addr,
pci_data_write(phb->bus, addr, val, size);
}
-static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
- unsigned size)
+static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
+ unsigned size)
{
uint32_t ret;
APBState *s = opaque;
@@ -286,8 +285,8 @@ static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
return ret;
}
-/* The APB host has an IRQ line for each IRQ line of each slot. */
-static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
+/* The sabre host has an IRQ line for each IRQ line of each slot. */
+static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num)
{
/* Return the irq as swizzled by the PBM */
return irq_num;
@@ -316,7 +315,7 @@ static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
}
-static void pci_apb_set_irq(void *opaque, int irq_num, int level)
+static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
{
APBState *s = opaque;
@@ -326,7 +325,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
if (level) {
s->pci_irq_in |= 1ULL << irq_num;
if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
- pbm_set_request(s, irq_num);
+ sabre_set_request(s, irq_num);
}
} else {
s->pci_irq_in &= ~(1ULL << irq_num);
@@ -338,7 +337,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
s->pci_irq_in |= 1ULL << irq_num;
if ((s->irq_request == NO_IRQ_REQUEST)
&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
- pbm_set_request(s, irq_num);
+ sabre_set_request(s, irq_num);
}
} else {
s->pci_irq_in &= ~(1ULL << irq_num);
@@ -346,7 +345,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
}
}
-static void pci_pbm_reset(DeviceState *d)
+static void sabre_reset(DeviceState *d)
{
APBState *s = APB_DEVICE(d);
PCIDevice *pci_dev;
@@ -379,12 +378,12 @@ static void pci_pbm_reset(DeviceState *d)
}
static const MemoryRegionOps pci_config_ops = {
- .read = apb_pci_config_read,
- .write = apb_pci_config_write,
+ .read = sabre_pci_config_read,
+ .write = sabre_pci_config_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void pci_pbm_realize(DeviceState *dev, Error **errp)
+static void sabre_realize(DeviceState *dev, Error **errp)
{
APBState *s = APB_DEVICE(dev);
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
@@ -403,17 +402,17 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
&s->pci_mmio);
phb->bus = pci_register_root_bus(dev, "pci",
- pci_apb_set_irq, pci_apb_map_irq, s,
+ pci_sabre_set_irq, pci_sabre_map_irq, s,
&s->pci_mmio,
&s->pci_ioport,
0, 32, TYPE_PCI_BUS);
pci_create_simple(phb->bus, 0, "pbm-pci");
- /* APB IOMMU */
+ /* IOMMU */
memory_region_add_subregion_overlap(&s->apb_config, 0x200,
sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
- pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, s->iommu);
+ pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
/* APB secondary busses */
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
@@ -429,7 +428,7 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
qdev_init_nofail(&pci_dev->qdev);
}
-static void pci_pbm_init(Object *obj)
+static void sabre_init(Object *obj)
{
APBState *s = APB_DEVICE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
@@ -444,7 +443,7 @@ static void pci_pbm_init(Object *obj)
for (i = 0; i < 32; i++) {
s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
}
- qdev_init_gpio_in_named(DEVICE(s), pci_apb_set_irq, "pbm-irq", MAX_IVEC);
+ qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC);
qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC);
s->irq_request = NO_IRQ_REQUEST;
s->pci_irq_in = 0ULL;
@@ -456,7 +455,7 @@ static void pci_pbm_init(Object *obj)
0, NULL);
/* apb_config */
- memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
+ memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s,
"apb-config", 0x10000);
/* at region 0 */
sysbus_init_mmio(sbd, &s->apb_config);
@@ -473,7 +472,7 @@ static void pci_pbm_init(Object *obj)
sysbus_init_mmio(sbd, &s->pci_ioport);
}
-static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
+static void sabre_pci_host_realize(PCIDevice *d, Error **errp)
{
pci_set_word(d->config + PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
@@ -482,12 +481,12 @@ static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
PCI_STATUS_DEVSEL_MEDIUM);
}
-static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
+static void sabre_pci_host_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- k->realize = pbm_pci_host_realize;
+ k->realize = sabre_pci_host_realize;
k->vendor_id = PCI_VENDOR_ID_SUN;
k->device_id = PCI_DEVICE_ID_SUN_SABRE;
k->class_id = PCI_CLASS_BRIDGE_HOST;
@@ -502,41 +501,41 @@ static const TypeInfo pbm_pci_host_info = {
.name = "pbm-pci",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
- .class_init = pbm_pci_host_class_init,
+ .class_init = sabre_pci_host_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
};
-static Property pbm_pci_host_properties[] = {
+static Property sabre_properties[] = {
DEFINE_PROP_UINT64("special-base", APBState, special_base, 0),
DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0),
DEFINE_PROP_END_OF_LIST(),
};
-static void pbm_host_class_init(ObjectClass *klass, void *data)
+static void sabre_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->realize = pci_pbm_realize;
- dc->reset = pci_pbm_reset;
- dc->props = pbm_pci_host_properties;
+ dc->realize = sabre_realize;
+ dc->reset = sabre_reset;
+ dc->props = sabre_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
-static const TypeInfo pbm_host_info = {
+static const TypeInfo sabre_info = {
.name = TYPE_APB,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(APBState),
- .instance_init = pci_pbm_init,
- .class_init = pbm_host_class_init,
+ .instance_init = sabre_init,
+ .class_init = sabre_class_init,
};
-static void pbm_register_types(void)
+static void sabre_register_types(void)
{
- type_register_static(&pbm_host_info);
+ type_register_static(&sabre_info);
type_register_static(&pbm_pci_host_info);
}
-type_init(pbm_register_types)
+type_init(sabre_register_types)
diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h
index 5e28f3e1f3..41de012396 100644
--- a/include/hw/pci-host/apb.h
+++ b/include/hw/pci-host/apb.h
@@ -15,7 +15,6 @@
#define OBIO_SER_IRQ 0x2b
#define TYPE_APB "pbm"
-
#define APB_DEVICE(obj) \
OBJECT_CHECK(APBState, (obj), TYPE_APB)
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 04/11] apb: change pbm_pci_host prefix functions to use sabre_pci prefix
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (2 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 03/11] apb: rename APB functions to use sabre prefix Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:09 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 05/11] apb: QOMify sabre PCI host bridge Mark Cave-Ayland
` (7 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
This is the proper name for the PBM host bridge as referenced in the Sun
documentation.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/pci-host/apb.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index d5c459a2df..98c5f344f7 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -472,7 +472,7 @@ static void sabre_init(Object *obj)
sysbus_init_mmio(sbd, &s->pci_ioport);
}
-static void sabre_pci_host_realize(PCIDevice *d, Error **errp)
+static void sabre_pci_realize(PCIDevice *d, Error **errp)
{
pci_set_word(d->config + PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
@@ -481,12 +481,12 @@ static void sabre_pci_host_realize(PCIDevice *d, Error **errp)
PCI_STATUS_DEVSEL_MEDIUM);
}
-static void sabre_pci_host_class_init(ObjectClass *klass, void *data)
+static void sabre_pci_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- k->realize = sabre_pci_host_realize;
+ k->realize = sabre_pci_realize;
k->vendor_id = PCI_VENDOR_ID_SUN;
k->device_id = PCI_DEVICE_ID_SUN_SABRE;
k->class_id = PCI_CLASS_BRIDGE_HOST;
@@ -497,11 +497,11 @@ static void sabre_pci_host_class_init(ObjectClass *klass, void *data)
dc->user_creatable = false;
}
-static const TypeInfo pbm_pci_host_info = {
+static const TypeInfo sabre_pci_info = {
.name = "pbm-pci",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
- .class_init = sabre_pci_host_class_init,
+ .class_init = sabre_pci_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
@@ -535,7 +535,7 @@ static const TypeInfo sabre_info = {
static void sabre_register_types(void)
{
type_register_static(&sabre_info);
- type_register_static(&pbm_pci_host_info);
+ type_register_static(&sabre_pci_info);
}
type_init(sabre_register_types)
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 05/11] apb: QOMify sabre PCI host bridge
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (3 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 04/11] apb: change pbm_pci_host prefix functions to use sabre_pci prefix Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:13 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 06/11] apb: rename QOM type from TYPE_APB to TYPE_SABRE Mark Cave-Ayland
` (6 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/pci-host/apb.c | 6 +++---
include/hw/pci-host/apb.h | 14 +++++++++++---
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 98c5f344f7..36c6251816 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -407,7 +407,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
&s->pci_ioport,
0, 32, TYPE_PCI_BUS);
- pci_create_simple(phb->bus, 0, "pbm-pci");
+ pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
/* IOMMU */
memory_region_add_subregion_overlap(&s->apb_config, 0x200,
@@ -498,9 +498,9 @@ static void sabre_pci_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo sabre_pci_info = {
- .name = "pbm-pci",
+ .name = TYPE_SABRE_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PCIDevice),
+ .instance_size = sizeof(SabrePCIState),
.class_init = sabre_pci_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h
index 41de012396..470863639a 100644
--- a/include/hw/pci-host/apb.h
+++ b/include/hw/pci-host/apb.h
@@ -14,9 +14,13 @@
#define OBIO_MSE_IRQ 0x2a
#define OBIO_SER_IRQ 0x2b
-#define TYPE_APB "pbm"
-#define APB_DEVICE(obj) \
- OBJECT_CHECK(APBState, (obj), TYPE_APB)
+typedef struct SabrePCIState {
+ PCIDevice parent_obj;
+} SabrePCIState;
+
+#define TYPE_SABRE_PCI_DEVICE "sabre-pci"
+#define SABRE_PCI_DEVICE(obj) \
+ OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
typedef struct APBState {
PCIHostState parent_obj;
@@ -41,4 +45,8 @@ typedef struct APBState {
unsigned int nr_resets;
} APBState;
+#define TYPE_APB "apb"
+#define APB_DEVICE(obj) \
+ OBJECT_CHECK(APBState, (obj), TYPE_APB)
+
#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 06/11] apb: rename QOM type from TYPE_APB to TYPE_SABRE
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (4 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 05/11] apb: QOMify sabre PCI host bridge Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:15 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 07/11] sun4u: rename apb variables and constants Mark Cave-Ayland
` (5 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
Similarly rename the corresponding APBState typedef to SabreState.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/pci-host/apb.c | 30 +++++++++++++++---------------
hw/sparc64/sun4u.c | 6 +++---
include/hw/pci-host/apb.h | 10 +++++-----
3 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 36c6251816..f6c5dbd469 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#define NO_IRQ_REQUEST (MAX_IVEC + 1)
-static inline void sabre_set_request(APBState *s, unsigned int irq_num)
+static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
{
APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
@@ -78,7 +78,7 @@ static inline void sabre_set_request(APBState *s, unsigned int irq_num)
qemu_set_irq(s->ivec_irqs[irq_num], 1);
}
-static inline void sabre_check_irqs(APBState *s)
+static inline void sabre_check_irqs(SabreState *s)
{
unsigned int i;
@@ -109,7 +109,7 @@ static inline void sabre_check_irqs(APBState *s)
}
}
-static inline void sabre_clear_request(APBState *s, unsigned int irq_num)
+static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
{
APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
qemu_set_irq(s->ivec_irqs[irq_num], 0);
@@ -126,7 +126,7 @@ static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
static void sabre_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
- APBState *s = opaque;
+ SabreState *s = opaque;
APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
@@ -204,7 +204,7 @@ static void sabre_config_write(void *opaque, hwaddr addr,
static uint64_t sabre_config_read(void *opaque,
hwaddr addr, unsigned size)
{
- APBState *s = opaque;
+ SabreState *s = opaque;
uint32_t val;
switch (addr & 0xffff) {
@@ -266,7 +266,7 @@ static const MemoryRegionOps sabre_config_ops = {
static void sabre_pci_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
- APBState *s = opaque;
+ SabreState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
@@ -277,7 +277,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t ret;
- APBState *s = opaque;
+ SabreState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
ret = pci_data_read(phb->bus, addr, size);
@@ -317,7 +317,7 @@ static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
{
- APBState *s = opaque;
+ SabreState *s = opaque;
APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
/* PCI IRQ map onto the first 32 INO. */
@@ -347,7 +347,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
static void sabre_reset(DeviceState *d)
{
- APBState *s = APB_DEVICE(d);
+ SabreState *s = SABRE_DEVICE(d);
PCIDevice *pci_dev;
unsigned int i;
uint16_t cmd;
@@ -385,7 +385,7 @@ static const MemoryRegionOps pci_config_ops = {
static void sabre_realize(DeviceState *dev, Error **errp)
{
- APBState *s = APB_DEVICE(dev);
+ SabreState *s = SABRE_DEVICE(dev);
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
PCIDevice *pci_dev;
@@ -430,7 +430,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
static void sabre_init(Object *obj)
{
- APBState *s = APB_DEVICE(obj);
+ SabreState *s = SABRE_DEVICE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
unsigned int i;
@@ -509,8 +509,8 @@ static const TypeInfo sabre_pci_info = {
};
static Property sabre_properties[] = {
- DEFINE_PROP_UINT64("special-base", APBState, special_base, 0),
- DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0),
+ DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0),
+ DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
DEFINE_PROP_END_OF_LIST(),
};
@@ -525,9 +525,9 @@ static void sabre_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo sabre_info = {
- .name = TYPE_APB,
+ .name = TYPE_SABRE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(APBState),
+ .instance_size = sizeof(SabreState),
.instance_init = sabre_init,
.class_init = sabre_class_init,
};
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index ec45ec2801..b8f685847a 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -465,7 +465,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
Nvram *nvram;
unsigned int i;
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
- APBState *apb;
+ SabreState *apb;
PCIBus *pci_bus, *pci_busA, *pci_busB;
PCIDevice *ebus, *pci_dev;
SysBusDevice *s;
@@ -488,8 +488,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
prom_init(hwdef->prom_addr, bios_name);
- /* Init APB (PCI host bridge) */
- apb = APB_DEVICE(qdev_create(NULL, TYPE_APB));
+ /* Init sabre (PCI host bridge) */
+ apb = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort);
diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h
index 470863639a..2552f3c984 100644
--- a/include/hw/pci-host/apb.h
+++ b/include/hw/pci-host/apb.h
@@ -22,7 +22,7 @@ typedef struct SabrePCIState {
#define SABRE_PCI_DEVICE(obj) \
OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
-typedef struct APBState {
+typedef struct SabreState {
PCIHostState parent_obj;
hwaddr special_base;
@@ -43,10 +43,10 @@ typedef struct APBState {
unsigned int irq_request;
uint32_t reset_control;
unsigned int nr_resets;
-} APBState;
+} SabreState;
-#define TYPE_APB "apb"
-#define APB_DEVICE(obj) \
- OBJECT_CHECK(APBState, (obj), TYPE_APB)
+#define TYPE_SABRE "sabre"
+#define SABRE_DEVICE(obj) \
+ OBJECT_CHECK(SabreState, (obj), TYPE_SABRE)
#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 07/11] sun4u: rename apb variables and constants
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (5 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 06/11] apb: rename QOM type from TYPE_APB to TYPE_SABRE Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:20 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 08/11] apb: rename apb.c to sabre.c Mark Cave-Ayland
` (4 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
In order to reflect the previous change of TYPE_APB to TYPE_SABRE, update
the corresponding variable names to keep the terminology consistent.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc64/sun4u.c | 41 +++++++++++++++++++++--------------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index b8f685847a..fb18afaaa6 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -55,9 +55,9 @@
#define CMDLINE_ADDR 0x003ff000
#define PROM_SIZE_MAX (4 * 1024 * 1024)
#define PROM_VADDR 0x000ffd00000ULL
-#define APB_SPECIAL_BASE 0x1fe00000000ULL
-#define APB_MEM_BASE 0x1ff00000000ULL
-#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
+#define PBM_SPECIAL_BASE 0x1fe00000000ULL
+#define PBM_MEM_BASE 0x1ff00000000ULL
+#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
#define PROM_FILENAME "openbios-sparc64"
#define NVRAM_SIZE 0x2000
#define MAX_IDE_BUS 2
@@ -465,7 +465,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
Nvram *nvram;
unsigned int i;
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
- SabreState *apb;
+ SabreState *sabre;
PCIBus *pci_bus, *pci_busA, *pci_busB;
PCIDevice *ebus, *pci_dev;
SysBusDevice *s;
@@ -489,23 +489,24 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
prom_init(hwdef->prom_addr, bios_name);
/* Init sabre (PCI host bridge) */
- apb = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
- qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
- qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
- object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort);
- qdev_init_nofail(DEVICE(apb));
+ sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
+ qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
+ qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
+ object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
+ &error_abort);
+ qdev_init_nofail(DEVICE(sabre));
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
- qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i,
+ qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
}
- pci_bus = PCI_HOST_BRIDGE(apb)->bus;
- pci_busA = pci_bridge_get_sec_bus(apb->bridgeA);
- pci_busB = pci_bridge_get_sec_bus(apb->bridgeB);
+ pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
+ pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
+ pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
- /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
+ /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
reserved (leaving no slots free after on-board devices) however slots
0-3 are free on busB */
pci_bus->slot_reserved_mask = 0xfffffffc;
@@ -517,17 +518,17 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
hwdef->console_serial_base);
qdev_init_nofail(DEVICE(ebus));
- /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */
+ /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
- qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ));
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
- qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ));
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
- qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ));
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
- qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ));
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
- qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ));
+ qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 08/11] apb: rename apb.c to sabre.c
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (6 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 07/11] sun4u: rename apb variables and constants Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:30 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host Mark Cave-Ayland
` (3 subsequent siblings)
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
This is the final stage in correcting the naming convention with respect to
sabre, APB and PBM. It is effectively a file rename from apb.c to sabre.c
along with touching up a few constants to remove the remaining references
to APB.
Note that as part of the rename process the configuration variable
CONFIG_PCI_APB is changed to CONFIG_PCI_SABRE.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
default-configs/sparc64-softmmu.mak | 2 +-
hw/pci-host/Makefile.objs | 2 +-
hw/pci-host/{apb.c => sabre.c} | 57 +++++++++++++++++-----------------
hw/sparc64/sun4u.c | 2 +-
include/hw/pci-host/{apb.h => sabre.h} | 2 +-
5 files changed, 33 insertions(+), 32 deletions(-)
rename hw/pci-host/{apb.c => sabre.c} (91%)
rename include/hw/pci-host/{apb.h => sabre.h} (97%)
diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-softmmu.mak
index 9b742a7b41..52edafe547 100644
--- a/default-configs/sparc64-softmmu.mak
+++ b/default-configs/sparc64-softmmu.mak
@@ -11,7 +11,7 @@ CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_IDE_ISA=y
CONFIG_IDE_CMD646=y
-CONFIG_PCI_APB=y
+CONFIG_PCI_SABRE=y
CONFIG_SIMBA=y
CONFIG_SUNHME=y
CONFIG_MC146818RTC=y
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index 9c7909cf44..4b69f737b5 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -11,7 +11,7 @@ common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o
# ARM devices
common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
-common-obj-$(CONFIG_PCI_APB) += apb.o
+common-obj-$(CONFIG_PCI_SABRE) += sabre.o
common-obj-$(CONFIG_FULONG) += bonito.o
common-obj-$(CONFIG_PCI_PIIX) += piix.o
common-obj-$(CONFIG_PCI_Q35) += q35.o
diff --git a/hw/pci-host/apb.c b/hw/pci-host/sabre.c
similarity index 91%
rename from hw/pci-host/apb.c
rename to hw/pci-host/sabre.c
index f6c5dbd469..4054c17598 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/sabre.c
@@ -1,8 +1,9 @@
/*
- * QEMU Ultrasparc APB PCI host
+ * QEMU Ultrasparc Sabre PCI host (PBM)
*
* Copyright (c) 2006 Fabrice Bellard
* Copyright (c) 2012,2013 Artyom Tarasenko
+ * Copyright (c) 2018 Mark Cave-Ayland
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -23,10 +24,6 @@
* THE SOFTWARE.
*/
-/* XXX This file and most of its contents are somewhat misnamed. The
- Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
- the secondary PCI bridge. */
-
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
@@ -34,20 +31,20 @@
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-bridge/simba.h"
-#include "hw/pci-host/apb.h"
+#include "hw/pci-host/sabre.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "qapi/error.h"
#include "qemu/log.h"
-/* debug APB */
-//#define DEBUG_APB
+/* debug sabre */
+//#define DEBUG_SABRE
-#ifdef DEBUG_APB
-#define APB_DPRINTF(fmt, ...) \
-do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
+#ifdef DEBUG_SABRE
+#define SABRE_DPRINTF(fmt, ...) \
+do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define APB_DPRINTF(fmt, ...)
+#define SABRE_DPRINTF(fmt, ...)
#endif
/*
@@ -72,7 +69,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
{
- APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
+ SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num);
s->irq_request = irq_num;
qemu_set_irq(s->ivec_irqs[irq_num], 1);
@@ -111,7 +108,7 @@ static inline void sabre_check_irqs(SabreState *s)
static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
{
- APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
+ SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
qemu_set_irq(s->ivec_irqs[irq_num], 0);
s->irq_request = NO_IRQ_REQUEST;
}
@@ -128,7 +125,8 @@ static void sabre_config_write(void *opaque, hwaddr addr,
{
SabreState *s = opaque;
- APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
+ SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
+ addr, val);
switch (addr & 0xffff) {
case 0x30 ... 0x4f: /* DMA error registers */
@@ -252,7 +250,7 @@ static uint64_t sabre_config_read(void *opaque,
val = 0;
break;
}
- APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
+ SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
return val;
}
@@ -269,7 +267,8 @@ static void sabre_pci_config_write(void *opaque, hwaddr addr,
SabreState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
- APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
+ SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
+ addr, val);
pci_data_write(phb->bus, addr, val, size);
}
@@ -281,7 +280,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
PCIHostState *phb = PCI_HOST_BRIDGE(s);
ret = pci_data_read(phb->bus, addr, size);
- APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
+ SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
return ret;
}
@@ -319,7 +318,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
{
SabreState *s = opaque;
- APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
+ SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
/* PCI IRQ map onto the first 32 INO. */
if (irq_num < 32) {
if (level) {
@@ -333,7 +332,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
} else {
/* OBIO IRQ map onto the next 32 INO. */
if (level) {
- APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
+ SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num,
+ level);
s->pci_irq_in |= 1ULL << irq_num;
if ((s->irq_request == NO_IRQ_REQUEST)
&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
@@ -390,7 +390,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
PCIDevice *pci_dev;
- /* apb_config */
+ /* sabre_config */
sysbus_mmio_map(sbd, 0, s->special_base);
/* PCI configuration space */
sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
@@ -410,7 +410,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
/* IOMMU */
- memory_region_add_subregion_overlap(&s->apb_config, 0x200,
+ memory_region_add_subregion_overlap(&s->sabre_config, 0x200,
sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
@@ -454,19 +454,20 @@ static void sabre_init(Object *obj)
qdev_prop_allow_set_link_before_realize,
0, NULL);
- /* apb_config */
- memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s,
- "apb-config", 0x10000);
+ /* sabre_config */
+ memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
+ "sabre-config", 0x10000);
/* at region 0 */
- sysbus_init_mmio(sbd, &s->apb_config);
+ sysbus_init_mmio(sbd, &s->sabre_config);
memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
- "apb-pci-config", 0x1000000);
+ "sabre-pci-config", 0x1000000);
/* at region 1 */
sysbus_init_mmio(sbd, &s->pci_config);
/* pci_ioport */
- memory_region_init(&s->pci_ioport, OBJECT(s), "apb-pci-ioport", 0x1000000);
+ memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport",
+ 0x1000000);
/* at region 2 */
sysbus_init_mmio(sbd, &s->pci_ioport);
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index fb18afaaa6..c4eff6bea2 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -30,7 +30,7 @@
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_host.h"
-#include "hw/pci-host/apb.h"
+#include "hw/pci-host/sabre.h"
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/timer/m48t59.h"
diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/sabre.h
similarity index 97%
rename from include/hw/pci-host/apb.h
rename to include/hw/pci-host/sabre.h
index 2552f3c984..0f2ccc01c6 100644
--- a/include/hw/pci-host/apb.h
+++ b/include/hw/pci-host/sabre.h
@@ -27,7 +27,7 @@ typedef struct SabreState {
hwaddr special_base;
hwaddr mem_base;
- MemoryRegion apb_config;
+ MemoryRegion sabre_config;
MemoryRegion pci_config;
MemoryRegion pci_mmio;
MemoryRegion pci_ioport;
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (7 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 08/11] apb: rename apb.c to sabre.c Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:32 ` Philippe Mathieu-Daudé
2018-01-16 4:48 ` Michael S. Tsirkin
2018-01-14 10:47 ` [Qemu-devel] [PATCH 10/11] sabre: convert from SABRE_DPRINTF macro to trace-events Mark Cave-Ayland
` (2 subsequent siblings)
11 siblings, 2 replies; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu
Cc: Mark Cave-Ayland, Michael S . Tsirkin, Marcel Apfelbaum
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Michael S. Tsirkin <mst@redhat.com>
CC: Marcel Apfelbaum <marcel@redhat.com>
---
Makefile.objs | 1 +
hw/pci-host/trace-events | 1 +
2 files changed, 2 insertions(+)
create mode 100644 hw/pci-host/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index c8b1bba593..6aa793ce4f 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -149,6 +149,7 @@ trace-events-subdirs += hw/i386/xen
trace-events-subdirs += hw/9pfs
trace-events-subdirs += hw/ppc
trace-events-subdirs += hw/pci
+trace-events-subdirs += hw/pci-host
trace-events-subdirs += hw/s390x
trace-events-subdirs += hw/vfio
trace-events-subdirs += hw/acpi
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
new file mode 100644
index 0000000000..9284b1fbad
--- /dev/null
+++ b/hw/pci-host/trace-events
@@ -0,0 +1 @@
+# See docs/devel/tracing.txt for syntax documentation.
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 10/11] sabre: convert from SABRE_DPRINTF macro to trace-events
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (8 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:36 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 11/11] sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events Mark Cave-Ayland
2018-01-14 11:15 ` [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions no-reply
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/pci-host/sabre.c | 32 ++++++++++----------------------
hw/pci-host/trace-events | 10 ++++++++++
2 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index 4054c17598..2268a41dd9 100644
--- a/hw/pci-host/sabre.c
+++ b/hw/pci-host/sabre.c
@@ -36,16 +36,7 @@
#include "exec/address-spaces.h"
#include "qapi/error.h"
#include "qemu/log.h"
-
-/* debug sabre */
-//#define DEBUG_SABRE
-
-#ifdef DEBUG_SABRE
-#define SABRE_DPRINTF(fmt, ...) \
-do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define SABRE_DPRINTF(fmt, ...)
-#endif
+#include "trace.h"
/*
* Chipset docs:
@@ -69,8 +60,7 @@ do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
{
- SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num);
-
+ trace_sabre_set_request(irq_num);
s->irq_request = irq_num;
qemu_set_irq(s->ivec_irqs[irq_num], 1);
}
@@ -108,7 +98,7 @@ static inline void sabre_check_irqs(SabreState *s)
static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
{
- SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
+ trace_sabre_clear_request(irq_num);
qemu_set_irq(s->ivec_irqs[irq_num], 0);
s->irq_request = NO_IRQ_REQUEST;
}
@@ -125,8 +115,7 @@ static void sabre_config_write(void *opaque, hwaddr addr,
{
SabreState *s = opaque;
- SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
- addr, val);
+ trace_sabre_config_write(addr, val);
switch (addr & 0xffff) {
case 0x30 ... 0x4f: /* DMA error registers */
@@ -250,7 +239,7 @@ static uint64_t sabre_config_read(void *opaque,
val = 0;
break;
}
- SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
+ trace_sabre_config_read(addr, val);
return val;
}
@@ -267,8 +256,7 @@ static void sabre_pci_config_write(void *opaque, hwaddr addr,
SabreState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
- SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
- addr, val);
+ trace_sabre_pci_config_write(addr, val);
pci_data_write(phb->bus, addr, val, size);
}
@@ -280,7 +268,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
PCIHostState *phb = PCI_HOST_BRIDGE(s);
ret = pci_data_read(phb->bus, addr, size);
- SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
+ trace_sabre_pci_config_read(addr, ret);
return ret;
}
@@ -318,7 +306,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
{
SabreState *s = opaque;
- SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
+ trace_sabre_pci_set_irq(irq_num, level);
+
/* PCI IRQ map onto the first 32 INO. */
if (irq_num < 32) {
if (level) {
@@ -332,8 +321,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
} else {
/* OBIO IRQ map onto the next 32 INO. */
if (level) {
- SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num,
- level);
+ trace_sabre_pci_set_obio_irq(irq_num, level);
s->pci_irq_in |= 1ULL << irq_num;
if ((s->irq_request == NO_IRQ_REQUEST)
&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index 9284b1fbad..32dfc84692 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -1 +1,11 @@
# See docs/devel/tracing.txt for syntax documentation.
+
+# hw/pci-host/sabre.c
+sabre_set_request(int irq_num) "request irq %d"
+sabre_clear_request(int irq_num) "clear request irq %d"
+sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
+sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
+sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
+sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
+sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d"
+sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d"
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PATCH 11/11] sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (9 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 10/11] sabre: convert from SABRE_DPRINTF macro to trace-events Mark Cave-Ayland
@ 2018-01-14 10:47 ` Mark Cave-Ayland
2018-01-14 13:41 ` Philippe Mathieu-Daudé
2018-01-14 11:15 ` [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions no-reply
11 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 10:47 UTC (permalink / raw)
To: qemu-devel, atar4qemu; +Cc: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc64/sparc64.c | 85 ++++++++++++++++++++-----------------------------
hw/sparc64/trace-events | 18 +++++++++++
2 files changed, 52 insertions(+), 51 deletions(-)
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index 95a06f00b2..408388945e 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -28,25 +28,9 @@
#include "hw/char/serial.h"
#include "hw/sparc/sparc64.h"
#include "qemu/timer.h"
+#include "trace.h"
-//#define DEBUG_IRQ
-//#define DEBUG_TIMER
-
-#ifdef DEBUG_IRQ
-#define CPUIRQ_DPRINTF(fmt, ...) \
- do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define CPUIRQ_DPRINTF(fmt, ...)
-#endif
-
-#ifdef DEBUG_TIMER
-#define TIMER_DPRINTF(fmt, ...) \
- do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define TIMER_DPRINTF(fmt, ...)
-#endif
-
#define TICK_MAX 0x7fffffffffffffffULL
void cpu_check_irqs(CPUSPARCState *env)
@@ -73,8 +57,7 @@ void cpu_check_irqs(CPUSPARCState *env)
is (2 << psrpil). */
if (pil < (2 << env->psrpil)) {
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
- CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
- env->interrupt_index);
+ trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
@@ -92,22 +75,21 @@ void cpu_check_irqs(CPUSPARCState *env)
if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
- CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
- "current %x >= pending %x\n",
- env->tl, cpu_tsptr(env)->tt, new_interrupt);
+ trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
+ cpu_tsptr(env)->tt,
+ new_interrupt);
} else if (old_interrupt != new_interrupt) {
env->interrupt_index = new_interrupt;
- CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
- old_interrupt, new_interrupt);
+ trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
+ new_interrupt);
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
}
} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
- CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
- "current interrupt %x\n",
- pil, env->pil_in, env->softint, env->interrupt_index);
+ trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
+ env->interrupt_index);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
@@ -131,7 +113,7 @@ void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level)
if (level) {
if (!(env->ivec_status & 0x20)) {
- CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
+ trace_sparc64_cpu_ivec_raise_irq(irq);
cs = CPU(cpu);
cs->halted = 0;
env->interrupt_index = TT_IVEC;
@@ -143,7 +125,7 @@ void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level)
}
} else {
if (env->ivec_status & 0x20) {
- CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
+ trace_sparc64_cpu_ivec_lower_irq(irq);
cs = CPU(cpu);
env->ivec_status &= ~0x20;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
@@ -216,10 +198,10 @@ static void tick_irq(void *opaque)
CPUTimer *timer = env->tick;
if (timer->disabled) {
- CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
+ trace_sparc64_cpu_tick_irq_disabled();
return;
} else {
- CPUIRQ_DPRINTF("tick: fire\n");
+ trace_sparc64_cpu_tick_irq_fire();
}
env->softint |= SOFTINT_TIMER;
@@ -234,10 +216,10 @@ static void stick_irq(void *opaque)
CPUTimer *timer = env->stick;
if (timer->disabled) {
- CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
+ trace_sparc64_cpu_stick_irq_disabled();
return;
} else {
- CPUIRQ_DPRINTF("stick: fire\n");
+ trace_sparc64_cpu_stick_irq_fire();
}
env->softint |= SOFTINT_STIMER;
@@ -252,10 +234,10 @@ static void hstick_irq(void *opaque)
CPUTimer *timer = env->hstick;
if (timer->disabled) {
- CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
+ trace_sparc64_cpu_hstick_irq_disabled();
return;
} else {
- CPUIRQ_DPRINTF("hstick: fire\n");
+ trace_sparc64_cpu_hstick_irq_fire();
}
env->softint |= SOFTINT_STIMER;
@@ -280,9 +262,9 @@ void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
cpu_to_timer_ticks(real_count, timer->frequency);
- TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
- timer->name, real_count,
- timer->npt ? "disabled" : "enabled", timer);
+ trace_sparc64_cpu_tick_set_count(timer->name, real_count,
+ timer->npt ? "disabled" : "enabled",
+ timer);
timer->npt = npt_bit ? 1 : 0;
timer->clock_offset = vm_clock_offset;
@@ -294,9 +276,9 @@ uint64_t cpu_tick_get_count(CPUTimer *timer)
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
timer->frequency);
- TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
- timer->name, real_count,
- timer->npt ? "disabled" : "enabled", timer);
+ trace_sparc64_cpu_tick_get_count(timer->name, real_count,
+ timer->npt ? "disabled" : "enabled",
+ timer);
if (timer->npt) {
real_count |= timer->npt_mask;
@@ -319,18 +301,19 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
expires = now + 1;
}
- TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
- "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
- timer->name, real_limit,
- timer->disabled ? "disabled" : "enabled",
- timer, limit,
- timer_to_cpu_ticks(now - timer->clock_offset,
- timer->frequency),
- timer_to_cpu_ticks(expires - now, timer->frequency));
+ trace_sparc64_cpu_tick_set_limit(timer->name, real_limit,
+ timer->disabled ? "disabled" : "enabled",
+ timer, limit,
+ timer_to_cpu_ticks(
+ now - timer->clock_offset,
+ timer->frequency
+ ),
+ timer_to_cpu_ticks(
+ expires - now, timer->frequency
+ ));
if (!real_limit) {
- TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
- timer->name);
+ trace_sparc64_cpu_tick_set_limit_zero(timer->name);
timer_del(timer->qtimer);
} else if (timer->disabled) {
timer_del(timer->qtimer);
diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events
index 2ee2d75f70..cf0888581d 100644
--- a/hw/sparc64/trace-events
+++ b/hw/sparc64/trace-events
@@ -7,3 +7,21 @@ ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d level %d"
sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d"
sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d"
sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64
+
+# hw/sparc64/sparc64.c
+sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
+sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
+sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
+sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
+sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d"
+sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d"
+sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled"
+sparc64_cpu_tick_irq_fire(void) "tick_irq: fire"
+sparc64_cpu_stick_irq_disabled(void) "stick_irq: softint disabled"
+sparc64_cpu_stick_irq_fire(void) "stick_irq: fire"
+sparc64_cpu_hstick_irq_disabled(void) "hstick_irq: softint disabled"
+sparc64_cpu_hstick_irq_fire(void) "hstick_irq: fire"
+sparc64_cpu_tick_set_count(const char *name, uint64_t real_count, const char *npt, void *p) "%s set_count count=0x%016lx (npt %s) p=%p"
+sparc64_cpu_tick_get_count(const char *name, uint64_t real_count, const char *npt, void *p) "%s get_count count=0x%016lx (npt %s) p=%p"
+sparc64_cpu_tick_set_limit(const char *name, uint64_t real_limit, const char *dis, void *p, uint64_t limit, uint64_t t, uint64_t dt) "%s set_limit limit=0x%016lx (%s) p=%p called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)"
+sparc64_cpu_tick_set_limit_zero(const char *name) "%s set_limit limit=ZERO - not starting timer"
--
2.11.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
` (10 preceding siblings ...)
2018-01-14 10:47 ` [Qemu-devel] [PATCH 11/11] sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events Mark Cave-Ayland
@ 2018-01-14 11:15 ` no-reply
2018-01-14 11:21 ` Mark Cave-Ayland
11 siblings, 1 reply; 32+ messages in thread
From: no-reply @ 2018-01-14 11:15 UTC (permalink / raw)
To: mark.cave-ayland; +Cc: famz, qemu-devel, atar4qemu
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180114104751.21965-1-mark.cave-ayland@ilande.co.uk
Subject: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
68e33f523f sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events
3ac895348d sabre: convert from SABRE_DPRINTF macro to trace-events
5b44f0019e pci: add trace-events support for hw/pci-host
a625765105 apb: rename apb.c to sabre.c
8ef3083a55 sun4u: rename apb variables and constants
349fc89fe8 apb: rename QOM type from TYPE_APB to TYPE_SABRE
74cbac48cd apb: QOMify sabre PCI host bridge
787f76fc03 apb: change pbm_pci_host prefix functions to use sabre_pci prefix
65b67f4892 apb: rename APB functions to use sabre prefix
3bdf1030e7 simba: rename PBMPCIBridge and QOM types to reflect simba naming
b645abcfb6 apb: split simba PCI bridge into hw/pci-bridge/simba.c
=== OUTPUT BEGIN ===
Checking PATCH 1/11: apb: split simba PCI bridge into hw/pci-bridge/simba.c...
Checking PATCH 2/11: simba: rename PBMPCIBridge and QOM types to reflect simba naming...
Checking PATCH 3/11: apb: rename APB functions to use sabre prefix...
Checking PATCH 4/11: apb: change pbm_pci_host prefix functions to use sabre_pci prefix...
Checking PATCH 5/11: apb: QOMify sabre PCI host bridge...
Checking PATCH 6/11: apb: rename QOM type from TYPE_APB to TYPE_SABRE...
Checking PATCH 7/11: sun4u: rename apb variables and constants...
Checking PATCH 8/11: apb: rename apb.c to sabre.c...
ERROR: do not use C99 // comments
#86: FILE: hw/pci-host/sabre.c:41:
+//#define DEBUG_SABRE
total: 1 errors, 0 warnings, 188 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 9/11: pci: add trace-events support for hw/pci-host...
Checking PATCH 10/11: sabre: convert from SABRE_DPRINTF macro to trace-events...
Checking PATCH 11/11: sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions
2018-01-14 11:15 ` [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions no-reply
@ 2018-01-14 11:21 ` Mark Cave-Ayland
2018-01-14 13:25 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-14 11:21 UTC (permalink / raw)
To: qemu-devel; +Cc: famz, atar4qemu
On 14/01/18 11:15, no-reply@patchew.org wrote:
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Message-id: 20180114104751.21965-1-mark.cave-ayland@ilande.co.uk
> Subject: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions
(lots cut)
> === OUTPUT BEGIN ===
> Checking PATCH 1/11: apb: split simba PCI bridge into hw/pci-bridge/simba.c...
> Checking PATCH 2/11: simba: rename PBMPCIBridge and QOM types to reflect simba naming...
> Checking PATCH 3/11: apb: rename APB functions to use sabre prefix...
> Checking PATCH 4/11: apb: change pbm_pci_host prefix functions to use sabre_pci prefix...
> Checking PATCH 5/11: apb: QOMify sabre PCI host bridge...
> Checking PATCH 6/11: apb: rename QOM type from TYPE_APB to TYPE_SABRE...
> Checking PATCH 7/11: sun4u: rename apb variables and constants...
> Checking PATCH 8/11: apb: rename apb.c to sabre.c...
> ERROR: do not use C99 // comments
> #86: FILE: hw/pci-host/sabre.c:41:
> +//#define DEBUG_SABRE
>
> total: 1 errors, 0 warnings, 188 lines checked
>
> Your patch has style problems, please review. If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
>
> Checking PATCH 9/11: pci: add trace-events support for hw/pci-host...
> Checking PATCH 10/11: sabre: convert from SABRE_DPRINTF macro to trace-events...
> Checking PATCH 11/11: sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events...
> === OUTPUT END ===
>
> Test command exited with code: 1
This is fine - it's just a side-effect of renaming DEBUG_APB to
DEBUG_SABRE as part of the APB to sabre rename, and in fact this code is
completely removed in patch 10 with the conversion to tracepoints.
ATB,
Mark.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 01/11] apb: split simba PCI bridge into hw/pci-bridge/simba.c
2018-01-14 10:47 ` [Qemu-devel] [PATCH 01/11] apb: split simba PCI bridge into hw/pci-bridge/simba.c Mark Cave-Ayland
@ 2018-01-14 13:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:05 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu
Cc: qemu-devel, Marcel Apfelbaum, Michael S . Tsirkin
[-- Attachment #1: Type: text/plain, Size: 11979 bytes --]
Hi Mark,
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> Move the QOM type and macros into a new include/hw/pci-bridge/simba.h
> file, and add a new CONFIG_SIMBA Makefile.objs variable which is enabled
> for sparc64-softmmu builds only.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> CC: Michael S. Tsirkin <mst@redhat.com>
> CC: Marcel Apfelbaum <marcel@redhat.com>
> ---
> default-configs/sparc64-softmmu.mak | 1 +
> hw/pci-bridge/Makefile.objs | 2 +
> hw/pci-bridge/simba.c | 101 ++++++++++++++++++++++++++++++++++++
> hw/pci-host/apb.c | 62 +---------------------
> include/hw/pci-bridge/simba.h | 38 ++++++++++++++
> include/hw/pci-host/apb.h | 9 ----
I recommend you to use the scripts/git.orderfile, such code movement
result slightly easier to review.
> 6 files changed, 143 insertions(+), 70 deletions(-)
> create mode 100644 hw/pci-bridge/simba.c
> create mode 100644 include/hw/pci-bridge/simba.h
>
> diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-softmmu.mak
> index 3e177bbd7b..9b742a7b41 100644
> --- a/default-configs/sparc64-softmmu.mak
> +++ b/default-configs/sparc64-softmmu.mak
> @@ -12,6 +12,7 @@ CONFIG_FDC=y
> CONFIG_IDE_ISA=y
> CONFIG_IDE_CMD646=y
> CONFIG_PCI_APB=y
> +CONFIG_SIMBA=y
> CONFIG_SUNHME=y
> CONFIG_MC146818RTC=y
> CONFIG_ISA_TESTDEV=y
> diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs
> index 1b05023662..47065f87d9 100644
> --- a/hw/pci-bridge/Makefile.objs
> +++ b/hw/pci-bridge/Makefile.objs
> @@ -6,3 +6,5 @@ common-obj-$(CONFIG_IOH3420) += ioh3420.o
> common-obj-$(CONFIG_I82801B11) += i82801b11.o
> # NewWorld PowerMac
> common-obj-$(CONFIG_DEC_PCI) += dec.o
> +# Sun4u
> +common-obj-$(CONFIG_SIMBA) += simba.o
> diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c
> new file mode 100644
> index 0000000000..05ba6f0f34
> --- /dev/null
> +++ b/hw/pci-bridge/simba.c
> @@ -0,0 +1,101 @@
> +/*
> + * QEMU Simba PCI bridge
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2012,2013 Artyom Tarasenko
> + * Copyright (c) 2018 Mark Cave-Ayland
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/pci/pci.h"
> +#include "hw/pci/pci_bridge.h"
> +#include "hw/pci/pci_bus.h"
> +#include "hw/pci-bridge/simba.h"
> +
> +/*
> + * Chipset docs:
> + * APB: "Advanced PCI Bridge (APB) User's Manual",
> + * http://www.sun.com/processors/manuals/805-1251.pdf
> + */
> +
> +static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
> +{
> + /*
> + * command register:
> + * According to PCI bridge spec, after reset
> + * bus master bit is off
> + * memory space enable bit is off
> + * According to manual (805-1251.pdf).
> + * the reset value should be zero unless the boot pin is tied high
> + * (which is true) and thus it should be PCI_COMMAND_MEMORY.
> + */
> + PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);
> +
> + pci_bridge_initfn(dev, TYPE_PCI_BUS);
> +
> + pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);
> + pci_set_word(dev->config + PCI_STATUS,
> + PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
> + PCI_STATUS_DEVSEL_MEDIUM);
> +
> + /* Allow 32-bit IO addresses */
> + pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);
> + pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);
> + pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);
> + pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);
> +
> + pci_bridge_update_mappings(PCI_BRIDGE(br));
> +}
> +
> +static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> + k->realize = apb_pci_bridge_realize;
> + k->exit = pci_bridge_exitfn;
> + k->vendor_id = PCI_VENDOR_ID_SUN;
> + k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
> + k->revision = 0x11;
> + k->config_write = pci_bridge_write_config;
> + k->is_bridge = 1;
> + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
> + dc->reset = pci_bridge_reset;
> + dc->vmsd = &vmstate_pci_device;
> +}
> +
> +static const TypeInfo pbm_pci_bridge_info = {
> + .name = TYPE_PBM_PCI_BRIDGE,
> + .parent = TYPE_PCI_BRIDGE,
> + .class_init = pbm_pci_bridge_class_init,
> + .instance_size = sizeof(PBMPCIBridge),
> + .interfaces = (InterfaceInfo[]) {
> + { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> + { },
> + },
> +};
> +
> +static void pbm_register_types(void)
> +{
> + type_register_static(&pbm_pci_bridge_info);
> +}
> +
> +type_init(pbm_register_types)
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index ec676f94b6..3a5c046794 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -33,6 +33,7 @@
> #include "hw/pci/pci_host.h"
> #include "hw/pci/pci_bridge.h"
> #include "hw/pci/pci_bus.h"
> +#include "hw/pci-bridge/simba.h"
> #include "hw/pci-host/apb.h"
> #include "sysemu/sysemu.h"
> #include "exec/address-spaces.h"
> @@ -53,9 +54,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
> * Chipset docs:
> * PBM: "UltraSPARC IIi User's Manual",
> * http://www.sun.com/processors/manuals/805-0087.pdf
> - *
> - * APB: "Advanced PCI Bridge (APB) User's Manual",
> - * http://www.sun.com/processors/manuals/805-1251.pdf
> */
>
> #define PBM_PCI_IMR_MASK 0x7fffffff
> @@ -348,35 +346,6 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
> }
> }
>
> -static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
> -{
> - /*
> - * command register:
> - * According to PCI bridge spec, after reset
> - * bus master bit is off
> - * memory space enable bit is off
> - * According to manual (805-1251.pdf).
> - * the reset value should be zero unless the boot pin is tied high
> - * (which is true) and thus it should be PCI_COMMAND_MEMORY.
> - */
> - PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);
> -
> - pci_bridge_initfn(dev, TYPE_PCI_BUS);
> -
> - pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);
> - pci_set_word(dev->config + PCI_STATUS,
> - PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
> - PCI_STATUS_DEVSEL_MEDIUM);
> -
> - /* Allow 32-bit IO addresses */
> - pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);
> - pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);
> - pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);
> - pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);
> -
> - pci_bridge_update_mappings(PCI_BRIDGE(br));
> -}
> -
> static void pci_pbm_reset(DeviceState *d)
> {
> APBState *s = APB_DEVICE(d);
> @@ -564,39 +533,10 @@ static const TypeInfo pbm_host_info = {
> .class_init = pbm_host_class_init,
> };
>
> -static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(klass);
> - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> -
> - k->realize = apb_pci_bridge_realize;
> - k->exit = pci_bridge_exitfn;
> - k->vendor_id = PCI_VENDOR_ID_SUN;
> - k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
> - k->revision = 0x11;
> - k->config_write = pci_bridge_write_config;
> - k->is_bridge = 1;
> - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
> - dc->reset = pci_bridge_reset;
> - dc->vmsd = &vmstate_pci_device;
> -}
> -
> -static const TypeInfo pbm_pci_bridge_info = {
> - .name = TYPE_PBM_PCI_BRIDGE,
> - .parent = TYPE_PCI_BRIDGE,
> - .class_init = pbm_pci_bridge_class_init,
> - .instance_size = sizeof(PBMPCIBridge),
> - .interfaces = (InterfaceInfo[]) {
> - { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> - { },
> - },
> -};
> -
> static void pbm_register_types(void)
> {
> type_register_static(&pbm_host_info);
> type_register_static(&pbm_pci_host_info);
> - type_register_static(&pbm_pci_bridge_info);
> }
>
> type_init(pbm_register_types)
> diff --git a/include/hw/pci-bridge/simba.h b/include/hw/pci-bridge/simba.h
> new file mode 100644
> index 0000000000..5ab1330236
> --- /dev/null
> +++ b/include/hw/pci-bridge/simba.h
> @@ -0,0 +1,38 @@
> +/*
> + * QEMU Simba PCI bridge
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2012,2013 Artyom Tarasenko
> + * Copyright (c) 2017 Mark Cave-Ayland
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/pci/pci_bridge.h"
> +
> +
> +typedef struct PBMPCIBridge {
> + /*< private >*/
> + PCIBridge parent_obj;
> +} PBMPCIBridge;
> +
> +#define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
> +#define PBM_PCI_BRIDGE(obj) \
> + OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
> diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h
> index 604d899b1e..5e28f3e1f3 100644
> --- a/include/hw/pci-host/apb.h
> +++ b/include/hw/pci-host/apb.h
> @@ -42,13 +42,4 @@ typedef struct APBState {
> unsigned int nr_resets;
> } APBState;
>
> -typedef struct PBMPCIBridge {
> - /*< private >*/
> - PCIBridge parent_obj;
> -} PBMPCIBridge;
> -
> -#define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
> -#define PBM_PCI_BRIDGE(obj) \
> - OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
> -
> #endif
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 02/11] simba: rename PBMPCIBridge and QOM types to reflect simba naming
2018-01-14 10:47 ` [Qemu-devel] [PATCH 02/11] simba: rename PBMPCIBridge and QOM types to reflect simba naming Mark Cave-Ayland
@ 2018-01-14 13:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:05 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu; +Cc: qemu-devel
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> Here we rename PBMPCIBridge to SimbaPCIBridge and the QOM type from
> TYPE_PBM_PCI_BRIDGE to TYPE_SIMBA_PCI_BRIDGE in improve the clarity
> of the device name.
>
> Also touch up the relevant spots in apb.c and various other function
> names as appropriate.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/pci-bridge/simba.c | 22 +++++++++++-----------
> hw/pci-host/apb.c | 12 ++++++------
> include/hw/pci-bridge/simba.h | 10 +++++-----
> 3 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c
> index 05ba6f0f34..dea4c8c5e7 100644
> --- a/hw/pci-bridge/simba.c
> +++ b/hw/pci-bridge/simba.c
> @@ -36,7 +36,7 @@
> * http://www.sun.com/processors/manuals/805-1251.pdf
> */
>
> -static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
> +static void simba_pci_bridge_realize(PCIDevice *dev, Error **errp)
> {
> /*
> * command register:
> @@ -47,7 +47,7 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
> * the reset value should be zero unless the boot pin is tied high
> * (which is true) and thus it should be PCI_COMMAND_MEMORY.
> */
> - PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);
> + SimbaPCIBridge *br = SIMBA_PCI_BRIDGE(dev);
>
> pci_bridge_initfn(dev, TYPE_PCI_BUS);
>
> @@ -65,12 +65,12 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
> pci_bridge_update_mappings(PCI_BRIDGE(br));
> }
>
> -static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
> +static void simba_pci_bridge_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
>
> - k->realize = apb_pci_bridge_realize;
> + k->realize = simba_pci_bridge_realize;
> k->exit = pci_bridge_exitfn;
> k->vendor_id = PCI_VENDOR_ID_SUN;
> k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
> @@ -82,20 +82,20 @@ static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
> dc->vmsd = &vmstate_pci_device;
> }
>
> -static const TypeInfo pbm_pci_bridge_info = {
> - .name = TYPE_PBM_PCI_BRIDGE,
> +static const TypeInfo simba_pci_bridge_info = {
> + .name = TYPE_SIMBA_PCI_BRIDGE,
> .parent = TYPE_PCI_BRIDGE,
> - .class_init = pbm_pci_bridge_class_init,
> - .instance_size = sizeof(PBMPCIBridge),
> + .class_init = simba_pci_bridge_class_init,
> + .instance_size = sizeof(SimbaPCIBridge),
> .interfaces = (InterfaceInfo[]) {
> { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> { },
> },
> };
>
> -static void pbm_register_types(void)
> +static void simba_register_types(void)
> {
> - type_register_static(&pbm_pci_bridge_info);
> + type_register_static(&simba_pci_bridge_info);
> }
>
> -type_init(pbm_register_types)
> +type_init(simba_register_types)
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 3a5c046794..43ee42d170 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -293,7 +293,7 @@ static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
> return irq_num;
> }
>
> -static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num)
> {
> /* The on-board devices have fixed (legacy) OBIO intnos */
> switch (PCI_SLOT(pci_dev->devfn)) {
> @@ -311,7 +311,7 @@ static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num)
> return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
> }
>
> -static int pci_pbmB_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
> {
> return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
> }
> @@ -417,15 +417,15 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
>
> /* APB secondary busses */
> pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
> - TYPE_PBM_PCI_BRIDGE);
> + TYPE_SIMBA_PCI_BRIDGE);
> s->bridgeB = PCI_BRIDGE(pci_dev);
> - pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbmB_map_irq);
> + pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq);
> qdev_init_nofail(&pci_dev->qdev);
>
> pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
> - TYPE_PBM_PCI_BRIDGE);
> + TYPE_SIMBA_PCI_BRIDGE);
> s->bridgeA = PCI_BRIDGE(pci_dev);
> - pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbmA_map_irq);
> + pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq);
> qdev_init_nofail(&pci_dev->qdev);
> }
>
> diff --git a/include/hw/pci-bridge/simba.h b/include/hw/pci-bridge/simba.h
> index 5ab1330236..fac56ab1cf 100644
> --- a/include/hw/pci-bridge/simba.h
> +++ b/include/hw/pci-bridge/simba.h
> @@ -28,11 +28,11 @@
> #include "hw/pci/pci_bridge.h"
>
>
> -typedef struct PBMPCIBridge {
> +typedef struct SimbaPCIBridge {
> /*< private >*/
> PCIBridge parent_obj;
> -} PBMPCIBridge;
> +} SimbaPCIBridge;
>
> -#define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
> -#define PBM_PCI_BRIDGE(obj) \
> - OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
> +#define TYPE_SIMBA_PCI_BRIDGE "pbm-bridge"
> +#define SIMBA_PCI_BRIDGE(obj) \
> + OBJECT_CHECK(SimbaPCIBridge, (obj), TYPE_SIMBA_PCI_BRIDGE)
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 03/11] apb: rename APB functions to use sabre prefix
2018-01-14 10:47 ` [Qemu-devel] [PATCH 03/11] apb: rename APB functions to use sabre prefix Mark Cave-Ayland
@ 2018-01-14 13:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:08 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu; +Cc: qemu-devel
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> As hinted in the comment at the top of the file, the naming convention for the
> APB types/QOM functions isn't correct. As a starting point we can at least
> rename the APB type and related functions to improve the readability of apb.c.
comment you remove later, ok.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/pci-host/apb.c | 109 +++++++++++++++++++++++-----------------------
> include/hw/pci-host/apb.h | 1 -
> 2 files changed, 54 insertions(+), 56 deletions(-)
>
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 43ee42d170..d5c459a2df 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
>
> #define NO_IRQ_REQUEST (MAX_IVEC + 1)
>
> -static inline void pbm_set_request(APBState *s, unsigned int irq_num)
> +static inline void sabre_set_request(APBState *s, unsigned int irq_num)
> {
> APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
>
> @@ -78,14 +78,13 @@ static inline void pbm_set_request(APBState *s, unsigned int irq_num)
> qemu_set_irq(s->ivec_irqs[irq_num], 1);
> }
>
> -static inline void pbm_check_irqs(APBState *s)
> +static inline void sabre_check_irqs(APBState *s)
> {
> -
> unsigned int i;
>
> /* Previous request is not acknowledged, resubmit */
> if (s->irq_request != NO_IRQ_REQUEST) {
> - pbm_set_request(s, s->irq_request);
> + sabre_set_request(s, s->irq_request);
> return;
> }
> /* no request pending */
> @@ -95,7 +94,7 @@ static inline void pbm_check_irqs(APBState *s)
> for (i = 0; i < 32; i++) {
> if (s->pci_irq_in & (1ULL << i)) {
> if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
> - pbm_set_request(s, i);
> + sabre_set_request(s, i);
> return;
> }
> }
> @@ -103,28 +102,28 @@ static inline void pbm_check_irqs(APBState *s)
> for (i = 32; i < 64; i++) {
> if (s->pci_irq_in & (1ULL << i)) {
> if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
> - pbm_set_request(s, i);
> + sabre_set_request(s, i);
> break;
> }
> }
> }
> }
>
> -static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
> +static inline void sabre_clear_request(APBState *s, unsigned int irq_num)
> {
> APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
> qemu_set_irq(s->ivec_irqs[irq_num], 0);
> s->irq_request = NO_IRQ_REQUEST;
> }
>
> -static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
> +static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
> {
> IOMMUState *is = opaque;
>
> return &is->iommu_as;
> }
>
> -static void apb_config_writel (void *opaque, hwaddr addr,
> +static void sabre_config_write(void *opaque, hwaddr addr,
> uint64_t val, unsigned size)
> {
> APBState *s = opaque;
> @@ -141,9 +140,9 @@ static void apb_config_writel (void *opaque, hwaddr addr,
> s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
> s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
> if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
> - pbm_clear_request(s, ino);
> + sabre_clear_request(s, ino);
> }
> - pbm_check_irqs(s);
> + sabre_check_irqs(s);
> }
> break;
> case 0x1000 ... 0x107f: /* OBIO interrupt control */
> @@ -153,17 +152,17 @@ static void apb_config_writel (void *opaque, hwaddr addr,
> s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
> if ((s->irq_request == (ino | 0x20))
> && !(val & ~PBM_PCI_IMR_MASK)) {
> - pbm_clear_request(s, ino | 0x20);
> + sabre_clear_request(s, ino | 0x20);
> }
> - pbm_check_irqs(s);
> + sabre_check_irqs(s);
> }
> break;
> case 0x1400 ... 0x14ff: /* PCI interrupt clear */
> if (addr & 4) {
> unsigned int ino = (addr & 0xff) >> 5;
> if ((s->irq_request / 4) == ino) {
> - pbm_clear_request(s, s->irq_request);
> - pbm_check_irqs(s);
> + sabre_clear_request(s, s->irq_request);
> + sabre_check_irqs(s);
> }
> }
> break;
> @@ -171,8 +170,8 @@ static void apb_config_writel (void *opaque, hwaddr addr,
> if (addr & 4) {
> unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
> if (s->irq_request == ino) {
> - pbm_clear_request(s, ino);
> - pbm_check_irqs(s);
> + sabre_clear_request(s, ino);
> + sabre_check_irqs(s);
> }
> }
> break;
> @@ -202,7 +201,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
> }
> }
>
> -static uint64_t apb_config_readl (void *opaque,
> +static uint64_t sabre_config_read(void *opaque,
> hwaddr addr, unsigned size)
> {
> APBState *s = opaque;
> @@ -258,14 +257,14 @@ static uint64_t apb_config_readl (void *opaque,
> return val;
> }
>
> -static const MemoryRegionOps apb_config_ops = {
> - .read = apb_config_readl,
> - .write = apb_config_writel,
> +static const MemoryRegionOps sabre_config_ops = {
> + .read = sabre_config_read,
> + .write = sabre_config_write,
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> -static void apb_pci_config_write(void *opaque, hwaddr addr,
> - uint64_t val, unsigned size)
> +static void sabre_pci_config_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> {
> APBState *s = opaque;
> PCIHostState *phb = PCI_HOST_BRIDGE(s);
> @@ -274,8 +273,8 @@ static void apb_pci_config_write(void *opaque, hwaddr addr,
> pci_data_write(phb->bus, addr, val, size);
> }
>
> -static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
> - unsigned size)
> +static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
> + unsigned size)
> {
> uint32_t ret;
> APBState *s = opaque;
> @@ -286,8 +285,8 @@ static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
> return ret;
> }
>
> -/* The APB host has an IRQ line for each IRQ line of each slot. */
> -static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
> +/* The sabre host has an IRQ line for each IRQ line of each slot. */
> +static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num)
> {
> /* Return the irq as swizzled by the PBM */
> return irq_num;
> @@ -316,7 +315,7 @@ static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
> return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
> }
>
> -static void pci_apb_set_irq(void *opaque, int irq_num, int level)
> +static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
> {
> APBState *s = opaque;
>
> @@ -326,7 +325,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
> if (level) {
> s->pci_irq_in |= 1ULL << irq_num;
> if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
> - pbm_set_request(s, irq_num);
> + sabre_set_request(s, irq_num);
> }
> } else {
> s->pci_irq_in &= ~(1ULL << irq_num);
> @@ -338,7 +337,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
> s->pci_irq_in |= 1ULL << irq_num;
> if ((s->irq_request == NO_IRQ_REQUEST)
> && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
> - pbm_set_request(s, irq_num);
> + sabre_set_request(s, irq_num);
> }
> } else {
> s->pci_irq_in &= ~(1ULL << irq_num);
> @@ -346,7 +345,7 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
> }
> }
>
> -static void pci_pbm_reset(DeviceState *d)
> +static void sabre_reset(DeviceState *d)
> {
> APBState *s = APB_DEVICE(d);
> PCIDevice *pci_dev;
> @@ -379,12 +378,12 @@ static void pci_pbm_reset(DeviceState *d)
> }
>
> static const MemoryRegionOps pci_config_ops = {
> - .read = apb_pci_config_read,
> - .write = apb_pci_config_write,
> + .read = sabre_pci_config_read,
> + .write = sabre_pci_config_write,
> .endianness = DEVICE_LITTLE_ENDIAN,
> };
>
> -static void pci_pbm_realize(DeviceState *dev, Error **errp)
> +static void sabre_realize(DeviceState *dev, Error **errp)
> {
> APBState *s = APB_DEVICE(dev);
> PCIHostState *phb = PCI_HOST_BRIDGE(dev);
> @@ -403,17 +402,17 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
> &s->pci_mmio);
>
> phb->bus = pci_register_root_bus(dev, "pci",
> - pci_apb_set_irq, pci_apb_map_irq, s,
> + pci_sabre_set_irq, pci_sabre_map_irq, s,
> &s->pci_mmio,
> &s->pci_ioport,
> 0, 32, TYPE_PCI_BUS);
>
> pci_create_simple(phb->bus, 0, "pbm-pci");
>
> - /* APB IOMMU */
> + /* IOMMU */
> memory_region_add_subregion_overlap(&s->apb_config, 0x200,
> sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
> - pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, s->iommu);
> + pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
>
> /* APB secondary busses */
> pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
> @@ -429,7 +428,7 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
> qdev_init_nofail(&pci_dev->qdev);
> }
>
> -static void pci_pbm_init(Object *obj)
> +static void sabre_init(Object *obj)
> {
> APBState *s = APB_DEVICE(obj);
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> @@ -444,7 +443,7 @@ static void pci_pbm_init(Object *obj)
> for (i = 0; i < 32; i++) {
> s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
> }
> - qdev_init_gpio_in_named(DEVICE(s), pci_apb_set_irq, "pbm-irq", MAX_IVEC);
> + qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC);
> qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC);
> s->irq_request = NO_IRQ_REQUEST;
> s->pci_irq_in = 0ULL;
> @@ -456,7 +455,7 @@ static void pci_pbm_init(Object *obj)
> 0, NULL);
>
> /* apb_config */
> - memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
> + memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s,
> "apb-config", 0x10000);
> /* at region 0 */
> sysbus_init_mmio(sbd, &s->apb_config);
> @@ -473,7 +472,7 @@ static void pci_pbm_init(Object *obj)
> sysbus_init_mmio(sbd, &s->pci_ioport);
> }
>
> -static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
> +static void sabre_pci_host_realize(PCIDevice *d, Error **errp)
> {
> pci_set_word(d->config + PCI_COMMAND,
> PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
> @@ -482,12 +481,12 @@ static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
> PCI_STATUS_DEVSEL_MEDIUM);
> }
>
> -static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
> +static void sabre_pci_host_class_init(ObjectClass *klass, void *data)
> {
> PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> - k->realize = pbm_pci_host_realize;
> + k->realize = sabre_pci_host_realize;
> k->vendor_id = PCI_VENDOR_ID_SUN;
> k->device_id = PCI_DEVICE_ID_SUN_SABRE;
> k->class_id = PCI_CLASS_BRIDGE_HOST;
> @@ -502,41 +501,41 @@ static const TypeInfo pbm_pci_host_info = {
> .name = "pbm-pci",
> .parent = TYPE_PCI_DEVICE,
> .instance_size = sizeof(PCIDevice),
> - .class_init = pbm_pci_host_class_init,
> + .class_init = sabre_pci_host_class_init,
> .interfaces = (InterfaceInfo[]) {
> { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> { },
> },
> };
>
> -static Property pbm_pci_host_properties[] = {
> +static Property sabre_properties[] = {
> DEFINE_PROP_UINT64("special-base", APBState, special_base, 0),
> DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> -static void pbm_host_class_init(ObjectClass *klass, void *data)
> +static void sabre_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> - dc->realize = pci_pbm_realize;
> - dc->reset = pci_pbm_reset;
> - dc->props = pbm_pci_host_properties;
> + dc->realize = sabre_realize;
> + dc->reset = sabre_reset;
> + dc->props = sabre_properties;
> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
> }
>
> -static const TypeInfo pbm_host_info = {
> +static const TypeInfo sabre_info = {
> .name = TYPE_APB,
> .parent = TYPE_PCI_HOST_BRIDGE,
> .instance_size = sizeof(APBState),
> - .instance_init = pci_pbm_init,
> - .class_init = pbm_host_class_init,
> + .instance_init = sabre_init,
> + .class_init = sabre_class_init,
> };
>
> -static void pbm_register_types(void)
> +static void sabre_register_types(void)
> {
> - type_register_static(&pbm_host_info);
> + type_register_static(&sabre_info);
> type_register_static(&pbm_pci_host_info);
> }
>
> -type_init(pbm_register_types)
> +type_init(sabre_register_types)
> diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h
> index 5e28f3e1f3..41de012396 100644
> --- a/include/hw/pci-host/apb.h
> +++ b/include/hw/pci-host/apb.h
> @@ -15,7 +15,6 @@
> #define OBIO_SER_IRQ 0x2b
>
> #define TYPE_APB "pbm"
> -
> #define APB_DEVICE(obj) \
> OBJECT_CHECK(APBState, (obj), TYPE_APB)
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 04/11] apb: change pbm_pci_host prefix functions to use sabre_pci prefix
2018-01-14 10:47 ` [Qemu-devel] [PATCH 04/11] apb: change pbm_pci_host prefix functions to use sabre_pci prefix Mark Cave-Ayland
@ 2018-01-14 13:09 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:09 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, atar4qemu
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> This is the proper name for the PBM host bridge as referenced in the Sun
> documentation.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/pci-host/apb.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index d5c459a2df..98c5f344f7 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -472,7 +472,7 @@ static void sabre_init(Object *obj)
> sysbus_init_mmio(sbd, &s->pci_ioport);
> }
>
> -static void sabre_pci_host_realize(PCIDevice *d, Error **errp)
> +static void sabre_pci_realize(PCIDevice *d, Error **errp)
> {
> pci_set_word(d->config + PCI_COMMAND,
> PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
> @@ -481,12 +481,12 @@ static void sabre_pci_host_realize(PCIDevice *d, Error **errp)
> PCI_STATUS_DEVSEL_MEDIUM);
> }
>
> -static void sabre_pci_host_class_init(ObjectClass *klass, void *data)
> +static void sabre_pci_class_init(ObjectClass *klass, void *data)
> {
> PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> - k->realize = sabre_pci_host_realize;
> + k->realize = sabre_pci_realize;
> k->vendor_id = PCI_VENDOR_ID_SUN;
> k->device_id = PCI_DEVICE_ID_SUN_SABRE;
> k->class_id = PCI_CLASS_BRIDGE_HOST;
> @@ -497,11 +497,11 @@ static void sabre_pci_host_class_init(ObjectClass *klass, void *data)
> dc->user_creatable = false;
> }
>
> -static const TypeInfo pbm_pci_host_info = {
> +static const TypeInfo sabre_pci_info = {
> .name = "pbm-pci",
> .parent = TYPE_PCI_DEVICE,
> .instance_size = sizeof(PCIDevice),
> - .class_init = sabre_pci_host_class_init,
> + .class_init = sabre_pci_class_init,
> .interfaces = (InterfaceInfo[]) {
> { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> { },
> @@ -535,7 +535,7 @@ static const TypeInfo sabre_info = {
> static void sabre_register_types(void)
> {
> type_register_static(&sabre_info);
> - type_register_static(&pbm_pci_host_info);
> + type_register_static(&sabre_pci_info);
> }
>
> type_init(sabre_register_types)
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 05/11] apb: QOMify sabre PCI host bridge
2018-01-14 10:47 ` [Qemu-devel] [PATCH 05/11] apb: QOMify sabre PCI host bridge Mark Cave-Ayland
@ 2018-01-14 13:13 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:13 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu; +Cc: qemu-devel
Hi Mark,
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This device is already QOM'ified, but now the QOM abstract inheritance
is clearer, so:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/pci-host/apb.c | 6 +++---
> include/hw/pci-host/apb.h | 14 +++++++++++---
> 2 files changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 98c5f344f7..36c6251816 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -407,7 +407,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
> &s->pci_ioport,
> 0, 32, TYPE_PCI_BUS);
>
> - pci_create_simple(phb->bus, 0, "pbm-pci");
> + pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
>
> /* IOMMU */
> memory_region_add_subregion_overlap(&s->apb_config, 0x200,
> @@ -498,9 +498,9 @@ static void sabre_pci_class_init(ObjectClass *klass, void *data)
> }
>
> static const TypeInfo sabre_pci_info = {
> - .name = "pbm-pci",
> + .name = TYPE_SABRE_PCI_DEVICE,
> .parent = TYPE_PCI_DEVICE,
> - .instance_size = sizeof(PCIDevice),
> + .instance_size = sizeof(SabrePCIState),
> .class_init = sabre_pci_class_init,
> .interfaces = (InterfaceInfo[]) {
> { INTERFACE_CONVENTIONAL_PCI_DEVICE },
> diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h
> index 41de012396..470863639a 100644
> --- a/include/hw/pci-host/apb.h
> +++ b/include/hw/pci-host/apb.h
> @@ -14,9 +14,13 @@
> #define OBIO_MSE_IRQ 0x2a
> #define OBIO_SER_IRQ 0x2b
>
> -#define TYPE_APB "pbm"
> -#define APB_DEVICE(obj) \
> - OBJECT_CHECK(APBState, (obj), TYPE_APB)
> +typedef struct SabrePCIState {
> + PCIDevice parent_obj;
> +} SabrePCIState;
> +
> +#define TYPE_SABRE_PCI_DEVICE "sabre-pci"
> +#define SABRE_PCI_DEVICE(obj) \
> + OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
>
> typedef struct APBState {
> PCIHostState parent_obj;
> @@ -41,4 +45,8 @@ typedef struct APBState {
> unsigned int nr_resets;
> } APBState;
>
> +#define TYPE_APB "apb"
> +#define APB_DEVICE(obj) \
> + OBJECT_CHECK(APBState, (obj), TYPE_APB)
> +
> #endif
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 06/11] apb: rename QOM type from TYPE_APB to TYPE_SABRE
2018-01-14 10:47 ` [Qemu-devel] [PATCH 06/11] apb: rename QOM type from TYPE_APB to TYPE_SABRE Mark Cave-Ayland
@ 2018-01-14 13:15 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:15 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu; +Cc: qemu-devel
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> Similarly rename the corresponding APBState typedef to SabreState.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/pci-host/apb.c | 30 +++++++++++++++---------------
> hw/sparc64/sun4u.c | 6 +++---
> include/hw/pci-host/apb.h | 10 +++++-----
> 3 files changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 36c6251816..f6c5dbd469 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
>
> #define NO_IRQ_REQUEST (MAX_IVEC + 1)
>
> -static inline void sabre_set_request(APBState *s, unsigned int irq_num)
> +static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
> {
> APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
>
> @@ -78,7 +78,7 @@ static inline void sabre_set_request(APBState *s, unsigned int irq_num)
> qemu_set_irq(s->ivec_irqs[irq_num], 1);
> }
>
> -static inline void sabre_check_irqs(APBState *s)
> +static inline void sabre_check_irqs(SabreState *s)
> {
> unsigned int i;
>
> @@ -109,7 +109,7 @@ static inline void sabre_check_irqs(APBState *s)
> }
> }
>
> -static inline void sabre_clear_request(APBState *s, unsigned int irq_num)
> +static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
> {
> APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
> qemu_set_irq(s->ivec_irqs[irq_num], 0);
> @@ -126,7 +126,7 @@ static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
> static void sabre_config_write(void *opaque, hwaddr addr,
> uint64_t val, unsigned size)
> {
> - APBState *s = opaque;
> + SabreState *s = opaque;
>
> APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
>
> @@ -204,7 +204,7 @@ static void sabre_config_write(void *opaque, hwaddr addr,
> static uint64_t sabre_config_read(void *opaque,
> hwaddr addr, unsigned size)
> {
> - APBState *s = opaque;
> + SabreState *s = opaque;
> uint32_t val;
>
> switch (addr & 0xffff) {
> @@ -266,7 +266,7 @@ static const MemoryRegionOps sabre_config_ops = {
> static void sabre_pci_config_write(void *opaque, hwaddr addr,
> uint64_t val, unsigned size)
> {
> - APBState *s = opaque;
> + SabreState *s = opaque;
> PCIHostState *phb = PCI_HOST_BRIDGE(s);
>
> APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
> @@ -277,7 +277,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
> unsigned size)
> {
> uint32_t ret;
> - APBState *s = opaque;
> + SabreState *s = opaque;
> PCIHostState *phb = PCI_HOST_BRIDGE(s);
>
> ret = pci_data_read(phb->bus, addr, size);
> @@ -317,7 +317,7 @@ static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
>
> static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
> {
> - APBState *s = opaque;
> + SabreState *s = opaque;
>
> APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
> /* PCI IRQ map onto the first 32 INO. */
> @@ -347,7 +347,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
>
> static void sabre_reset(DeviceState *d)
> {
> - APBState *s = APB_DEVICE(d);
> + SabreState *s = SABRE_DEVICE(d);
> PCIDevice *pci_dev;
> unsigned int i;
> uint16_t cmd;
> @@ -385,7 +385,7 @@ static const MemoryRegionOps pci_config_ops = {
>
> static void sabre_realize(DeviceState *dev, Error **errp)
> {
> - APBState *s = APB_DEVICE(dev);
> + SabreState *s = SABRE_DEVICE(dev);
> PCIHostState *phb = PCI_HOST_BRIDGE(dev);
> SysBusDevice *sbd = SYS_BUS_DEVICE(s);
> PCIDevice *pci_dev;
> @@ -430,7 +430,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
>
> static void sabre_init(Object *obj)
> {
> - APBState *s = APB_DEVICE(obj);
> + SabreState *s = SABRE_DEVICE(obj);
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> unsigned int i;
>
> @@ -509,8 +509,8 @@ static const TypeInfo sabre_pci_info = {
> };
>
> static Property sabre_properties[] = {
> - DEFINE_PROP_UINT64("special-base", APBState, special_base, 0),
> - DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0),
> + DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0),
> + DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -525,9 +525,9 @@ static void sabre_class_init(ObjectClass *klass, void *data)
> }
>
> static const TypeInfo sabre_info = {
> - .name = TYPE_APB,
> + .name = TYPE_SABRE,
> .parent = TYPE_PCI_HOST_BRIDGE,
> - .instance_size = sizeof(APBState),
> + .instance_size = sizeof(SabreState),
> .instance_init = sabre_init,
> .class_init = sabre_class_init,
> };
> diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
> index ec45ec2801..b8f685847a 100644
> --- a/hw/sparc64/sun4u.c
> +++ b/hw/sparc64/sun4u.c
> @@ -465,7 +465,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
> Nvram *nvram;
> unsigned int i;
> uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
> - APBState *apb;
> + SabreState *apb;
> PCIBus *pci_bus, *pci_busA, *pci_busB;
> PCIDevice *ebus, *pci_dev;
> SysBusDevice *s;
> @@ -488,8 +488,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>
> prom_init(hwdef->prom_addr, bios_name);
>
> - /* Init APB (PCI host bridge) */
> - apb = APB_DEVICE(qdev_create(NULL, TYPE_APB));
> + /* Init sabre (PCI host bridge) */
> + apb = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
> qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
> qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
> object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort);
> diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h
> index 470863639a..2552f3c984 100644
> --- a/include/hw/pci-host/apb.h
> +++ b/include/hw/pci-host/apb.h
> @@ -22,7 +22,7 @@ typedef struct SabrePCIState {
> #define SABRE_PCI_DEVICE(obj) \
> OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
>
> -typedef struct APBState {
> +typedef struct SabreState {
> PCIHostState parent_obj;
>
> hwaddr special_base;
> @@ -43,10 +43,10 @@ typedef struct APBState {
> unsigned int irq_request;
> uint32_t reset_control;
> unsigned int nr_resets;
> -} APBState;
> +} SabreState;
>
> -#define TYPE_APB "apb"
> -#define APB_DEVICE(obj) \
> - OBJECT_CHECK(APBState, (obj), TYPE_APB)
> +#define TYPE_SABRE "sabre"
> +#define SABRE_DEVICE(obj) \
> + OBJECT_CHECK(SabreState, (obj), TYPE_SABRE)
>
> #endif
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 07/11] sun4u: rename apb variables and constants
2018-01-14 10:47 ` [Qemu-devel] [PATCH 07/11] sun4u: rename apb variables and constants Mark Cave-Ayland
@ 2018-01-14 13:20 ` Philippe Mathieu-Daudé
2018-01-15 18:26 ` Mark Cave-Ayland
0 siblings, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:20 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu; +Cc: qemu-devel
Hi Mark,
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> In order to reflect the previous change of TYPE_APB to TYPE_SABRE, update
> the corresponding variable names to keep the terminology consistent.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/sparc64/sun4u.c | 41 +++++++++++++++++++++--------------------
> 1 file changed, 21 insertions(+), 20 deletions(-)
>
> diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
> index b8f685847a..fb18afaaa6 100644
> --- a/hw/sparc64/sun4u.c
> +++ b/hw/sparc64/sun4u.c
> @@ -55,9 +55,9 @@
> #define CMDLINE_ADDR 0x003ff000
> #define PROM_SIZE_MAX (4 * 1024 * 1024)
> #define PROM_VADDR 0x000ffd00000ULL
> -#define APB_SPECIAL_BASE 0x1fe00000000ULL
> -#define APB_MEM_BASE 0x1ff00000000ULL
> -#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
> +#define PBM_SPECIAL_BASE 0x1fe00000000ULL
> +#define PBM_MEM_BASE 0x1ff00000000ULL
> +#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
> #define PROM_FILENAME "openbios-sparc64"
> #define NVRAM_SIZE 0x2000
> #define MAX_IDE_BUS 2
> @@ -465,7 +465,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
> Nvram *nvram;
> unsigned int i;
> uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
> - SabreState *apb;
> + SabreState *sabre;
> PCIBus *pci_bus, *pci_busA, *pci_busB;
> PCIDevice *ebus, *pci_dev;
> SysBusDevice *s;
> @@ -489,23 +489,24 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
> prom_init(hwdef->prom_addr, bios_name);
>
> /* Init sabre (PCI host bridge) */
> - apb = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
> - qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
> - qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
> - object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort);
> - qdev_init_nofail(DEVICE(apb));
> + sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
> + qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
> + qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
> + object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
> + &error_abort);
> + qdev_init_nofail(DEVICE(sabre));
>
> /* Wire up PCI interrupts to CPU */
> for (i = 0; i < IVEC_MAX; i++) {
> - qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i,
> + qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
> qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
> }
>
> - pci_bus = PCI_HOST_BRIDGE(apb)->bus;
> - pci_busA = pci_bridge_get_sec_bus(apb->bridgeA);
> - pci_busB = pci_bridge_get_sec_bus(apb->bridgeB);
> + pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
> + pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
> + pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
>
> - /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
> + /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
This single change might go in patch #2 instead.
Anyway:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> reserved (leaving no slots free after on-board devices) however slots
> 0-3 are free on busB */
> pci_bus->slot_reserved_mask = 0xfffffffc;
> @@ -517,17 +518,17 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
> hwdef->console_serial_base);
> qdev_init_nofail(DEVICE(ebus));
>
> - /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */
> + /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
> qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
> - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ));
> + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
> qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
> - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ));
> + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
> qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
> - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ));
> + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
> qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
> - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ));
> + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
> qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
> - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ));
> + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
>
> pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions
2018-01-14 11:21 ` Mark Cave-Ayland
@ 2018-01-14 13:25 ` Philippe Mathieu-Daudé
2018-01-15 18:38 ` Mark Cave-Ayland
0 siblings, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:25 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel; +Cc: famz, atar4qemu
On 01/14/2018 08:21 AM, Mark Cave-Ayland wrote:
> On 14/01/18 11:15, no-reply@patchew.org wrote:
>> Hi,
>>
>> This series seems to have some coding style problems. See output below
>> for
>> more information:
>>
>> Type: series
>> Message-id: 20180114104751.21965-1-mark.cave-ayland@ilande.co.uk
>> Subject: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and
>> tracepoint conversions
>
> (lots cut)
>
>> === OUTPUT BEGIN ===
>> Checking PATCH 1/11: apb: split simba PCI bridge into
>> hw/pci-bridge/simba.c...
>> Checking PATCH 2/11: simba: rename PBMPCIBridge and QOM types to
>> reflect simba naming...
>> Checking PATCH 3/11: apb: rename APB functions to use sabre prefix...
>> Checking PATCH 4/11: apb: change pbm_pci_host prefix functions to use
>> sabre_pci prefix...
>> Checking PATCH 5/11: apb: QOMify sabre PCI host bridge...
>> Checking PATCH 6/11: apb: rename QOM type from TYPE_APB to TYPE_SABRE...
>> Checking PATCH 7/11: sun4u: rename apb variables and constants...
>> Checking PATCH 8/11: apb: rename apb.c to sabre.c...
>> ERROR: do not use C99 // comments
>> #86: FILE: hw/pci-host/sabre.c:41:
>> +//#define DEBUG_SABRE
>>
>> total: 1 errors, 0 warnings, 188 lines checked
>>
>> Your patch has style problems, please review. If any of these errors
>> are false positives report them to the maintainer, see
>> CHECKPATCH in MAINTAINERS.
>>
>> Checking PATCH 9/11: pci: add trace-events support for hw/pci-host...
>> Checking PATCH 10/11: sabre: convert from SABRE_DPRINTF macro to
>> trace-events...
>> Checking PATCH 11/11: sparc64: convert hw/sparc64/sparc64.c from
>> DPRINTF macros to trace events...
>> === OUTPUT END ===
>>
>> Test command exited with code: 1
>
> This is fine - it's just a side-effect of renaming DEBUG_APB to
> DEBUG_SABRE as part of the APB to sabre rename, and in fact this code is
> completely removed in patch 10 with the conversion to tracepoints.
This can be avoided moving patch #8 after #10, although not worthy IMHO.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 08/11] apb: rename apb.c to sabre.c
2018-01-14 10:47 ` [Qemu-devel] [PATCH 08/11] apb: rename apb.c to sabre.c Mark Cave-Ayland
@ 2018-01-14 13:30 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:30 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu; +Cc: qemu-devel
Hi Mark,
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> This is the final stage in correcting the naming convention with respect to
> sabre, APB and PBM. It is effectively a file rename from apb.c to sabre.c
> along with touching up a few constants to remove the remaining references
> to APB.
>
> Note that as part of the rename process the configuration variable
> CONFIG_PCI_APB is changed to CONFIG_PCI_SABRE.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> default-configs/sparc64-softmmu.mak | 2 +-
> hw/pci-host/Makefile.objs | 2 +-
> hw/pci-host/{apb.c => sabre.c} | 57 +++++++++++++++++-----------------
> hw/sparc64/sun4u.c | 2 +-
> include/hw/pci-host/{apb.h => sabre.h} | 2 +-
> 5 files changed, 33 insertions(+), 32 deletions(-)
> rename hw/pci-host/{apb.c => sabre.c} (91%)
> rename include/hw/pci-host/{apb.h => sabre.h} (97%)
>
> diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-softmmu.mak
> index 9b742a7b41..52edafe547 100644
> --- a/default-configs/sparc64-softmmu.mak
> +++ b/default-configs/sparc64-softmmu.mak
> @@ -11,7 +11,7 @@ CONFIG_PCKBD=y
> CONFIG_FDC=y
> CONFIG_IDE_ISA=y
> CONFIG_IDE_CMD646=y
> -CONFIG_PCI_APB=y
> +CONFIG_PCI_SABRE=y
> CONFIG_SIMBA=y
> CONFIG_SUNHME=y
> CONFIG_MC146818RTC=y
> diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
> index 9c7909cf44..4b69f737b5 100644
> --- a/hw/pci-host/Makefile.objs
> +++ b/hw/pci-host/Makefile.objs
> @@ -11,7 +11,7 @@ common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o
> # ARM devices
> common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
>
> -common-obj-$(CONFIG_PCI_APB) += apb.o
> +common-obj-$(CONFIG_PCI_SABRE) += sabre.o
> common-obj-$(CONFIG_FULONG) += bonito.o
> common-obj-$(CONFIG_PCI_PIIX) += piix.o
> common-obj-$(CONFIG_PCI_Q35) += q35.o
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/sabre.c
> similarity index 91%
> rename from hw/pci-host/apb.c
> rename to hw/pci-host/sabre.c
> index f6c5dbd469..4054c17598 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/sabre.c
> @@ -1,8 +1,9 @@
> /*
> - * QEMU Ultrasparc APB PCI host
> + * QEMU Ultrasparc Sabre PCI host (PBM)
> *
> * Copyright (c) 2006 Fabrice Bellard
> * Copyright (c) 2012,2013 Artyom Tarasenko
> + * Copyright (c) 2018 Mark Cave-Ayland
> *
> * Permission is hereby granted, free of charge, to any person obtaining a copy
> * of this software and associated documentation files (the "Software"), to deal
> @@ -23,10 +24,6 @@
> * THE SOFTWARE.
> */
>
> -/* XXX This file and most of its contents are somewhat misnamed. The
> - Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
> - the secondary PCI bridge. */
> -
> #include "qemu/osdep.h"
> #include "hw/sysbus.h"
> #include "hw/pci/pci.h"
> @@ -34,20 +31,20 @@
> #include "hw/pci/pci_bridge.h"
> #include "hw/pci/pci_bus.h"
> #include "hw/pci-bridge/simba.h"
> -#include "hw/pci-host/apb.h"
> +#include "hw/pci-host/sabre.h"
> #include "sysemu/sysemu.h"
> #include "exec/address-spaces.h"
> #include "qapi/error.h"
> #include "qemu/log.h"
>
> -/* debug APB */
> -//#define DEBUG_APB
> +/* debug sabre */
> +//#define DEBUG_SABRE
>
> -#ifdef DEBUG_APB
> -#define APB_DPRINTF(fmt, ...) \
> -do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
> +#ifdef DEBUG_SABRE
> +#define SABRE_DPRINTF(fmt, ...) \
> +do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
> #else
> -#define APB_DPRINTF(fmt, ...)
> +#define SABRE_DPRINTF(fmt, ...)
I wouldn't worry about APB_DPRINTF and directly remove it in patch #10.
> #endif
>
> /*
> @@ -72,7 +69,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
>
> static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
> {
> - APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
> + SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num);
>
> s->irq_request = irq_num;
> qemu_set_irq(s->ivec_irqs[irq_num], 1);
> @@ -111,7 +108,7 @@ static inline void sabre_check_irqs(SabreState *s)
>
> static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
> {
> - APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
> + SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
> qemu_set_irq(s->ivec_irqs[irq_num], 0);
> s->irq_request = NO_IRQ_REQUEST;
> }
> @@ -128,7 +125,8 @@ static void sabre_config_write(void *opaque, hwaddr addr,
> {
> SabreState *s = opaque;
>
> - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
> + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
> + addr, val);
>
> switch (addr & 0xffff) {
> case 0x30 ... 0x4f: /* DMA error registers */
> @@ -252,7 +250,7 @@ static uint64_t sabre_config_read(void *opaque,
> val = 0;
> break;
> }
> - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
> + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
>
> return val;
> }
> @@ -269,7 +267,8 @@ static void sabre_pci_config_write(void *opaque, hwaddr addr,
> SabreState *s = opaque;
> PCIHostState *phb = PCI_HOST_BRIDGE(s);
>
> - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
> + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
> + addr, val);
> pci_data_write(phb->bus, addr, val, size);
> }
>
> @@ -281,7 +280,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
> PCIHostState *phb = PCI_HOST_BRIDGE(s);
>
> ret = pci_data_read(phb->bus, addr, size);
> - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
> + SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
> return ret;
> }
>
> @@ -319,7 +318,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
> {
> SabreState *s = opaque;
>
> - APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
> + SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
> /* PCI IRQ map onto the first 32 INO. */
> if (irq_num < 32) {
> if (level) {
> @@ -333,7 +332,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
> } else {
> /* OBIO IRQ map onto the next 32 INO. */
> if (level) {
> - APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
> + SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num,
> + level);
> s->pci_irq_in |= 1ULL << irq_num;
> if ((s->irq_request == NO_IRQ_REQUEST)
> && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
> @@ -390,7 +390,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
> SysBusDevice *sbd = SYS_BUS_DEVICE(s);
> PCIDevice *pci_dev;
>
> - /* apb_config */
> + /* sabre_config */
> sysbus_mmio_map(sbd, 0, s->special_base);
> /* PCI configuration space */
> sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
> @@ -410,7 +410,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
> pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
>
> /* IOMMU */
> - memory_region_add_subregion_overlap(&s->apb_config, 0x200,
> + memory_region_add_subregion_overlap(&s->sabre_config, 0x200,
> sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
> pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
>
> @@ -454,19 +454,20 @@ static void sabre_init(Object *obj)
> qdev_prop_allow_set_link_before_realize,
> 0, NULL);
>
> - /* apb_config */
> - memory_region_init_io(&s->apb_config, OBJECT(s), &sabre_config_ops, s,
> - "apb-config", 0x10000);
> + /* sabre_config */
> + memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
> + "sabre-config", 0x10000);
> /* at region 0 */
> - sysbus_init_mmio(sbd, &s->apb_config);
> + sysbus_init_mmio(sbd, &s->sabre_config);
>
> memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
> - "apb-pci-config", 0x1000000);
> + "sabre-pci-config", 0x1000000);
> /* at region 1 */
> sysbus_init_mmio(sbd, &s->pci_config);
>
> /* pci_ioport */
> - memory_region_init(&s->pci_ioport, OBJECT(s), "apb-pci-ioport", 0x1000000);
> + memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport",
> + 0x1000000);
>
> /* at region 2 */
> sysbus_init_mmio(sbd, &s->pci_ioport);
> diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
> index fb18afaaa6..c4eff6bea2 100644
> --- a/hw/sparc64/sun4u.c
> +++ b/hw/sparc64/sun4u.c
> @@ -30,7 +30,7 @@
> #include "hw/pci/pci_bridge.h"
> #include "hw/pci/pci_bus.h"
> #include "hw/pci/pci_host.h"
> -#include "hw/pci-host/apb.h"
> +#include "hw/pci-host/sabre.h"
> #include "hw/i386/pc.h"
> #include "hw/char/serial.h"
> #include "hw/timer/m48t59.h"
> diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/sabre.h
> similarity index 97%
> rename from include/hw/pci-host/apb.h
> rename to include/hw/pci-host/sabre.h
> index 2552f3c984..0f2ccc01c6 100644
> --- a/include/hw/pci-host/apb.h
> +++ b/include/hw/pci-host/sabre.h
> @@ -27,7 +27,7 @@ typedef struct SabreState {
>
> hwaddr special_base;
> hwaddr mem_base;
> - MemoryRegion apb_config;
> + MemoryRegion sabre_config;
> MemoryRegion pci_config;
> MemoryRegion pci_mmio;
> MemoryRegion pci_ioport;
for the part not related to APB_DPRINTF/SABRE_DPRINTF:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
you can also use my R-b for this patch if you don't want to move
APB_DPRINTF/SABRE_DPRINTF to patch #10 and keep this series done .
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host
2018-01-14 10:47 ` [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host Mark Cave-Ayland
@ 2018-01-14 13:32 ` Philippe Mathieu-Daudé
2018-01-14 16:27 ` Marcel Apfelbaum
2018-01-16 4:48 ` Michael S. Tsirkin
1 sibling, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:32 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu
Cc: qemu-devel, Marcel Apfelbaum, Michael S . Tsirkin
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Not sure this is worth a separate commit (I'd squash it in the next
patch), still:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> CC: Michael S. Tsirkin <mst@redhat.com>
> CC: Marcel Apfelbaum <marcel@redhat.com>
> ---
> Makefile.objs | 1 +
> hw/pci-host/trace-events | 1 +
> 2 files changed, 2 insertions(+)
> create mode 100644 hw/pci-host/trace-events
>
> diff --git a/Makefile.objs b/Makefile.objs
> index c8b1bba593..6aa793ce4f 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -149,6 +149,7 @@ trace-events-subdirs += hw/i386/xen
> trace-events-subdirs += hw/9pfs
> trace-events-subdirs += hw/ppc
> trace-events-subdirs += hw/pci
> +trace-events-subdirs += hw/pci-host
> trace-events-subdirs += hw/s390x
> trace-events-subdirs += hw/vfio
> trace-events-subdirs += hw/acpi
> diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
> new file mode 100644
> index 0000000000..9284b1fbad
> --- /dev/null
> +++ b/hw/pci-host/trace-events
> @@ -0,0 +1 @@
> +# See docs/devel/tracing.txt for syntax documentation.
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 10/11] sabre: convert from SABRE_DPRINTF macro to trace-events
2018-01-14 10:47 ` [Qemu-devel] [PATCH 10/11] sabre: convert from SABRE_DPRINTF macro to trace-events Mark Cave-Ayland
@ 2018-01-14 13:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:36 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu; +Cc: qemu-devel
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/pci-host/sabre.c | 32 ++++++++++----------------------
> hw/pci-host/trace-events | 10 ++++++++++
> 2 files changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
> index 4054c17598..2268a41dd9 100644
> --- a/hw/pci-host/sabre.c
> +++ b/hw/pci-host/sabre.c
> @@ -36,16 +36,7 @@
> #include "exec/address-spaces.h"
> #include "qapi/error.h"
> #include "qemu/log.h"
> -
> -/* debug sabre */
> -//#define DEBUG_SABRE
> -
> -#ifdef DEBUG_SABRE
> -#define SABRE_DPRINTF(fmt, ...) \
> -do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
> -#else
> -#define SABRE_DPRINTF(fmt, ...)
> -#endif
> +#include "trace.h"
>
> /*
> * Chipset docs:
> @@ -69,8 +60,7 @@ do { printf("sabre: " fmt , ## __VA_ARGS__); } while (0)
>
> static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
> {
> - SABRE_DPRINTF("%s: request irq %d\n", __func__, irq_num);
> -
> + trace_sabre_set_request(irq_num);
> s->irq_request = irq_num;
> qemu_set_irq(s->ivec_irqs[irq_num], 1);
> }
> @@ -108,7 +98,7 @@ static inline void sabre_check_irqs(SabreState *s)
>
> static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
> {
> - SABRE_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
> + trace_sabre_clear_request(irq_num);
> qemu_set_irq(s->ivec_irqs[irq_num], 0);
> s->irq_request = NO_IRQ_REQUEST;
> }
> @@ -125,8 +115,7 @@ static void sabre_config_write(void *opaque, hwaddr addr,
> {
> SabreState *s = opaque;
>
> - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
> - addr, val);
> + trace_sabre_config_write(addr, val);
>
> switch (addr & 0xffff) {
> case 0x30 ... 0x4f: /* DMA error registers */
> @@ -250,7 +239,7 @@ static uint64_t sabre_config_read(void *opaque,
> val = 0;
> break;
> }
> - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
> + trace_sabre_config_read(addr, val);
>
> return val;
> }
> @@ -267,8 +256,7 @@ static void sabre_pci_config_write(void *opaque, hwaddr addr,
> SabreState *s = opaque;
> PCIHostState *phb = PCI_HOST_BRIDGE(s);
>
> - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,
> - addr, val);
> + trace_sabre_pci_config_write(addr, val);
> pci_data_write(phb->bus, addr, val, size);
> }
>
> @@ -280,7 +268,7 @@ static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
> PCIHostState *phb = PCI_HOST_BRIDGE(s);
>
> ret = pci_data_read(phb->bus, addr, size);
> - SABRE_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
> + trace_sabre_pci_config_read(addr, ret);
> return ret;
> }
>
> @@ -318,7 +306,8 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
> {
> SabreState *s = opaque;
>
> - SABRE_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
> + trace_sabre_pci_set_irq(irq_num, level);
> +
> /* PCI IRQ map onto the first 32 INO. */
> if (irq_num < 32) {
> if (level) {
> @@ -332,8 +321,7 @@ static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
> } else {
> /* OBIO IRQ map onto the next 32 INO. */
> if (level) {
> - SABRE_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num,
> - level);
> + trace_sabre_pci_set_obio_irq(irq_num, level);
> s->pci_irq_in |= 1ULL << irq_num;
> if ((s->irq_request == NO_IRQ_REQUEST)
> && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
> diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
> index 9284b1fbad..32dfc84692 100644
> --- a/hw/pci-host/trace-events
> +++ b/hw/pci-host/trace-events
> @@ -1 +1,11 @@
> # See docs/devel/tracing.txt for syntax documentation.
> +
> +# hw/pci-host/sabre.c
> +sabre_set_request(int irq_num) "request irq %d"
unsigned int irq_num, %u?
or maybe simpler to change sabre_clear_request() to take an int.
> +sabre_clear_request(int irq_num) "clear request irq %d"
ditto.
> +sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
> +sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
> +sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
> +sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64
Cool, you cared about replacing TARGET_FMT_plx by PRIx64 :)
> +sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d"
> +sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d"
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 11/11] sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events
2018-01-14 10:47 ` [Qemu-devel] [PATCH 11/11] sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events Mark Cave-Ayland
@ 2018-01-14 13:41 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-01-14 13:41 UTC (permalink / raw)
To: Mark Cave-Ayland, atar4qemu; +Cc: qemu-devel
On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/sparc64/sparc64.c | 85 ++++++++++++++++++++-----------------------------
> hw/sparc64/trace-events | 18 +++++++++++
> 2 files changed, 52 insertions(+), 51 deletions(-)
>
> diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
> index 95a06f00b2..408388945e 100644
> --- a/hw/sparc64/sparc64.c
> +++ b/hw/sparc64/sparc64.c
> @@ -28,25 +28,9 @@
> #include "hw/char/serial.h"
> #include "hw/sparc/sparc64.h"
> #include "qemu/timer.h"
> +#include "trace.h"
>
>
> -//#define DEBUG_IRQ
> -//#define DEBUG_TIMER
> -
> -#ifdef DEBUG_IRQ
> -#define CPUIRQ_DPRINTF(fmt, ...) \
> - do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
> -#else
> -#define CPUIRQ_DPRINTF(fmt, ...)
> -#endif
> -
> -#ifdef DEBUG_TIMER
> -#define TIMER_DPRINTF(fmt, ...) \
> - do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
> -#else
> -#define TIMER_DPRINTF(fmt, ...)
> -#endif
> -
> #define TICK_MAX 0x7fffffffffffffffULL
>
> void cpu_check_irqs(CPUSPARCState *env)
> @@ -73,8 +57,7 @@ void cpu_check_irqs(CPUSPARCState *env)
> is (2 << psrpil). */
> if (pil < (2 << env->psrpil)) {
> if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> - CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
> - env->interrupt_index);
> + trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
> env->interrupt_index = 0;
> cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
> }
> @@ -92,22 +75,21 @@ void cpu_check_irqs(CPUSPARCState *env)
>
> if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
> && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
> - CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
> - "current %x >= pending %x\n",
> - env->tl, cpu_tsptr(env)->tt, new_interrupt);
> + trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
> + cpu_tsptr(env)->tt,
> + new_interrupt);
80 cols limit striking again...
> } else if (old_interrupt != new_interrupt) {
> env->interrupt_index = new_interrupt;
> - CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
> - old_interrupt, new_interrupt);
> + trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
> + new_interrupt);
> cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> }
> break;
> }
> }
> } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> - CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
> - "current interrupt %x\n",
> - pil, env->pil_in, env->softint, env->interrupt_index);
> + trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
> + env->interrupt_index);
> env->interrupt_index = 0;
> cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
> }
> @@ -131,7 +113,7 @@ void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level)
>
> if (level) {
> if (!(env->ivec_status & 0x20)) {
> - CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
> + trace_sparc64_cpu_ivec_raise_irq(irq);
> cs = CPU(cpu);
> cs->halted = 0;
> env->interrupt_index = TT_IVEC;
> @@ -143,7 +125,7 @@ void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level)
> }
> } else {
> if (env->ivec_status & 0x20) {
> - CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
> + trace_sparc64_cpu_ivec_lower_irq(irq);
> cs = CPU(cpu);
> env->ivec_status &= ~0x20;
> cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
> @@ -216,10 +198,10 @@ static void tick_irq(void *opaque)
> CPUTimer *timer = env->tick;
>
> if (timer->disabled) {
> - CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
> + trace_sparc64_cpu_tick_irq_disabled();
> return;
> } else {
> - CPUIRQ_DPRINTF("tick: fire\n");
> + trace_sparc64_cpu_tick_irq_fire();
> }
>
> env->softint |= SOFTINT_TIMER;
> @@ -234,10 +216,10 @@ static void stick_irq(void *opaque)
> CPUTimer *timer = env->stick;
>
> if (timer->disabled) {
> - CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
> + trace_sparc64_cpu_stick_irq_disabled();
> return;
> } else {
> - CPUIRQ_DPRINTF("stick: fire\n");
> + trace_sparc64_cpu_stick_irq_fire();
> }
>
> env->softint |= SOFTINT_STIMER;
> @@ -252,10 +234,10 @@ static void hstick_irq(void *opaque)
> CPUTimer *timer = env->hstick;
>
> if (timer->disabled) {
> - CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
> + trace_sparc64_cpu_hstick_irq_disabled();
> return;
> } else {
> - CPUIRQ_DPRINTF("hstick: fire\n");
> + trace_sparc64_cpu_hstick_irq_fire();
> }
>
> env->softint |= SOFTINT_STIMER;
> @@ -280,9 +262,9 @@ void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
> int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
> cpu_to_timer_ticks(real_count, timer->frequency);
>
> - TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
> - timer->name, real_count,
> - timer->npt ? "disabled" : "enabled", timer);
> + trace_sparc64_cpu_tick_set_count(timer->name, real_count,
> + timer->npt ? "disabled" : "enabled",
> + timer);
>
> timer->npt = npt_bit ? 1 : 0;
> timer->clock_offset = vm_clock_offset;
> @@ -294,9 +276,9 @@ uint64_t cpu_tick_get_count(CPUTimer *timer)
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
> timer->frequency);
>
> - TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
> - timer->name, real_count,
> - timer->npt ? "disabled" : "enabled", timer);
> + trace_sparc64_cpu_tick_get_count(timer->name, real_count,
> + timer->npt ? "disabled" : "enabled",
> + timer);
>
> if (timer->npt) {
> real_count |= timer->npt_mask;
> @@ -319,18 +301,19 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
> expires = now + 1;
> }
>
> - TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
> - "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
> - timer->name, real_limit,
> - timer->disabled ? "disabled" : "enabled",
> - timer, limit,
> - timer_to_cpu_ticks(now - timer->clock_offset,
> - timer->frequency),
> - timer_to_cpu_ticks(expires - now, timer->frequency));
> + trace_sparc64_cpu_tick_set_limit(timer->name, real_limit,
> + timer->disabled ? "disabled" : "enabled",
> + timer, limit,
> + timer_to_cpu_ticks(
> + now - timer->clock_offset,
> + timer->frequency
> + ),
funny, I'd personally keep this on the previous line (matter of taste).
> + timer_to_cpu_ticks(
> + expires - now, timer->frequency
> + ));
ditto.
>
> if (!real_limit) {
> - TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
> - timer->name);
> + trace_sparc64_cpu_tick_set_limit_zero(timer->name);
> timer_del(timer->qtimer);
> } else if (timer->disabled) {
> timer_del(timer->qtimer);
> diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events
> index 2ee2d75f70..cf0888581d 100644
> --- a/hw/sparc64/trace-events
> +++ b/hw/sparc64/trace-events
> @@ -7,3 +7,21 @@ ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d level %d"
> sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d"
> sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d"
> sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64
> +
> +# hw/sparc64/sparc64.c
> +sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
> +sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
> +sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
> +sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
> +sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d"
> +sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d"
> +sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled"
> +sparc64_cpu_tick_irq_fire(void) "tick_irq: fire"
> +sparc64_cpu_stick_irq_disabled(void) "stick_irq: softint disabled"
> +sparc64_cpu_stick_irq_fire(void) "stick_irq: fire"
> +sparc64_cpu_hstick_irq_disabled(void) "hstick_irq: softint disabled"
> +sparc64_cpu_hstick_irq_fire(void) "hstick_irq: fire"
> +sparc64_cpu_tick_set_count(const char *name, uint64_t real_count, const char *npt, void *p) "%s set_count count=0x%016lx (npt %s) p=%p"
> +sparc64_cpu_tick_get_count(const char *name, uint64_t real_count, const char *npt, void *p) "%s get_count count=0x%016lx (npt %s) p=%p"
> +sparc64_cpu_tick_set_limit(const char *name, uint64_t real_limit, const char *dis, void *p, uint64_t limit, uint64_t t, uint64_t dt) "%s set_limit limit=0x%016lx (%s) p=%p called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)"
> +sparc64_cpu_tick_set_limit_zero(const char *name) "%s set_limit limit=ZERO - not starting timer"
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host
2018-01-14 13:32 ` Philippe Mathieu-Daudé
@ 2018-01-14 16:27 ` Marcel Apfelbaum
2018-01-15 18:29 ` Mark Cave-Ayland
0 siblings, 1 reply; 32+ messages in thread
From: Marcel Apfelbaum @ 2018-01-14 16:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Mark Cave-Ayland, atar4qemu
Cc: Marcel Apfelbaum, qemu-devel, Michael S . Tsirkin
On 14/01/2018 15:32, Philippe Mathieu-Daudé wrote:
> On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Not sure this is worth a separate commit (I'd squash it in the next
> patch), still:
I agree, no need to add a new directory to the trace list
while we don't have a trace events file.
Thanks,
Marcel
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> CC: Michael S. Tsirkin <mst@redhat.com>
>> CC: Marcel Apfelbaum <marcel@redhat.com>
>> ---
>> Makefile.objs | 1 +
>> hw/pci-host/trace-events | 1 +
>> 2 files changed, 2 insertions(+)
>> create mode 100644 hw/pci-host/trace-events
>>
>> diff --git a/Makefile.objs b/Makefile.objs
>> index c8b1bba593..6aa793ce4f 100644
>> --- a/Makefile.objs
>> +++ b/Makefile.objs
>> @@ -149,6 +149,7 @@ trace-events-subdirs += hw/i386/xen
>> trace-events-subdirs += hw/9pfs
>> trace-events-subdirs += hw/ppc
>> trace-events-subdirs += hw/pci
>> +trace-events-subdirs += hw/pci-host
>> trace-events-subdirs += hw/s390x
>> trace-events-subdirs += hw/vfio
>> trace-events-subdirs += hw/acpi
>> diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
>> new file mode 100644
>> index 0000000000..9284b1fbad
>> --- /dev/null
>> +++ b/hw/pci-host/trace-events
>> @@ -0,0 +1 @@
>> +# See docs/devel/tracing.txt for syntax documentation.
>>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 07/11] sun4u: rename apb variables and constants
2018-01-14 13:20 ` Philippe Mathieu-Daudé
@ 2018-01-15 18:26 ` Mark Cave-Ayland
0 siblings, 0 replies; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-15 18:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, atar4qemu; +Cc: qemu-devel
On 14/01/18 13:20, Philippe Mathieu-Daudé wrote:
> Hi Mark,
>
> On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
>> In order to reflect the previous change of TYPE_APB to TYPE_SABRE, update
>> the corresponding variable names to keep the terminology consistent.
>>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> ---
>> hw/sparc64/sun4u.c | 41 +++++++++++++++++++++--------------------
>> 1 file changed, 21 insertions(+), 20 deletions(-)
>>
>> diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
>> index b8f685847a..fb18afaaa6 100644
>> --- a/hw/sparc64/sun4u.c
>> +++ b/hw/sparc64/sun4u.c
>> @@ -55,9 +55,9 @@
>> #define CMDLINE_ADDR 0x003ff000
>> #define PROM_SIZE_MAX (4 * 1024 * 1024)
>> #define PROM_VADDR 0x000ffd00000ULL
>> -#define APB_SPECIAL_BASE 0x1fe00000000ULL
>> -#define APB_MEM_BASE 0x1ff00000000ULL
>> -#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
>> +#define PBM_SPECIAL_BASE 0x1fe00000000ULL
>> +#define PBM_MEM_BASE 0x1ff00000000ULL
>> +#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
>> #define PROM_FILENAME "openbios-sparc64"
>> #define NVRAM_SIZE 0x2000
>> #define MAX_IDE_BUS 2
>> @@ -465,7 +465,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>> Nvram *nvram;
>> unsigned int i;
>> uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
>> - SabreState *apb;
>> + SabreState *sabre;
>> PCIBus *pci_bus, *pci_busA, *pci_busB;
>> PCIDevice *ebus, *pci_dev;
>> SysBusDevice *s;
>> @@ -489,23 +489,24 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>> prom_init(hwdef->prom_addr, bios_name);
>>
>> /* Init sabre (PCI host bridge) */
>> - apb = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
>> - qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
>> - qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
>> - object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort);
>> - qdev_init_nofail(DEVICE(apb));
>> + sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
>> + qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
>> + qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
>> + object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
>> + &error_abort);
>> + qdev_init_nofail(DEVICE(sabre));
>>
>> /* Wire up PCI interrupts to CPU */
>> for (i = 0; i < IVEC_MAX; i++) {
>> - qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i,
>> + qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
>> qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
>> }
>>
>> - pci_bus = PCI_HOST_BRIDGE(apb)->bus;
>> - pci_busA = pci_bridge_get_sec_bus(apb->bridgeA);
>> - pci_busB = pci_bridge_get_sec_bus(apb->bridgeB);
>> + pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
>> + pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
>> + pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
>>
>> - /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
>> + /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
>
> This single change might go in patch #2 instead.
>
> Anyway:
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Hi Philippe,
I did think about that, but it feels a bit cleaner to keep all the sun4u
changes in one place (see the change to the constants and the other
comments within the file).
ATB,
Mark.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host
2018-01-14 16:27 ` Marcel Apfelbaum
@ 2018-01-15 18:29 ` Mark Cave-Ayland
0 siblings, 0 replies; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-15 18:29 UTC (permalink / raw)
To: marcel, Philippe Mathieu-Daudé, atar4qemu
Cc: qemu-devel, Michael S . Tsirkin
On 14/01/18 16:27, Marcel Apfelbaum wrote:
> On 14/01/2018 15:32, Philippe Mathieu-Daudé wrote:
>> On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
>>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Not sure this is worth a separate commit (I'd squash it in the next
>> patch), still:
>
> I agree, no need to add a new directory to the trace list
> while we don't have a trace events file.
Hi Marcel,
The basic skeleton of the file is there with the just the default
comments, but other than that it's empty. The only reason I placed it
into a separate patch was so it could get an Ack from someone on the PCI
side, but I'm happy to squash it based upon your comment above.
ATB,
Mark.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions
2018-01-14 13:25 ` Philippe Mathieu-Daudé
@ 2018-01-15 18:38 ` Mark Cave-Ayland
2018-01-20 20:24 ` Artyom Tarasenko
0 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2018-01-15 18:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: famz, atar4qemu
On 14/01/18 13:25, Philippe Mathieu-Daudé wrote:
> On 01/14/2018 08:21 AM, Mark Cave-Ayland wrote:
>> On 14/01/18 11:15, no-reply@patchew.org wrote:
>>> Hi,
>>>
>>> This series seems to have some coding style problems. See output below
>>> for
>>> more information:
>>>
>>> Type: series
>>> Message-id: 20180114104751.21965-1-mark.cave-ayland@ilande.co.uk
>>> Subject: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and
>>> tracepoint conversions
>>
>> (lots cut)
>>
>>> === OUTPUT BEGIN ===
>>> Checking PATCH 1/11: apb: split simba PCI bridge into
>>> hw/pci-bridge/simba.c...
>>> Checking PATCH 2/11: simba: rename PBMPCIBridge and QOM types to
>>> reflect simba naming...
>>> Checking PATCH 3/11: apb: rename APB functions to use sabre prefix...
>>> Checking PATCH 4/11: apb: change pbm_pci_host prefix functions to use
>>> sabre_pci prefix...
>>> Checking PATCH 5/11: apb: QOMify sabre PCI host bridge...
>>> Checking PATCH 6/11: apb: rename QOM type from TYPE_APB to TYPE_SABRE...
>>> Checking PATCH 7/11: sun4u: rename apb variables and constants...
>>> Checking PATCH 8/11: apb: rename apb.c to sabre.c...
>>> ERROR: do not use C99 // comments
>>> #86: FILE: hw/pci-host/sabre.c:41:
>>> +//#define DEBUG_SABRE
>>>
>>> total: 1 errors, 0 warnings, 188 lines checked
>>>
>>> Your patch has style problems, please review. If any of these errors
>>> are false positives report them to the maintainer, see
>>> CHECKPATCH in MAINTAINERS.
>>>
>>> Checking PATCH 9/11: pci: add trace-events support for hw/pci-host...
>>> Checking PATCH 10/11: sabre: convert from SABRE_DPRINTF macro to
>>> trace-events...
>>> Checking PATCH 11/11: sparc64: convert hw/sparc64/sparc64.c from
>>> DPRINTF macros to trace events...
>>> === OUTPUT END ===
>>>
>>> Test command exited with code: 1
>>
>> This is fine - it's just a side-effect of renaming DEBUG_APB to
>> DEBUG_SABRE as part of the APB to sabre rename, and in fact this code is
>> completely removed in patch 10 with the conversion to tracepoints.
>
> This can be avoided moving patch #8 after #10, although not worthy IMHO.
Thanks once again for the review. It was quite a tricky patchset to
order in the end because of the rename, and there wasn't really one
ordering which I found completely satisfactory.
Given that you're generally happy with the patches, I'm inclined to keep
the patchset in its current form, pending any further comments from Artyom.
ATB,
Mark.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host
2018-01-14 10:47 ` [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host Mark Cave-Ayland
2018-01-14 13:32 ` Philippe Mathieu-Daudé
@ 2018-01-16 4:48 ` Michael S. Tsirkin
1 sibling, 0 replies; 32+ messages in thread
From: Michael S. Tsirkin @ 2018-01-16 4:48 UTC (permalink / raw)
To: Mark Cave-Ayland; +Cc: qemu-devel, atar4qemu, Marcel Apfelbaum
On Sun, Jan 14, 2018 at 10:47:49AM +0000, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> CC: Michael S. Tsirkin <mst@redhat.com>
> CC: Marcel Apfelbaum <marcel@redhat.com>
Seems harmless so why not.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> Makefile.objs | 1 +
> hw/pci-host/trace-events | 1 +
> 2 files changed, 2 insertions(+)
> create mode 100644 hw/pci-host/trace-events
>
> diff --git a/Makefile.objs b/Makefile.objs
> index c8b1bba593..6aa793ce4f 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -149,6 +149,7 @@ trace-events-subdirs += hw/i386/xen
> trace-events-subdirs += hw/9pfs
> trace-events-subdirs += hw/ppc
> trace-events-subdirs += hw/pci
> +trace-events-subdirs += hw/pci-host
> trace-events-subdirs += hw/s390x
> trace-events-subdirs += hw/vfio
> trace-events-subdirs += hw/acpi
> diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
> new file mode 100644
> index 0000000000..9284b1fbad
> --- /dev/null
> +++ b/hw/pci-host/trace-events
> @@ -0,0 +1 @@
> +# See docs/devel/tracing.txt for syntax documentation.
> --
> 2.11.0
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions
2018-01-15 18:38 ` Mark Cave-Ayland
@ 2018-01-20 20:24 ` Artyom Tarasenko
0 siblings, 0 replies; 32+ messages in thread
From: Artyom Tarasenko @ 2018-01-20 20:24 UTC (permalink / raw)
To: Mark Cave-Ayland; +Cc: Philippe Mathieu-Daudé, qemu-devel, Fam Zheng
On Mon, Jan 15, 2018 at 7:38 PM, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
> On 14/01/18 13:25, Philippe Mathieu-Daudé wrote:
>
>> On 01/14/2018 08:21 AM, Mark Cave-Ayland wrote:
>>>
>>> On 14/01/18 11:15, no-reply@patchew.org wrote:
>>>>
>>>> Hi,
>>>>
>>>> This series seems to have some coding style problems. See output below
>>>> for
>>>> more information:
>>>>
>>>> Type: series
>>>> Message-id: 20180114104751.21965-1-mark.cave-ayland@ilande.co.uk
>>>> Subject: [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and
>>>> tracepoint conversions
>>>
>>>
>>> (lots cut)
>>>
>>>> === OUTPUT BEGIN ===
>>>> Checking PATCH 1/11: apb: split simba PCI bridge into
>>>> hw/pci-bridge/simba.c...
>>>> Checking PATCH 2/11: simba: rename PBMPCIBridge and QOM types to
>>>> reflect simba naming...
>>>> Checking PATCH 3/11: apb: rename APB functions to use sabre prefix...
>>>> Checking PATCH 4/11: apb: change pbm_pci_host prefix functions to use
>>>> sabre_pci prefix...
>>>> Checking PATCH 5/11: apb: QOMify sabre PCI host bridge...
>>>> Checking PATCH 6/11: apb: rename QOM type from TYPE_APB to TYPE_SABRE...
>>>> Checking PATCH 7/11: sun4u: rename apb variables and constants...
>>>> Checking PATCH 8/11: apb: rename apb.c to sabre.c...
>>>> ERROR: do not use C99 // comments
>>>> #86: FILE: hw/pci-host/sabre.c:41:
>>>> +//#define DEBUG_SABRE
>>>>
>>>> total: 1 errors, 0 warnings, 188 lines checked
>>>>
>>>> Your patch has style problems, please review. If any of these errors
>>>> are false positives report them to the maintainer, see
>>>> CHECKPATCH in MAINTAINERS.
>>>>
>>>> Checking PATCH 9/11: pci: add trace-events support for hw/pci-host...
>>>> Checking PATCH 10/11: sabre: convert from SABRE_DPRINTF macro to
>>>> trace-events...
>>>> Checking PATCH 11/11: sparc64: convert hw/sparc64/sparc64.c from
>>>> DPRINTF macros to trace events...
>>>> === OUTPUT END ===
>>>>
>>>> Test command exited with code: 1
>>>
>>>
>>> This is fine - it's just a side-effect of renaming DEBUG_APB to
>>> DEBUG_SABRE as part of the APB to sabre rename, and in fact this code is
>>> completely removed in patch 10 with the conversion to tracepoints.
>>
>>
>> This can be avoided moving patch #8 after #10, although not worthy IMHO.
>
>
> Thanks once again for the review. It was quite a tricky patchset to order in
> the end because of the rename, and there wasn't really one ordering which I
> found completely satisfactory.
>
> Given that you're generally happy with the patches, I'm inclined to keep the
> patchset in its current form, pending any further comments from Artyom.
>
The whole series does look good to me. The new naming conventions are
really a lot cleaner than what we used to have. Well done!
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
--
Regards,
Artyom Tarasenko
SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2018-01-20 20:24 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-01-14 10:47 [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions Mark Cave-Ayland
2018-01-14 10:47 ` [Qemu-devel] [PATCH 01/11] apb: split simba PCI bridge into hw/pci-bridge/simba.c Mark Cave-Ayland
2018-01-14 13:05 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 02/11] simba: rename PBMPCIBridge and QOM types to reflect simba naming Mark Cave-Ayland
2018-01-14 13:05 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 03/11] apb: rename APB functions to use sabre prefix Mark Cave-Ayland
2018-01-14 13:08 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 04/11] apb: change pbm_pci_host prefix functions to use sabre_pci prefix Mark Cave-Ayland
2018-01-14 13:09 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 05/11] apb: QOMify sabre PCI host bridge Mark Cave-Ayland
2018-01-14 13:13 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 06/11] apb: rename QOM type from TYPE_APB to TYPE_SABRE Mark Cave-Ayland
2018-01-14 13:15 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 07/11] sun4u: rename apb variables and constants Mark Cave-Ayland
2018-01-14 13:20 ` Philippe Mathieu-Daudé
2018-01-15 18:26 ` Mark Cave-Ayland
2018-01-14 10:47 ` [Qemu-devel] [PATCH 08/11] apb: rename apb.c to sabre.c Mark Cave-Ayland
2018-01-14 13:30 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 09/11] pci: add trace-events support for hw/pci-host Mark Cave-Ayland
2018-01-14 13:32 ` Philippe Mathieu-Daudé
2018-01-14 16:27 ` Marcel Apfelbaum
2018-01-15 18:29 ` Mark Cave-Ayland
2018-01-16 4:48 ` Michael S. Tsirkin
2018-01-14 10:47 ` [Qemu-devel] [PATCH 10/11] sabre: convert from SABRE_DPRINTF macro to trace-events Mark Cave-Ayland
2018-01-14 13:36 ` Philippe Mathieu-Daudé
2018-01-14 10:47 ` [Qemu-devel] [PATCH 11/11] sparc64: convert hw/sparc64/sparc64.c from DPRINTF macros to trace events Mark Cave-Ayland
2018-01-14 13:41 ` Philippe Mathieu-Daudé
2018-01-14 11:15 ` [Qemu-devel] [PATCH 00/11] sun4u: APB tidy-up/rename and tracepoint conversions no-reply
2018-01-14 11:21 ` Mark Cave-Ayland
2018-01-14 13:25 ` Philippe Mathieu-Daudé
2018-01-15 18:38 ` Mark Cave-Ayland
2018-01-20 20:24 ` Artyom Tarasenko
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