From: Eduardo Habkost <ehabkost@redhat.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Kang, Luwei" <luwei.kang@intel.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"rth@twiddle.net" <rth@twiddle.net>,
"mtosatti@redhat.com" <mtosatti@redhat.com>,
Chao Peng <chao.p.peng@linux.intel.com>,
"libvir-list@redhat.com" <libvir-list@redhat.com>
Subject: Re: [Qemu-devel] [PATCH RESEND v1 1/2] i386: Add Intel Processor Trace feature support
Date: Thu, 18 Jan 2018 12:37:45 -0200 [thread overview]
Message-ID: <20180118143744.GY627@localhost.localdomain> (raw)
In-Reply-To: <c67f0021-0ca0-413b-bb84-3ff54dd791de@redhat.com>
On Thu, Jan 18, 2018 at 02:39:57PM +0100, Paolo Bonzini wrote:
> On 18/01/2018 14:24, Eduardo Habkost wrote:
> > However, if there's a simple way to make it possible to migrate
> > between hosts with different CPUID[14h] data, it would be even
> > better. With the current KVM intel-pt implementation, what
> > happens if the CPUID[14h] data seen by the guest doesn't match
> > exactly the CPUID[14h] leaves from the host?
>
> Some bits in there can be treated as CPU features (e.g. EBX bit 0 "CR3
> filtering support"). Probably we should handle these in KVM right now.
> KVM needs to compute a mask of valid 1 bits for IA32_RTIT_CTL based on
> CPUID, and apply it when the MSR is written.
Does this mean QEMU can't set CPUID values that won't match the
host with the existing implementation, or this won't matter for
well-behaved guests that don't try to set reserved bits on the
MSRs?
> It also needs to whitelist
> bits like we do for other feature words. These include:
>
> - CPUID[EAX=14h,ECX=0].EBX
>
> - CPUID[EAX=14h,ECX=0].ECX except bit 31
>
> - CPUID[EAX=14h,ECX=1].EAX bits 16:31 (if CPUID[EAX=14h,ECX=0].EBX[3]=1)
>
> - CPUID[EAX=14h,ECX=1].EBX (if CPUID[EAX=14h,ECX=0].EBX[1]=1)
What do you mean by whitelist?
>
> Others, currently only CPUID[EAX=14h,ECX=0].ECX[31] must match, there is
> no way to emulate the "wrong" value.
In this case we could make it configurable but require the host
and guest value to always match.
This might be an obstacle to enabling intel-pt by default
(because it could make VMs not migratable to newer hosts), but
may allow the feature to be configured in a predictable
way.
>
> Others, currently only CPUID[EAX=14h,ECX=1].EAX[2:0] are numeric values,
> and it's possible to emulate a lower value than the one in the processor.
This could be handled by QEMU. There's no requirement that all
GET_SUPPORTED_CPUID values should be validated by simple bit
masking.
>
> CPUID[EAX=14h,ECX=0].EAX is the maximum subleaf. It should be (barring
> guest bugs) okay to always present leaf 1.
>
> Paolo
--
Eduardo
next prev parent reply other threads:[~2018-01-18 14:37 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-08 20:36 [Qemu-devel] [PATCH RESEND v1 1/2] i386: Add Intel Processor Trace feature support Luwei Kang
2018-01-08 20:36 ` [Qemu-devel] [PATCH RESEND v1 2/2] i386: Add support to get/set/migrate Intel Processor Trace feature Luwei Kang
2018-01-12 14:22 ` [Qemu-devel] [PATCH RESEND v1 1/2] i386: Add Intel Processor Trace feature support Eduardo Habkost
2018-01-15 7:19 ` Kang, Luwei
2018-01-15 9:33 ` Paolo Bonzini
2018-01-15 14:04 ` Eduardo Habkost
2018-01-15 14:25 ` Jiri Denemark
2018-01-15 14:31 ` Eduardo Habkost
2018-01-16 6:10 ` Kang, Luwei
2018-01-16 11:51 ` Eduardo Habkost
2018-01-17 10:32 ` Kang, Luwei
2018-01-18 2:42 ` Eduardo Habkost
2018-01-18 5:33 ` Kang, Luwei
2018-01-18 13:24 ` Eduardo Habkost
2018-01-18 13:39 ` Paolo Bonzini
2018-01-18 14:37 ` Eduardo Habkost [this message]
2018-01-18 14:44 ` Paolo Bonzini
2018-01-18 16:52 ` Eduardo Habkost
2018-01-18 16:53 ` Paolo Bonzini
2018-01-22 10:36 ` Kang, Luwei
2018-01-26 9:19 ` Paolo Bonzini
2018-01-22 10:45 ` Kang, Luwei
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