From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecEsL-0003k9-Ig for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:25:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecEsI-00079K-Cc for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:25:21 -0500 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:44253) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecEsI-000795-75 for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:25:18 -0500 Received: by mail-qt0-x244.google.com with SMTP id m59so32585682qte.11 for ; Thu, 18 Jan 2018 10:25:18 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 18 Jan 2018 15:24:52 -0300 Message-Id: <20180118182510.15630-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v8 00/17] SDHCI: clean v1/v2 Specs (part 2) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Alistair Francis , Peter Maydell , Stefan Hajnoczi Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Kevin O'Connor , "Edgar E . Iglesias" , Andrey Smirnov , Marcel Apfelbaum , Krzysztof Kozlowski Since v7: - use error_propagate() Since v6: - rebased on upstream to use DEFINE_SDHCI_COMMON_PROPERTIES - included qtests back - add PCI qtests - series was getting big, splitting again; next one is "implement Spec v3" - following Alistair advice, new properties default to current SDHC_CAPAB_REG_DEFAULT (probably 'default' for historical reason, being the first capabilities set). This leads to weird properties imho, i.e. defaulting 'max-frequency' to 52 MHz, the Exynos SoC has to set this property to 0. - addressed Alistair reviews - confirmed the Exynos4210 specs after chatting on IRC with Krzysztof Kozlowski who kindly verified in the datasheet. Since v5: - addressed Alistair reviews - dropped "abstract generic-sdhci" - dropped Linux Device Tree names - split qtests in another series - change the bcm2835 minimum blocksize to 1KB (Andrew Baumann) - added Alistair R-b - based on Alistair work: - add SD tunning sequence via Host Control 2 to use UHS-I cards - add CMD/DAT[] fields in the Present State (used in next series to switch card voltage) based on Alistair work: - add SD tunning sequence via Host Control 2 to use UHS-I cards - add CMD/DAT[] fields in the Present State (used in next series to switch card voltage) Since v4 ("SDHCI: add qtests and fix few issues"): - spec_version default to v2 (current behaviour) - addressed Alistair review (no v1, tell user about valid version) Since v3: - no change, but split back in 2 series, 1st part is "SDHCI: housekeeping v5", Since v2: - more detailed 'capabilities', all boards converted to use these properties - since all qtests pass, removed the previous 'capareg' property - added Stefan/Alistair R-b - corrected 'access' LED behavior (Alistair's review) - more uses of the registerfields API - remove some dead code - cosmetix: - added more comments - renamed a pair of registers - reordered few struct members Since v1: - addressed Alistair Francis review comments, added some R-b - only move register defines to "sd-internal.h" - fixed deposit64() arguments - dropped unuseful s->fifo_buffer = NULL - use a qemu_irq for the LED, restrict the logging to ON/OFF - fixed a trace format string error - included Andrey Smirnov ACMD12ERRSTS write patch - dropped few unuseful patches, and separate the Python polemical ones for later >>From the "SDHCI housekeeping" series: - 1: we restrict part of "sd/sd.h" into local "sd-internal.h", - 2,3: we somehow beautiful the code, no logical changes, - 4-7: we refactor the common sysbus/pci qdev code, - 8-10: we add plenty of trace events which will result useful later, - 11: we finally expose a "dma-memory" property. >>From the "SDHCI: add a qtest and fix few issues" series: - 12,13: fix registers - 14,15: boards can specify which SDHCI Spec to use (v2 and v3 so far) - 15-20: HCI qtest Regards, Phil. $ git backport-diff with v7 001/17:[down] 'use error_propagate(local_err) in realize()' 002/17:[----] [--] 'sdhci: add qtest to check the SD capabilities register' 003/17:[----] [--] 'sdhci: add check_capab_readonly() qtest' 004/17:[----] [--] 'sdhci: add a check_capab_baseclock() qtest' 005/17:[----] [--] 'sdhci: add a check_capab_sdma() qtest' 006/17:[----] [--] 'sdhci: add qtest to check the SD Spec version' 007/17:[0007] [FC] 'sdhci: add init_readonly_registers() to initialize the CAPAB register' 008/17:[----] [--] 'sdhci: add a 'spec_version property' (default to v2)' 009/17:[0006] [FC] 'sdhci: add basic Spec v1 capabilities' ... no change ... $ git backport-diff with v6 001/16:[down] 'sdhci: add qtest to check the SD capabilities register' 002/16:[0008] [FC] 'sdhci: add check_capab_readonly() qtest' 003/16:[0001] [FC] 'sdhci: add a check_capab_baseclock() qtest' 004/16:[----] [-C] 'sdhci: add a check_capab_sdma() qtest' 005/16:[0078] [FC] 'sdhci: add qtest to check the SD Spec version' 006/16:[down] 'sdhci: add init_readonly_registers() to initialize the CAPAB register' 007/16:[0010] [FC] 'sdhci: add a 'spec_version property' (default to v2)' 008/16:[0049] [FC] 'sdhci: add basic Spec v1 capabilities' 009/16:[0007] [FC] 'sdhci: add max-block-length capability (Spec v1)' 010/16:[0013] [FC] 'sdhci: add clock capabilities (Spec v1)' 011/16:[----] [--] 'sdhci: add BLOCK_SIZE_MASK for DMA' 012/16:[----] [-C] 'sdhci: Fix 64-bit ADMA2' 013/16:[0036] [FC] 'sdhci: add DMA and 64-bit capabilities (Spec v2)' 014/16:[0010] [FC] 'hw/arm/xilinx_zynq: implement SDHCI Spec v2' 015/16:[0014] [FC] 'hw/arm/exynos4210: implement SDHCI Spec v2' 016/16:[down] 'sdhci: throw an error if capabilities are incorrectly configured' Philippe Mathieu-Daudé (16): sdhci: use error_propagate(local_err) in realize() sdhci: add qtest to check the SD capabilities register sdhci: add check_capab_readonly() qtest sdhci: add a check_capab_baseclock() qtest sdhci: add a check_capab_sdma() qtest sdhci: add qtest to check the SD Spec version sdhci: add init_readonly_registers() to initialize the CAPAB register sdhci: add a 'spec_version property' (default to v2) sdhci: add basic Spec v1 capabilities sdhci: add max-block-length capability (Spec v1) sdhci: add clock capabilities (Spec v1) sdhci: add BLOCK_SIZE_MASK for DMA sdhci: add DMA and 64-bit capabilities (Spec v2) hw/arm/xilinx_zynq: implement SDHCI Spec v2 hw/arm/exynos4210: implement SDHCI Spec v2 sdhci: throw an error if capabilities are incorrectly configured Sai Pavan Boddu (1): sdhci: Fix 64-bit ADMA2 include/hw/sd/sdhci.h | 26 ++++++ hw/sd/sdhci-internal.h | 43 +++++++--- hw/arm/exynos4210.c | 21 ++++- hw/arm/xilinx_zynq.c | 70 ++++++++++------ hw/sd/sdhci.c | 223 ++++++++++++++++++++++++++++++++----------------- tests/sdhci-test.c | 215 +++++++++++++++++++++++++++++++++++++++++++++++ tests/Makefile.include | 3 + 7 files changed, 488 insertions(+), 113 deletions(-) create mode 100644 tests/sdhci-test.c -- 2.15.1