From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Paolo Bonzini <pbonzini@redhat.com>,
Alistair Francis <alistair.francis@xilinx.com>,
Peter Maydell <peter.maydell@linaro.org>,
Stefan Hajnoczi <stefanha@redhat.com>
Cc: Sai Pavan Boddu <saipava@xilinx.com>,
qemu-devel@nongnu.org, Kevin O'Connor <kevin@koconnor.net>,
"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
Andrey Smirnov <andrew.smirnov@gmail.com>,
Marcel Apfelbaum <marcel@redhat.com>
Subject: [Qemu-devel] [PATCH v8 13/17] sdhci: Fix 64-bit ADMA2
Date: Thu, 18 Jan 2018 15:31:04 -0300 [thread overview]
Message-ID: <20180118183108.16009-13-f4bug@amsat.org> (raw)
In-Reply-To: <20180118183108.16009-1-f4bug@amsat.org>
In-Reply-To: <20180118182510.15630-1-f4bug@amsat.org>
From: Sai Pavan Boddu <saipava@xilinx.com>
The 64-bit ADMA address is not converted to the cpu endianes correctly.
This patch fixes the issue and uses a valid mask for the attribute data.
Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
[AF: Re-write commit message]
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/sd/sdhci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 7390b8464b..6277f067da 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -632,8 +632,8 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
dscr->length = le16_to_cpu(dscr->length);
dma_memory_read(s->dma_as, entry_addr + 4,
(uint8_t *)(&dscr->addr), 8);
- dscr->attr = le64_to_cpu(dscr->attr);
- dscr->attr &= 0xfffffff8;
+ dscr->addr = le64_to_cpu(dscr->addr);
+ dscr->attr &= (uint8_t) ~0xC0;
dscr->incr = 12;
break;
}
--
2.15.1
next prev parent reply other threads:[~2018-01-18 18:32 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-18 18:24 [Qemu-devel] [PATCH v8 00/17] SDHCI: clean v1/v2 Specs (part 2) Philippe Mathieu-Daudé
2018-01-18 18:30 ` [Qemu-devel] [PATCH v8 01/17] sdhci: use error_propagate(local_err) in realize() Philippe Mathieu-Daudé
2018-01-19 17:59 ` Alistair Francis
2018-01-18 18:30 ` [Qemu-devel] [PATCH v8 02/17] sdhci: add qtest to check the SD capabilities register Philippe Mathieu-Daudé
2018-01-18 18:30 ` [Qemu-devel] [PATCH v8 03/17] sdhci: add check_capab_readonly() qtest Philippe Mathieu-Daudé
2018-01-18 18:30 ` [Qemu-devel] [PATCH v8 04/17] sdhci: add a check_capab_baseclock() qtest Philippe Mathieu-Daudé
2018-01-18 18:30 ` [Qemu-devel] [PATCH v8 05/17] sdhci: add a check_capab_sdma() qtest Philippe Mathieu-Daudé
2018-01-18 18:30 ` [Qemu-devel] [PATCH v8 06/17] sdhci: add qtest to check the SD Spec version Philippe Mathieu-Daudé
2018-01-18 18:30 ` [Qemu-devel] [PATCH v8 07/17] sdhci: add init_readonly_registers() to initialize the CAPAB register Philippe Mathieu-Daudé
2018-01-19 18:01 ` Alistair Francis
2018-01-18 18:30 ` [Qemu-devel] [PATCH v8 08/17] sdhci: add a 'spec_version property' (default to v2) Philippe Mathieu-Daudé
2018-01-18 18:31 ` [Qemu-devel] [PATCH v8 09/17] sdhci: add basic Spec v1 capabilities Philippe Mathieu-Daudé
2018-01-19 18:19 ` Alistair Francis
2018-01-18 18:31 ` [Qemu-devel] [PATCH v8 10/17] sdhci: add max-block-length capability (Spec v1) Philippe Mathieu-Daudé
2018-01-18 18:31 ` Philippe Mathieu-Daudé [this message]
2018-01-18 18:31 ` [Qemu-devel] [PATCH v8 15/17] hw/arm/xilinx_zynq: implement SDHCI Spec v2 Philippe Mathieu-Daudé
2018-01-18 18:31 ` [Qemu-devel] [PATCH v8 16/17] hw/arm/exynos4210: " Philippe Mathieu-Daudé
2018-01-21 16:49 ` Krzysztof Kozlowski
2018-01-18 18:31 ` [Qemu-devel] [PATCH v8 17/17] sdhci: throw an error if capabilities are incorrectly configured Philippe Mathieu-Daudé
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