From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecEys-00072Y-Q5 for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:32:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecEyr-0003Lt-TQ for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:32:06 -0500 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:46977) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecEyr-0003Ln-PU for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:32:05 -0500 Received: by mail-qt0-x241.google.com with SMTP id o35so22514461qtj.13 for ; Thu, 18 Jan 2018 10:32:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 18 Jan 2018 15:30:57 -0300 Message-Id: <20180118183108.16009-6-f4bug@amsat.org> In-Reply-To: <20180118183108.16009-1-f4bug@amsat.org> References: <20180118183108.16009-1-f4bug@amsat.org> In-Reply-To: <20180118182510.15630-1-f4bug@amsat.org> References: <20180118182510.15630-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v8 06/17] sdhci: add qtest to check the SD Spec version List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Alistair Francis , Peter Maydell , Stefan Hajnoczi Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Kevin O'Connor , "Edgar E . Iglesias" , Andrey Smirnov , Marcel Apfelbaum Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi --- tests/sdhci-test.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index 3f6377474c..37ada0e1c5 100644 --- a/tests/sdhci-test.c +++ b/tests/sdhci-test.c @@ -49,6 +49,21 @@ static struct { QPCIBar mem_bar; } g = { }; +static uint32_t sdhci_readl(uintptr_t base, uint32_t reg_addr) +{ + if (g.dev) { + uint32_t value; + + qpci_memread(g.dev, g.mem_bar, reg_addr, &value, sizeof(value)); + + return value; + } else { + QTestState *qtest = global_qtest; + + return qtest_readl(qtest, base + reg_addr); + } +} + static uint64_t sdhci_readq(uintptr_t base, uint32_t reg_addr) { if (g.dev) { @@ -75,6 +90,16 @@ static void sdhci_writeq(uintptr_t base, uint32_t reg_addr, uint64_t value) } } +static void check_specs_version(uintptr_t addr, uint8_t version) +{ + uint32_t v; + + v = sdhci_readl(addr, SDHC_HCVER); + v &= 0xff; + v += 1; + g_assert_cmpuint(v, ==, version); +} + static void check_capab_capareg(uintptr_t addr, uint64_t expected_capab) { uint64_t capab; @@ -157,6 +182,7 @@ static void test_machine(const void *data) machine_start(test); + check_specs_version(test->sdhci.addr, test->sdhci.version); check_capab_capareg(test->sdhci.addr, test->sdhci.capab.reg); check_capab_readonly(test->sdhci.addr); check_capab_sdma(test->sdhci.addr, test->sdhci.capab.sdma); -- 2.15.1