From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44575) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecFGb-0005zf-0X for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:50:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecFGW-0007xm-42 for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:50:25 -0500 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:33263) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecFGV-0007xA-U7 for qemu-devel@nongnu.org; Thu, 18 Jan 2018 13:50:20 -0500 Received: by mail-qt0-x243.google.com with SMTP id e2so32780462qti.0 for ; Thu, 18 Jan 2018 10:50:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 18 Jan 2018 15:50:11 -0300 Message-Id: <20180118185011.19315-1-f4bug@amsat.org> In-Reply-To: <20180118183108.16009-14-f4bug@amsat.org> References: <20180118183108.16009-14-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v8 18/17] !fixup sdhci: add DMA and 64-bit capabilities (Spec v2) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Alistair Francis , Peter Maydell , Stefan Hajnoczi Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Kevin O'Connor , "Edgar E . Iglesias" , Andrey Smirnov , Marcel Apfelbaum Signed-off-by: Philippe Mathieu-Daudé --- missed from patch 14/17 while rebasing :| hw/sd/sdhci.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d0d64f0c52..51368e028e 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -41,24 +41,6 @@ #define TYPE_SDHCI_BUS "sdhci-bus" #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) -/* Default SD/MMC host controller features information, which will be - * presented in CAPABILITIES register of generic SD host controller at reset. - * If not stated otherwise: - * 0 - not supported, 1 - supported, other - prohibited. - */ -#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ -#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ -#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ - -/* Now check all parameters and calculate CAPABILITIES REGISTER value */ -#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 -#error Capabilities features can have value 0 or 1 only! -#endif - -#define SDHC_CAPAB_REG_DEFAULT \ - ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_ADMA1 << 20) | \ - (SDHC_CAPAB_ADMA2 << 19)) - #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) static void sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, -- 2.15.1