From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54144) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecSHN-0001GM-4m for qemu-devel@nongnu.org; Fri, 19 Jan 2018 03:44:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecSHI-0005Ms-8r for qemu-devel@nongnu.org; Fri, 19 Jan 2018 03:44:05 -0500 Received: from mail.ispras.ru ([83.149.199.45]:53668) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecSHI-0005Mg-1f for qemu-devel@nongnu.org; Fri, 19 Jan 2018 03:44:00 -0500 From: Pavel Dovgalyuk Date: Fri, 19 Jan 2018 11:43:59 +0300 Message-ID: <20180119084359.7100.2236.stgit@pasha-VirtualBox> In-Reply-To: <20180119084235.7100.98318.stgit@pasha-VirtualBox> References: <20180119084235.7100.98318.stgit@pasha-VirtualBox> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC PATCH v4 11/23] target/arm/arm-powertctl: drop BQL assertions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kwolf@redhat.com, peter.maydell@linaro.org, boost.lists@gmail.com, quintela@redhat.com, jasowang@redhat.com, mst@redhat.com, zuban32s@gmail.com, maria.klimushenkova@ispras.ru, dovgaluk@ispras.ru, kraxel@redhat.com, pavel.dovgaluk@ispras.ru, pbonzini@redhat.com, alex.bennee@linaro.org From: Alex Benn=C3=A9e The powerctl code is run in the context of the vCPU changing power state. It does not need the BQL to protect its changes. Signed-off-by: Alex Benn=C3=A9e --- target/arm/arm-powerctl.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 25207cb..9661a59 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -124,7 +124,6 @@ static void arm_set_cpu_on_async_work(CPUState *targe= t_cpu_state, g_free(info); =20 /* Finally set the power status */ - assert(qemu_mutex_iothread_locked()); target_cpu->power_state =3D PSCI_ON; } =20 @@ -135,8 +134,6 @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, ui= nt64_t context_id, ARMCPU *target_cpu; struct CpuOnInfo *info; =20 - assert(qemu_mutex_iothread_locked()); - DPRINTF("cpu %" PRId64 " (EL %d, %s) @ 0x%" PRIx64 " with R0 =3D 0x%= " PRIx64 "\n", cpuid, target_el, target_aa64 ? "aarch64" : "aarch32",= entry, context_id); @@ -227,7 +224,6 @@ static void arm_set_cpu_off_async_work(CPUState *targ= et_cpu_state, { ARMCPU *target_cpu =3D ARM_CPU(target_cpu_state); =20 - assert(qemu_mutex_iothread_locked()); target_cpu->power_state =3D PSCI_OFF; target_cpu_state->halted =3D 1; target_cpu_state->exception_index =3D EXCP_HLT; @@ -238,8 +234,6 @@ int arm_set_cpu_off(uint64_t cpuid) CPUState *target_cpu_state; ARMCPU *target_cpu; =20 - assert(qemu_mutex_iothread_locked()); - DPRINTF("cpu %" PRId64 "\n", cpuid); =20 /* change to the cpu we are powering up */ @@ -274,8 +268,6 @@ int arm_reset_cpu(uint64_t cpuid) CPUState *target_cpu_state; ARMCPU *target_cpu; =20 - assert(qemu_mutex_iothread_locked()); - DPRINTF("cpu %" PRId64 "\n", cpuid); =20 /* change to the cpu we are resetting */