From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, rth@twiddle.net,
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [Qemu-devel] [PATCH] target/arm: Fix 32-bit address truncation
Date: Fri, 19 Jan 2018 19:46:48 +0000 [thread overview]
Message-ID: <20180119194648.25501-1-ard.biesheuvel@linaro.org> (raw)
Commit ("3b39d734141a target/arm: Handle page table walk load failures
correctly") modified both versions of the page table walking code (i.e.,
arm_ldl_ptw and arm_ldq_ptw) to record the result of the translation in
a temporary 'data' variable so that it can be inspected before being
returned. However, arm_ldq_ptw() returns an uint64_t, and using a
temporary uint32_t variable truncates the upper bits, corrupting the
result. This causes problems when using more than 4 GB of memory in
a TCG guest. So use a uint64_t instead.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 67059033019c..a41b6c3a1b82 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8368,7 +8368,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
MemTxAttrs attrs = {};
MemTxResult result = MEMTX_OK;
AddressSpace *as;
- uint32_t data;
+ uint64_t data;
attrs.secure = is_secure;
as = arm_addressspace(cs, attrs);
--
2.11.0
next reply other threads:[~2018-01-19 19:47 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-19 19:46 Ard Biesheuvel [this message]
2018-01-22 11:12 ` [Qemu-devel] [PATCH] target/arm: Fix 32-bit address truncation Peter Maydell
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