From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v3 11/45] target/hppa: Implement rfi
Date: Wed, 24 Jan 2018 15:25:51 -0800 [thread overview]
Message-ID: <20180124232625.30105-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 1 +
target/hppa/helper.h | 2 ++
target/hppa/op_helper.c | 24 ++++++++++++++++++++++++
target/hppa/translate.c | 30 ++++++++++++++++++++++++++++--
4 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index c92c564a7f..6ec3430ae3 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -178,6 +178,7 @@ struct CPUHPPAState {
target_ureg cr[32]; /* control registers */
target_ureg cr_back[2]; /* back of cr17/cr18 */
+ target_ureg shadow[7]; /* shadow registers */
/* Those resources are used only in QEMU core */
CPU_COMMON
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 254a4da133..79d22ae486 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -78,5 +78,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
#ifndef CONFIG_USER_ONLY
+DEF_HELPER_1(rfi, void, env)
+DEF_HELPER_1(rfi_r, void, env)
DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr)
#endif
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 1c3e043cc0..3f5dcbbca0 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -614,4 +614,28 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM);
return psw & PSW_SM;
}
+
+void HELPER(rfi)(CPUHPPAState *env)
+{
+ /* ??? On second reading this condition simply seems
+ to be undefined rather than a diagnosed trap. */
+ if (env->psw & (PSW_I | PSW_R | PSW_Q)) {
+ helper_excp(env, EXCP_ILL);
+ }
+ env->iaoq_f = env->cr[CR_IIAOQ];
+ env->iaoq_b = env->cr_back[1];
+ cpu_hppa_put_psw(env, env->cr[CR_IPSW]);
+}
+
+void HELPER(rfi_r)(CPUHPPAState *env)
+{
+ env->gr[1] = env->shadow[0];
+ env->gr[8] = env->shadow[1];
+ env->gr[9] = env->shadow[2];
+ env->gr[16] = env->shadow[3];
+ env->gr[17] = env->shadow[4];
+ env->gr[24] = env->shadow[5];
+ env->gr[25] = env->shadow[6];
+ helper_rfi(env);
+}
#endif
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 8ca58f3df3..df0bb04907 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -655,6 +655,10 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status)
{
TCGLabel *null_lab = ctx->null_lab;
+ /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
+ For UPDATED, we cannot update on the nullified path. */
+ assert(status != DISAS_IAQ_N_UPDATED);
+
if (likely(null_lab == NULL)) {
/* The current insn wasn't conditional or handled the condition
applied to it without a branch, so the (new) setting of
@@ -676,8 +680,6 @@ static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status)
gen_set_label(null_lab);
ctx->null_cond = cond_make_n();
}
-
- assert(status != DISAS_NORETURN && status != DISAS_IAQ_N_UPDATED);
if (status == DISAS_NORETURN) {
status = DISAS_NEXT;
}
@@ -2153,6 +2155,29 @@ static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn,
/* Exit the TB to recognize new interrupts. */
return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT);
}
+
+static DisasJumpType trans_rfi(DisasContext *ctx, uint32_t insn,
+ const DisasInsn *di)
+{
+ unsigned comp = extract32(insn, 5, 4);
+
+ CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
+ nullify_over(ctx);
+
+ if (comp == 5) {
+ gen_helper_rfi_r(cpu_env);
+ } else {
+ gen_helper_rfi(cpu_env);
+ }
+ if (ctx->base.singlestep_enabled) {
+ gen_excp_1(EXCP_DEBUG);
+ } else {
+ tcg_gen_exit_tb(0);
+ }
+
+ /* Exit the TB to recognize new interrupts. */
+ return nullify_end(ctx, DISAS_NORETURN);
+}
#endif /* !CONFIG_USER_ONLY */
static const DisasInsn table_system[] = {
@@ -2169,6 +2194,7 @@ static const DisasInsn table_system[] = {
{ 0x00000e60u, 0xfc00ffe0u, trans_rsm },
{ 0x00000d60u, 0xfc00ffe0u, trans_ssm },
{ 0x00001860u, 0xffe0ffffu, trans_mtsm },
+ { 0x00000c00u, 0xfffffe1fu, trans_rfi },
#endif
};
--
2.14.3
next prev parent reply other threads:[~2018-01-24 23:26 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-24 23:25 [Qemu-devel] [PATCH v3 00/45] hppa-softmmu Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 01/45] target/hppa: Skeleton support for hppa-softmmu Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 02/45] target/hppa: Define the rest of the PSW Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 03/45] target/hppa: Disable gateway page emulation for system mode Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 04/45] target/hppa: Define hardware exception types Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 05/45] target/hppa: Split address size from register size Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 06/45] target/hppa: Implement mmu_idx from IA privilege level Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 07/45] target/hppa: Implement the system mask instructions Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 08/45] target/hppa: Add space registers Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 09/45] target/hppa: Add control registers Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 10/45] target/hppa: Adjust insn mask for mfctl, w Richard Henderson
2018-01-24 23:25 ` Richard Henderson [this message]
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 12/45] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 13/45] target/hppa: Implement unaligned access trap Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 14/45] target/hppa: Use space registers in data operations Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 15/45] target/hppa: Avoid privilege level decrease during branches Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 16/45] target/hppa: Implement IASQ Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 17/45] target/hppa: Implement tlb_fill Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 18/45] target/hppa: Implement external interrupts Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 19/45] target/hppa: Implement the interval timer Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 20/45] target/hppa: Log unimplemented instructions Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 21/45] target/hppa: Implement I*TLBA and I*TLBP insns Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 22/45] target/hppa: Implement P*TLB and P*TLBE insns Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 23/45] target/hppa: Implement LDWA Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 24/45] target/hppa: Implement LPA Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 25/45] target/hppa: Implement LCI Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 26/45] target/hppa: Implement SYNCDMA insn Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 27/45] target/hppa: Implement halt and reset instructions Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 28/45] target/hppa: Optimize for flat addressing space Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 29/45] target/hppa: Add system registers to gdbstub Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 30/45] target/hppa: Add migration for the cpu Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 31/45] target/hppa: Implement B,GATE insn Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 32/45] target/hppa: Only use EXCP_DTLB_MISS Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 33/45] qom: Add MMU_DEBUG_LOAD Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 34/45] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 35/45] target/hppa: Increase number of temp regs Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 36/45] target/hppa: Fix comment Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 37/45] target/hppa: Implement LDSID for system mode Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 38/45] target/hppa: Implement a pause instruction Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 39/45] target/hppa: Implement STWA Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 40/45] target/hppa: Enable MTTCG Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 41/45] hw/hppa: Implement DINO system board Richard Henderson
2018-01-25 11:22 ` Philippe Mathieu-Daudé
2018-01-27 13:22 ` Helge Deller
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 42/45] pc-bios: Add hppa-firmware.img and git submodule Richard Henderson
2018-02-04 22:40 ` Philippe Mathieu-Daudé
2018-02-06 7:35 ` Helge Deller
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 43/45] hw/hppa: Add MAINTAINERS entry Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 44/45] target/hppa: Fix 32-bit operand masks for 0E FCVT Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 45/45] target/hppa: Implement PROBE for system mode Richard Henderson
2018-01-25 0:11 ` [Qemu-devel] [PATCH v3 00/45] hppa-softmmu no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180124232625.30105-12-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).