* [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9
2018-01-31 8:27 [Qemu-devel] [PATCH 0/3] target/ppc: add hash MMU support for the POWER9 PowerNV machine Cédric Le Goater
@ 2018-01-31 8:27 ` Cédric Le Goater
2018-02-02 2:34 ` Suraj Jitindar Singh
2018-01-31 8:27 ` [Qemu-devel] [PATCH 2/3] target/ppc: add hash MMU support on POWER9 for PowerNV only Cédric Le Goater
2018-01-31 8:27 ` [Qemu-devel] [PATCH 3/3] target/ppc: generalize check on radix when in HV mode Cédric Le Goater
2 siblings, 1 reply; 10+ messages in thread
From: Cédric Le Goater @ 2018-01-31 8:27 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson
Cc: Suraj Jitindar Singh, Cédric Le Goater
The Partition Table Control Register (PTCR) is a hypervisor privileged
SPR. It contains the host real address of the Partition Table and its
size.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 1 +
target/ppc/misc_helper.c | 12 ++++++++++++
target/ppc/mmu-hash64.h | 6 ++++++
target/ppc/mmu_helper.c | 28 ++++++++++++++++++++++++++++
target/ppc/translate.c | 3 +++
target/ppc/translate_init.c | 18 ++++++++++++++++++
7 files changed, 70 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9f8cbbe7aa4d..53061229a0a8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1314,6 +1314,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
#if !defined(CONFIG_USER_ONLY)
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
+void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
#endif /* !defined(CONFIG_USER_ONLY) */
void ppc_store_msr (CPUPPCState *env, target_ulong value);
@@ -1605,6 +1606,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_GIVOR13 (0x1BC)
#define SPR_BOOKE_GIVOR14 (0x1BD)
#define SPR_TIR (0x1BE)
+#define SPR_PTCR (0x1D0)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5b739179b8b5..19453c68138a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
+DEF_HELPER_2(store_ptcr, void, env, tl)
#endif
DEF_HELPER_2(store_sdr1, void, env, tl)
DEF_HELPER_2(store_pidr, void, env, tl)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 0e4217821b8e..8c8cba5cc6f1 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
}
}
+#if defined(TARGET_PPC64)
+void helper_store_ptcr(CPUPPCState *env, target_ulong val)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ if (env->spr[SPR_PTCR] != val) {
+ ppc_store_ptcr(env, val);
+ tlb_flush(CPU(cpu));
+ }
+}
+#endif /* defined(TARGET_PPC64) */
+
void helper_store_pidr(CPUPPCState *env, target_ulong val)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index d297b97d3773..4fb00ac17abb 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -98,6 +98,12 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
+/*
+ * Partition table definitions
+ */
+#define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
+#define PTCR_PTAS 0x000000000000001FULL /* Partition Table Size */
+
static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
{
return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 16ef5acaa28f..b1e660a4d16a 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2029,6 +2029,34 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
env->spr[SPR_SDR1] = value;
}
+#if defined(TARGET_PPC64)
+void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
+
+ assert(!cpu->vhyp);
+
+ if (env->mmu_model & POWERPC_MMU_V3) {
+ target_ulong ptcr_mask = PTCR_PTAB | PTCR_PTAS;
+ target_ulong ptas = value & PTCR_PTAS;
+
+ if (value & ~ptcr_mask) {
+ error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
+ value & ~ptcr_mask);
+ value &= ptcr_mask;
+ }
+ if (ptas > 28) {
+ error_report("Invalid PTAS 0x" TARGET_FMT_lx" stored in PTCR",
+ ptas);
+ return;
+ }
+ }
+ env->spr[SPR_PTCR] = value;
+}
+
+#endif /* defined(TARGET_PPC64) */
+
/* Segment registers load and store */
target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
{
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4132f67bb1f7..c2e6e3072799 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7130,6 +7130,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
}
+ if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
+ cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
+ }
cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
env->spr[SPR_DAR], env->spr[SPR_DSISR]);
break;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 55c99c97e377..a6eaa74244ca 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -417,6 +417,11 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
tcg_temp_free(t0);
}
+static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
+}
+
#endif
#endif
@@ -8164,6 +8169,18 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
#endif
}
+/* Page Table */
+static void gen_spr_power9_ptcr(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_PTCR, "PTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_ptcr,
+ 0x00000000);
+#endif
+}
+
static void init_proc_book3s_common(CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -8756,6 +8773,7 @@ static void init_proc_POWER9(CPUPPCState *env)
gen_spr_power8_ic(env);
gen_spr_power8_book4(env);
gen_spr_power8_rpr(env);
+ gen_spr_power9_ptcr(env);
/* POWER9 Specific registers */
spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
--
2.13.6
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9
2018-01-31 8:27 ` [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9 Cédric Le Goater
@ 2018-02-02 2:34 ` Suraj Jitindar Singh
2018-02-02 2:41 ` Suraj Jitindar Singh
2018-02-02 14:43 ` Cédric Le Goater
0 siblings, 2 replies; 10+ messages in thread
From: Suraj Jitindar Singh @ 2018-02-02 2:34 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc, qemu-devel, David Gibson
On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote:
> The Partition Table Control Register (PTCR) is a hypervisor
> privileged
> SPR. It contains the host real address of the Partition Table and its
> size.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/cpu.h | 2 ++
> target/ppc/helper.h | 1 +
> target/ppc/misc_helper.c | 12 ++++++++++++
> target/ppc/mmu-hash64.h | 6 ++++++
> target/ppc/mmu_helper.c | 28 ++++++++++++++++++++++++++++
> target/ppc/translate.c | 3 +++
> target/ppc/translate_init.c | 18 ++++++++++++++++++
> 7 files changed, 70 insertions(+)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 9f8cbbe7aa4d..53061229a0a8 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1314,6 +1314,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu,
> vaddr address, int size, int rw,
>
> #if !defined(CONFIG_USER_ONLY)
> void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
> #endif /* !defined(CONFIG_USER_ONLY) */
> void ppc_store_msr (CPUPPCState *env, target_ulong value);
>
> @@ -1605,6 +1606,7 @@ void ppc_compat_add_property(Object *obj, const
> char *name,
> #define SPR_BOOKE_GIVOR13 (0x1BC)
> #define SPR_BOOKE_GIVOR14 (0x1BD)
> #define SPR_TIR (0x1BE)
> +#define SPR_PTCR (0x1D0)
> #define SPR_BOOKE_SPEFSCR (0x200)
> #define SPR_Exxx_BBEAR (0x201)
> #define SPR_Exxx_BBTAR (0x202)
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 5b739179b8b5..19453c68138a 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu,
> TCG_CALL_NO_RWG, tl, env)
> #if !defined(CONFIG_USER_ONLY)
> #if defined(TARGET_PPC64)
> DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
> +DEF_HELPER_2(store_ptcr, void, env, tl)
> #endif
> DEF_HELPER_2(store_sdr1, void, env, tl)
> DEF_HELPER_2(store_pidr, void, env, tl)
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index 0e4217821b8e..8c8cba5cc6f1 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env,
> target_ulong val)
> }
> }
>
> +#if defined(TARGET_PPC64)
> +void helper_store_ptcr(CPUPPCState *env, target_ulong val)
> +{
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> + if (env->spr[SPR_PTCR] != val) {
> + ppc_store_ptcr(env, val);
> + tlb_flush(CPU(cpu));
> + }
> +}
> +#endif /* defined(TARGET_PPC64) */
> +
> void helper_store_pidr(CPUPPCState *env, target_ulong val)
> {
> PowerPCCPU *cpu = ppc_env_get_cpu(env);
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index d297b97d3773..4fb00ac17abb 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -98,6 +98,12 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
> #define HPTE64_V_1TB_SEG 0x4000000000000000ULL
> #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
>
> +/*
> + * Partition table definitions
> + */
> +#define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition
> Table Base */
> +#define PTCR_PTAS 0x000000000000001FULL /* Partition
> Table Size */
> +
s/PTCR_PTAB/PTCR_PATB
s/PTCR_PTAS/PTCR_PATS
To match the ISA?
> static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
> {
> return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 16ef5acaa28f..b1e660a4d16a 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -2029,6 +2029,34 @@ void ppc_store_sdr1(CPUPPCState *env,
> target_ulong value)
> env->spr[SPR_SDR1] = value;
> }
>
> +#if defined(TARGET_PPC64)
> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
> +{
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__,
> value);
> +
> + assert(!cpu->vhyp);
> +
> + if (env->mmu_model & POWERPC_MMU_V3) {
> + target_ulong ptcr_mask = PTCR_PTAB | PTCR_PTAS;
> + target_ulong ptas = value & PTCR_PTAS;
> +
> + if (value & ~ptcr_mask) {
> + error_report("Invalid bits 0x"TARGET_FMT_lx" set in
> PTCR",
> + value & ~ptcr_mask);
> + value &= ptcr_mask;
> + }
> + if (ptas > 28) {
> + error_report("Invalid PTAS 0x" TARGET_FMT_lx" stored in
> PTCR",
> + ptas);
> + return;
> + }
> + }
Should we throw some error if the ptcr is being accessed on a non-
power9 machine?
> + env->spr[SPR_PTCR] = value;
> +}
> +
> +#endif /* defined(TARGET_PPC64) */
> +
> /* Segment registers load and store */
> target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
> {
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 4132f67bb1f7..c2e6e3072799 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7130,6 +7130,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
> fprintf_function cpu_fprintf,
> if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
> cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env-
> >spr[SPR_SDR1]);
> }
> + if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
> + cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env-
> >spr[SPR_PTCR]);
> + }
> cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR "
> TARGET_FMT_lx "\n",
> env->spr[SPR_DAR], env->spr[SPR_DSISR]);
> break;
> diff --git a/target/ppc/translate_init.c
> b/target/ppc/translate_init.c
> index 55c99c97e377..a6eaa74244ca 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -417,6 +417,11 @@ static void spr_write_hior(DisasContext *ctx,
> int sprn, int gprn)
> tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> tcg_temp_free(t0);
> }
> +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> #endif
> #endif
>
> @@ -8164,6 +8169,18 @@ static void gen_spr_power8_rpr(CPUPPCState
> *env)
> #endif
> }
>
> +/* Page Table */
> +static void gen_spr_power9_ptcr(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register_hv(env, SPR_PTCR, "PTCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_ptcr,
> + 0x00000000);
> +#endif
> +}
> +
> static void init_proc_book3s_common(CPUPPCState *env)
> {
> gen_spr_ne_601(env);
> @@ -8756,6 +8773,7 @@ static void init_proc_POWER9(CPUPPCState *env)
> gen_spr_power8_ic(env);
> gen_spr_power8_book4(env);
> gen_spr_power8_rpr(env);
> + gen_spr_power9_ptcr(env);
>
> /* POWER9 Specific registers */
> spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9
2018-02-02 2:34 ` Suraj Jitindar Singh
@ 2018-02-02 2:41 ` Suraj Jitindar Singh
2018-02-02 14:44 ` Cédric Le Goater
2018-02-02 14:43 ` Cédric Le Goater
1 sibling, 1 reply; 10+ messages in thread
From: Suraj Jitindar Singh @ 2018-02-02 2:41 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc, qemu-devel, David Gibson
On Fri, 2018-02-02 at 13:34 +1100, Suraj Jitindar Singh wrote:
> On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote:
> > The Partition Table Control Register (PTCR) is a hypervisor
> > privileged
> > SPR. It contains the host real address of the Partition Table and
> > its
> > size.
> >
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
> > target/ppc/cpu.h | 2 ++
> > target/ppc/helper.h | 1 +
> > target/ppc/misc_helper.c | 12 ++++++++++++
> > target/ppc/mmu-hash64.h | 6 ++++++
> > target/ppc/mmu_helper.c | 28 ++++++++++++++++++++++++++++
> > target/ppc/translate.c | 3 +++
> > target/ppc/translate_init.c | 18 ++++++++++++++++++
> > 7 files changed, 70 insertions(+)
> >
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index 9f8cbbe7aa4d..53061229a0a8 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -1314,6 +1314,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu,
> > vaddr address, int size, int rw,
> >
> > #if !defined(CONFIG_USER_ONLY)
> > void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
> > +void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
> > #endif /* !defined(CONFIG_USER_ONLY) */
> > void ppc_store_msr (CPUPPCState *env, target_ulong value);
> >
> > @@ -1605,6 +1606,7 @@ void ppc_compat_add_property(Object *obj,
> > const
> > char *name,
> > #define SPR_BOOKE_GIVOR13 (0x1BC)
> > #define SPR_BOOKE_GIVOR14 (0x1BD)
> > #define SPR_TIR (0x1BE)
> > +#define SPR_PTCR (0x1D0)
> > #define SPR_BOOKE_SPEFSCR (0x200)
> > #define SPR_Exxx_BBEAR (0x201)
> > #define SPR_Exxx_BBTAR (0x202)
> > diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> > index 5b739179b8b5..19453c68138a 100644
> > --- a/target/ppc/helper.h
> > +++ b/target/ppc/helper.h
> > @@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu,
> > TCG_CALL_NO_RWG, tl, env)
> > #if !defined(CONFIG_USER_ONLY)
> > #if defined(TARGET_PPC64)
> > DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
> > +DEF_HELPER_2(store_ptcr, void, env, tl)
> > #endif
> > DEF_HELPER_2(store_sdr1, void, env, tl)
> > DEF_HELPER_2(store_pidr, void, env, tl)
> > diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> > index 0e4217821b8e..8c8cba5cc6f1 100644
> > --- a/target/ppc/misc_helper.c
> > +++ b/target/ppc/misc_helper.c
> > @@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env,
> > target_ulong val)
> > }
> > }
> >
> > +#if defined(TARGET_PPC64)
> > +void helper_store_ptcr(CPUPPCState *env, target_ulong val)
> > +{
> > + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> > +
> > + if (env->spr[SPR_PTCR] != val) {
> > + ppc_store_ptcr(env, val);
> > + tlb_flush(CPU(cpu));
> > + }
> > +}
> > +#endif /* defined(TARGET_PPC64) */
> > +
> > void helper_store_pidr(CPUPPCState *env, target_ulong val)
> > {
> > PowerPCCPU *cpu = ppc_env_get_cpu(env);
> > diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> > index d297b97d3773..4fb00ac17abb 100644
> > --- a/target/ppc/mmu-hash64.h
> > +++ b/target/ppc/mmu-hash64.h
> > @@ -98,6 +98,12 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
> > #define HPTE64_V_1TB_SEG 0x4000000000000000ULL
> > #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
> >
> > +/*
> > + * Partition table definitions
> > + */
> > +#define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition
> > Table Base */
> > +#define PTCR_PTAS 0x000000000000001FULL /* Partition
> > Table Size */
> > +
>
> s/PTCR_PTAB/PTCR_PATB
> s/PTCR_PTAS/PTCR_PATS
> To match the ISA?
Also these should be in target/ppc/mmu-book3s-v3.h, they're not hash
specific
>
> > static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
> > {
> > return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
> > diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> > index 16ef5acaa28f..b1e660a4d16a 100644
> > --- a/target/ppc/mmu_helper.c
> > +++ b/target/ppc/mmu_helper.c
> > @@ -2029,6 +2029,34 @@ void ppc_store_sdr1(CPUPPCState *env,
> > target_ulong value)
> > env->spr[SPR_SDR1] = value;
> > }
> >
> > +#if defined(TARGET_PPC64)
> > +void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
> > +{
> > + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> > + qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n",
> > __func__,
> > value);
> > +
> > + assert(!cpu->vhyp);
> > +
> > + if (env->mmu_model & POWERPC_MMU_V3) {
> > + target_ulong ptcr_mask = PTCR_PTAB | PTCR_PTAS;
> > + target_ulong ptas = value & PTCR_PTAS;
> > +
> > + if (value & ~ptcr_mask) {
> > + error_report("Invalid bits 0x"TARGET_FMT_lx" set in
> > PTCR",
> > + value & ~ptcr_mask);
> > + value &= ptcr_mask;
> > + }
> > + if (ptas > 28) {
> > + error_report("Invalid PTAS 0x" TARGET_FMT_lx" stored
> > in
> > PTCR",
> > + ptas);
> > + return;
> > + }
> > + }
>
> Should we throw some error if the ptcr is being accessed on a non-
> power9 machine?
>
> > + env->spr[SPR_PTCR] = value;
> > +}
> > +
> > +#endif /* defined(TARGET_PPC64) */
> > +
> > /* Segment registers load and store */
> > target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
> > {
> > diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> > index 4132f67bb1f7..c2e6e3072799 100644
> > --- a/target/ppc/translate.c
> > +++ b/target/ppc/translate.c
> > @@ -7130,6 +7130,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE
> > *f,
> > fprintf_function cpu_fprintf,
> > if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
> > cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env-
> > > spr[SPR_SDR1]);
> >
> > }
> > + if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
> > + cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env-
> > > spr[SPR_PTCR]);
> >
> > + }
> > cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR "
> > TARGET_FMT_lx "\n",
> > env->spr[SPR_DAR], env->spr[SPR_DSISR]);
> > break;
> > diff --git a/target/ppc/translate_init.c
> > b/target/ppc/translate_init.c
> > index 55c99c97e377..a6eaa74244ca 100644
> > --- a/target/ppc/translate_init.c
> > +++ b/target/ppc/translate_init.c
> > @@ -417,6 +417,11 @@ static void spr_write_hior(DisasContext *ctx,
> > int sprn, int gprn)
> > tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState,
> > excp_prefix));
> > tcg_temp_free(t0);
> > }
> > +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> > +{
> > + gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
> > +}
> > +
> > #endif
> > #endif
> >
> > @@ -8164,6 +8169,18 @@ static void gen_spr_power8_rpr(CPUPPCState
> > *env)
> > #endif
> > }
> >
> > +/* Page Table */
> > +static void gen_spr_power9_ptcr(CPUPPCState *env)
> > +{
> > +#if !defined(CONFIG_USER_ONLY)
> > + spr_register_hv(env, SPR_PTCR, "PTCR",
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + SPR_NOACCESS, SPR_NOACCESS,
> > + &spr_read_generic, &spr_write_ptcr,
> > + 0x00000000);
> > +#endif
> > +}
> > +
> > static void init_proc_book3s_common(CPUPPCState *env)
> > {
> > gen_spr_ne_601(env);
> > @@ -8756,6 +8773,7 @@ static void init_proc_POWER9(CPUPPCState
> > *env)
> > gen_spr_power8_ic(env);
> > gen_spr_power8_book4(env);
> > gen_spr_power8_rpr(env);
> > + gen_spr_power9_ptcr(env);
> >
> > /* POWER9 Specific registers */
> > spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9
2018-02-02 2:41 ` Suraj Jitindar Singh
@ 2018-02-02 14:44 ` Cédric Le Goater
0 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2018-02-02 14:44 UTC (permalink / raw)
To: Suraj Jitindar Singh, qemu-ppc, qemu-devel, David Gibson
On 02/02/2018 03:41 AM, Suraj Jitindar Singh wrote:
>>> +/*
>>> + * Partition table definitions
>>> + */
>>> +#define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition
>>> Table Base */
>>> +#define PTCR_PTAS 0x000000000000001FULL /* Partition
>>> Table Size */
>>> +
>> s/PTCR_PTAB/PTCR_PATB
>> s/PTCR_PTAS/PTCR_PATS
>> To match the ISA?
>
> Also these should be in target/ppc/mmu-book3s-v3.h, they're not hash
> specific
>
OK. I Will fix that.
Thanks,
C.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9
2018-02-02 2:34 ` Suraj Jitindar Singh
2018-02-02 2:41 ` Suraj Jitindar Singh
@ 2018-02-02 14:43 ` Cédric Le Goater
1 sibling, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2018-02-02 14:43 UTC (permalink / raw)
To: Suraj Jitindar Singh, qemu-ppc, qemu-devel, David Gibson
On 02/02/2018 03:34 AM, Suraj Jitindar Singh wrote:
> On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote:
>> The Partition Table Control Register (PTCR) is a hypervisor
>> privileged
>> SPR. It contains the host real address of the Partition Table and its
>> size.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> target/ppc/cpu.h | 2 ++
>> target/ppc/helper.h | 1 +
>> target/ppc/misc_helper.c | 12 ++++++++++++
>> target/ppc/mmu-hash64.h | 6 ++++++
>> target/ppc/mmu_helper.c | 28 ++++++++++++++++++++++++++++
>> target/ppc/translate.c | 3 +++
>> target/ppc/translate_init.c | 18 ++++++++++++++++++
>> 7 files changed, 70 insertions(+)
>>
>> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
>> index 9f8cbbe7aa4d..53061229a0a8 100644
>> --- a/target/ppc/cpu.h
>> +++ b/target/ppc/cpu.h
>> @@ -1314,6 +1314,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu,
>> vaddr address, int size, int rw,
>>
>> #if !defined(CONFIG_USER_ONLY)
>> void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
>> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
>> #endif /* !defined(CONFIG_USER_ONLY) */
>> void ppc_store_msr (CPUPPCState *env, target_ulong value);
>>
>> @@ -1605,6 +1606,7 @@ void ppc_compat_add_property(Object *obj, const
>> char *name,
>> #define SPR_BOOKE_GIVOR13 (0x1BC)
>> #define SPR_BOOKE_GIVOR14 (0x1BD)
>> #define SPR_TIR (0x1BE)
>> +#define SPR_PTCR (0x1D0)
>> #define SPR_BOOKE_SPEFSCR (0x200)
>> #define SPR_Exxx_BBEAR (0x201)
>> #define SPR_Exxx_BBTAR (0x202)
>> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
>> index 5b739179b8b5..19453c68138a 100644
>> --- a/target/ppc/helper.h
>> +++ b/target/ppc/helper.h
>> @@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu,
>> TCG_CALL_NO_RWG, tl, env)
>> #if !defined(CONFIG_USER_ONLY)
>> #if defined(TARGET_PPC64)
>> DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
>> +DEF_HELPER_2(store_ptcr, void, env, tl)
>> #endif
>> DEF_HELPER_2(store_sdr1, void, env, tl)
>> DEF_HELPER_2(store_pidr, void, env, tl)
>> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
>> index 0e4217821b8e..8c8cba5cc6f1 100644
>> --- a/target/ppc/misc_helper.c
>> +++ b/target/ppc/misc_helper.c
>> @@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env,
>> target_ulong val)
>> }
>> }
>>
>> +#if defined(TARGET_PPC64)
>> +void helper_store_ptcr(CPUPPCState *env, target_ulong val)
>> +{
>> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
>> +
>> + if (env->spr[SPR_PTCR] != val) {
>> + ppc_store_ptcr(env, val);
>> + tlb_flush(CPU(cpu));
>> + }
>> +}
>> +#endif /* defined(TARGET_PPC64) */
>> +
>> void helper_store_pidr(CPUPPCState *env, target_ulong val)
>> {
>> PowerPCCPU *cpu = ppc_env_get_cpu(env);
>> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
>> index d297b97d3773..4fb00ac17abb 100644
>> --- a/target/ppc/mmu-hash64.h
>> +++ b/target/ppc/mmu-hash64.h
>> @@ -98,6 +98,12 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
>> #define HPTE64_V_1TB_SEG 0x4000000000000000ULL
>> #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
>>
>> +/*
>> + * Partition table definitions
>> + */
>> +#define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition
>> Table Base */
>> +#define PTCR_PTAS 0x000000000000001FULL /* Partition
>> Table Size */
>> +
>
> s/PTCR_PTAB/PTCR_PATB
> s/PTCR_PTAS/PTCR_PATS
> To match the ISA?
yes. My bad.
>> static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
>> {
>> return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
>> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
>> index 16ef5acaa28f..b1e660a4d16a 100644
>> --- a/target/ppc/mmu_helper.c
>> +++ b/target/ppc/mmu_helper.c
>> @@ -2029,6 +2029,34 @@ void ppc_store_sdr1(CPUPPCState *env,
>> target_ulong value)
>> env->spr[SPR_SDR1] = value;
>> }
>>
>> +#if defined(TARGET_PPC64)
>> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
>> +{
>> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
>> + qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__,
>> value);
>> +
>> + assert(!cpu->vhyp);
>> +
>> + if (env->mmu_model & POWERPC_MMU_V3) {
>> + target_ulong ptcr_mask = PTCR_PTAB | PTCR_PTAS;
>> + target_ulong ptas = value & PTCR_PTAS;
>> +
>> + if (value & ~ptcr_mask) {
>> + error_report("Invalid bits 0x"TARGET_FMT_lx" set in
>> PTCR",
>> + value & ~ptcr_mask);
>> + value &= ptcr_mask;
>> + }
>> + if (ptas > 28) {
>> + error_report("Invalid PTAS 0x" TARGET_FMT_lx" stored in
>> PTCR",
>> + ptas);
>> + return;
>> + }
>> + }
>
> Should we throw some error if the ptcr is being accessed on a non-
> power9 machine?
The SPR is only added for POWER9 processor. We should be fine.
Thanks,
C.
>
>> + env->spr[SPR_PTCR] = value;
>> +}
>> +
>> +#endif /* defined(TARGET_PPC64) */
>> +
>> /* Segment registers load and store */
>> target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
>> {
>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
>> index 4132f67bb1f7..c2e6e3072799 100644
>> --- a/target/ppc/translate.c
>> +++ b/target/ppc/translate.c
>> @@ -7130,6 +7130,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
>> fprintf_function cpu_fprintf,
>> if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
>> cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env-
>>> spr[SPR_SDR1]);
>> }
>> + if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
>> + cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env-
>>> spr[SPR_PTCR]);
>> + }
>> cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR "
>> TARGET_FMT_lx "\n",
>> env->spr[SPR_DAR], env->spr[SPR_DSISR]);
>> break;
>> diff --git a/target/ppc/translate_init.c
>> b/target/ppc/translate_init.c
>> index 55c99c97e377..a6eaa74244ca 100644
>> --- a/target/ppc/translate_init.c
>> +++ b/target/ppc/translate_init.c
>> @@ -417,6 +417,11 @@ static void spr_write_hior(DisasContext *ctx,
>> int sprn, int gprn)
>> tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
>> tcg_temp_free(t0);
>> }
>> +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
>> +{
>> + gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
>> +}
>> +
>> #endif
>> #endif
>>
>> @@ -8164,6 +8169,18 @@ static void gen_spr_power8_rpr(CPUPPCState
>> *env)
>> #endif
>> }
>>
>> +/* Page Table */
>> +static void gen_spr_power9_ptcr(CPUPPCState *env)
>> +{
>> +#if !defined(CONFIG_USER_ONLY)
>> + spr_register_hv(env, SPR_PTCR, "PTCR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_ptcr,
>> + 0x00000000);
>> +#endif
>> +}
>> +
>> static void init_proc_book3s_common(CPUPPCState *env)
>> {
>> gen_spr_ne_601(env);
>> @@ -8756,6 +8773,7 @@ static void init_proc_POWER9(CPUPPCState *env)
>> gen_spr_power8_ic(env);
>> gen_spr_power8_book4(env);
>> gen_spr_power8_rpr(env);
>> + gen_spr_power9_ptcr(env);
>>
>> /* POWER9 Specific registers */
>> spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH 2/3] target/ppc: add hash MMU support on POWER9 for PowerNV only
2018-01-31 8:27 [Qemu-devel] [PATCH 0/3] target/ppc: add hash MMU support for the POWER9 PowerNV machine Cédric Le Goater
2018-01-31 8:27 ` [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9 Cédric Le Goater
@ 2018-01-31 8:27 ` Cédric Le Goater
2018-01-31 8:27 ` [Qemu-devel] [PATCH 3/3] target/ppc: generalize check on radix when in HV mode Cédric Le Goater
2 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2018-01-31 8:27 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson
Cc: Suraj Jitindar Singh, Cédric Le Goater
The HPTE bits definitions are slightly modified in ISA v3.0. Let's add
some helpers to hide the differences in the hash MMU code.
On a POWER9 processor, the Partition Table is composed of a pair of
doublewords per partition. The first doubleword indicates whether the
partition uses HPT or Radix Trees translation and contains the address
of the host's translation table structure and size.
The first doubleword of the PTCR holds the Hash Page Table base
address for the host when the hash MMU is in use. Also add an helper
to retrieve the HPT base address depending on the MMU revision.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_hcall.c | 5 +++--
target/ppc/mmu-hash64.c | 48 +++++++++++++++++++++++++++++++++++++++---------
target/ppc/mmu-hash64.h | 34 ++++++++++++++++++++++++++++++++--
3 files changed, 74 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 3fda7fd39da1..30cfc1f450cc 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -94,7 +94,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
return H_PARAMETER;
}
- raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
+ raddr = (ptel & ppc_hash64_hpte_r_rpn(cpu)) & ~((1ULL << apshift) - 1);
if (is_ram_address(spapr, raddr)) {
/* Regular RAM - should have WIMG=0010 */
@@ -586,7 +586,8 @@ static int rehash_hpte(PowerPCCPU *cpu,
base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
- avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
+ avpn = ppc_hash64_hpte_v_avpn_val(cpu, pte0) &
+ ~(((1ULL << base_pg_shift) - 1) >> 23);
if (pte0 & HPTE64_V_SECONDARY) {
pteg = ~pteg;
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 14d34e512f42..54f052ad717c 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -290,6 +290,22 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
return rt;
}
+hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ if (env->mmu_model & POWERPC_MMU_V3) {
+ if (msr_hv) {
+ return ldq_phys(CPU(cpu)->as, cpu->env.spr[SPR_PTCR] & PTCR_PTAB);
+ } else {
+ error_report("HPT Support Unimplemented");
+ exit(1);
+ }
+ } else {
+ return cpu->env.spr[SPR_SDR1];
+ }
+}
+
/* Check No-Execute or Guarded Storage */
static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
ppc_hash_pte64_t pte)
@@ -452,8 +468,9 @@ void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
false, n * HASH_PTE_SIZE_64);
}
-static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
- uint64_t pte0, uint64_t pte1)
+static unsigned hpte_page_shift(PowerPCCPU *cpu,
+ const struct ppc_one_seg_page_size *sps,
+ uint64_t pte0, uint64_t pte1)
{
int i;
@@ -479,7 +496,7 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
continue;
}
- mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
+ mask = ((1ULL << ps->page_shift) - 1) & ppc_hash64_hpte_r_rpn(cpu);
if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
return ps->page_shift;
@@ -489,6 +506,18 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
return 0; /* Bad page size encoding */
}
+static bool ppc_hash64_hpte_v_compare(PowerPCCPU *cpu, target_ulong pte0,
+ target_ulong ptem)
+{
+ CPUPPCState *env = &cpu->env;
+
+ if (env->mmu_model & POWERPC_MMU_V3) {
+ return HPTE64_V_COMPARE_3_0(pte0, ptem);
+ } else {
+ return HPTE64_V_COMPARE(pte0, ptem);
+ }
+}
+
static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
const struct ppc_one_seg_page_size *sps,
target_ulong ptem,
@@ -509,8 +538,8 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
pte1 = ppc_hash64_hpte1(cpu, pteg, i);
/* This compares V, B, H (secondary) and the AVPN */
- if (HPTE64_V_COMPARE(pte0, ptem)) {
- *pshift = hpte_page_shift(sps, pte0, pte1);
+ if (ppc_hash64_hpte_v_compare(cpu, pte0, ptem)) {
+ *pshift = hpte_page_shift(cpu, sps, pte0, pte1);
/*
* If there is no match, ignore the PTE, it could simply
* be for a different segment size encoding and the
@@ -570,7 +599,8 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
hash = vsid ^ (epn >> sps->page_shift);
}
- ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
+ ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) &
+ ppc_hash64_hpte_v_avpn(cpu));
ptem |= HPTE64_V_VALID;
/* Page address translation */
@@ -625,7 +655,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
break;
}
- shift = hpte_page_shift(sps, pte0, pte1);
+ shift = hpte_page_shift(cpu, sps, pte0, pte1);
if (shift) {
return shift;
}
@@ -861,7 +891,7 @@ skip_slb_search:
/* 7. Determine the real address from the PTE */
- raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
+ raddr = deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, eaddr);
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, 1ULL << apshift);
@@ -911,7 +941,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
return -1;
}
- return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
+ return deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, addr)
& TARGET_PAGE_MASK;
}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 4fb00ac17abb..4dc6b3968ec0 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -69,8 +69,12 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
#define HPTE64_V_SSIZE_SHIFT 62
#define HPTE64_V_AVPN_SHIFT 7
#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
+#define HPTE64_V_AVPN_3_0 0x000fffffffffff80ULL
#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
+#define HPTE64_V_AVPN_VAL_3_0(x) \
+ (((x) & HPTE64_V_AVPN_3_0) >> HPTE64_V_AVPN_SHIFT)
#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
+#define HPTE64_V_COMPARE_3_0(x, y) (!(((x) ^ (y)) & 0x3fffffffffffff83ULL))
#define HPTE64_V_BOLTED 0x0000000000000010ULL
#define HPTE64_V_LARGE 0x0000000000000004ULL
#define HPTE64_V_SECONDARY 0x0000000000000002ULL
@@ -81,6 +85,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
#define HPTE64_R_KEY_HI 0x3000000000000000ULL
#define HPTE64_R_RPN_SHIFT 12
#define HPTE64_R_RPN 0x0ffffffffffff000ULL
+#define HPTE64_R_RPN_3_0 0x01fffffffffff000ULL
#define HPTE64_R_FLAGS 0x00000000000003ffULL
#define HPTE64_R_PP 0x0000000000000003ULL
#define HPTE64_R_N 0x0000000000000004ULL
@@ -104,9 +109,34 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
#define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
#define PTCR_PTAS 0x000000000000001FULL /* Partition Table Size */
+static inline target_ulong ppc_hash64_hpte_r_rpn(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ return env->mmu_model & POWERPC_MMU_V3 ? HPTE64_R_RPN_3_0 : HPTE64_R_RPN;
+}
+
+static inline target_ulong ppc_hash64_hpte_v_avpn(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ return env->mmu_model & POWERPC_MMU_V3 ? HPTE64_V_AVPN_3_0 : HPTE64_V_AVPN;
+}
+
+static inline target_ulong ppc_hash64_hpte_v_avpn_val(PowerPCCPU *cpu,
+ target_ulong pte0)
+{
+ CPUPPCState *env = &cpu->env;
+
+ return env->mmu_model & POWERPC_MMU_V3 ?
+ HPTE64_V_AVPN_VAL_3_0(pte0) : HPTE64_V_AVPN_VAL(pte0);
+}
+
+hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu);
+
static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
{
- return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
+ return ppc_hash64_hpt_reg(cpu) & SDR_64_HTABORG;
}
static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
@@ -116,7 +146,7 @@ static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
return vhc->hpt_mask(cpu->vhyp);
}
- return (1ULL << ((cpu->env.spr[SPR_SDR1] & SDR_64_HTABSIZE) + 18 - 7)) - 1;
+ return (1ULL << ((ppc_hash64_hpt_reg(cpu) & SDR_64_HTABSIZE) + 18 - 7)) - 1;
}
struct ppc_hash_pte64 {
--
2.13.6
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH 3/3] target/ppc: generalize check on radix when in HV mode
2018-01-31 8:27 [Qemu-devel] [PATCH 0/3] target/ppc: add hash MMU support for the POWER9 PowerNV machine Cédric Le Goater
2018-01-31 8:27 ` [Qemu-devel] [PATCH 1/3] target/ppc: add basic support for PTCR on POWER9 Cédric Le Goater
2018-01-31 8:27 ` [Qemu-devel] [PATCH 2/3] target/ppc: add hash MMU support on POWER9 for PowerNV only Cédric Le Goater
@ 2018-01-31 8:27 ` Cédric Le Goater
2018-02-02 2:43 ` Suraj Jitindar Singh
2 siblings, 1 reply; 10+ messages in thread
From: Cédric Le Goater @ 2018-01-31 8:27 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson
Cc: Suraj Jitindar Singh, Cédric Le Goater
On a POWER9 processor, the first doubleword of the PTCR indicates
whether the partition uses HPT or Radix Trees translation. Use that
bit to check for radix mode on powernv QEMU machines.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/mmu-book3s-v3.c | 17 ++++++++++++++++-
target/ppc/mmu-book3s-v3.h | 8 +-------
target/ppc/mmu-hash64.h | 1 +
target/ppc/mmu_helper.c | 4 ++--
target/ppc/translate_init.c | 2 +-
5 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
index e7798b3582b0..50b60fca3445 100644
--- a/target/ppc/mmu-book3s-v3.c
+++ b/target/ppc/mmu-book3s-v3.c
@@ -24,10 +24,25 @@
#include "mmu-book3s-v3.h"
#include "mmu-radix64.h"
+bool ppc64_radix(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ if (msr_hv) {
+ return ldq_phys(CPU(cpu)->as, cpu->env.spr[SPR_PTCR] &
+ PTCR_PTAB) & PTCR_PTAB_HR;
+ } else {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+
+ return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
+ }
+}
+
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx)
{
- if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
+ if (ppc64_radix(cpu)) { /* radix mode */
return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
} else { /* Guest uses hash */
return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index 56095dab522c..3876cb51b35c 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -37,13 +37,7 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
}
-static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
-{
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
-
- return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
-}
+bool ppc64_radix(PowerPCCPU *cpu);
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx);
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 4dc6b3968ec0..7e2ac64b6eeb 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -106,6 +106,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
/*
* Partition table definitions
*/
+#define PTCR_PTAB_HR PPC_BIT(0) /* 1:Host Radix 0:HPT */
#define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
#define PTCR_PTAS 0x000000000000001FULL /* Partition Table Size */
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index b1e660a4d16a..059863b99b2e 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1286,7 +1286,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
break;
case POWERPC_MMU_VER_3_00:
- if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
+ if (ppc64_radix(ppc_env_get_cpu(env))) {
/* TODO - Unsupported */
} else {
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
@@ -1432,7 +1432,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
case POWERPC_MMU_VER_2_07:
return ppc_hash64_get_phys_page_debug(cpu, addr);
case POWERPC_MMU_VER_3_00:
- if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
+ if (ppc64_radix(ppc_env_get_cpu(env))) {
return ppc_radix64_get_phys_page_debug(cpu, addr);
} else {
return ppc_hash64_get_phys_page_debug(cpu, addr);
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index a6eaa74244ca..07012ee75e81 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8965,7 +8965,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
* KVM but not under TCG. Update the default LPCR to keep new
* CPUs in sync when radix is enabled.
*/
- if (ppc64_radix_guest(cpu)) {
+ if (ppc64_radix(cpu)) {
lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
} else {
lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
--
2.13.6
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 3/3] target/ppc: generalize check on radix when in HV mode
2018-01-31 8:27 ` [Qemu-devel] [PATCH 3/3] target/ppc: generalize check on radix when in HV mode Cédric Le Goater
@ 2018-02-02 2:43 ` Suraj Jitindar Singh
2018-02-02 14:46 ` Cédric Le Goater
0 siblings, 1 reply; 10+ messages in thread
From: Suraj Jitindar Singh @ 2018-02-02 2:43 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc, qemu-devel, David Gibson
On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote:
> On a POWER9 processor, the first doubleword of the PTCR indicates
> whether the partition uses HPT or Radix Trees translation. Use that
> bit to check for radix mode on powernv QEMU machines.
The above isn't quite right.
On a POWER9 processor, the first doubleword of the partition table
entry (as pointed to by the PTCR) indicates whether the host uses HPT
or Radix Tree translation for that partition.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/mmu-book3s-v3.c | 17 ++++++++++++++++-
> target/ppc/mmu-book3s-v3.h | 8 +-------
> target/ppc/mmu-hash64.h | 1 +
> target/ppc/mmu_helper.c | 4 ++--
> target/ppc/translate_init.c | 2 +-
> 5 files changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
> index e7798b3582b0..50b60fca3445 100644
> --- a/target/ppc/mmu-book3s-v3.c
> +++ b/target/ppc/mmu-book3s-v3.c
> @@ -24,10 +24,25 @@
> #include "mmu-book3s-v3.h"
> #include "mmu-radix64.h"
>
> +bool ppc64_radix(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> +
> + if (msr_hv) {
I would prefer something like:
uint64_t prtbe0 = ldq_phys(...);
return prtbe0 & HR;
> + return ldq_phys(CPU(cpu)->as, cpu->env.spr[SPR_PTCR] &
> + PTCR_PTAB) & PTCR_PTAB_HR;
> + } else {
> + PPCVirtualHypervisorClass *vhc =
> + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> +
> + return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> + }
> +}
> +
> int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
> int mmu_idx)
> {
> - if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
> + if (ppc64_radix(cpu)) { /* radix mode */
> return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx,
> mmu_idx);
> } else { /* Guest uses hash */
> return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx,
> mmu_idx);
> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
> index 56095dab522c..3876cb51b35c 100644
> --- a/target/ppc/mmu-book3s-v3.h
> +++ b/target/ppc/mmu-book3s-v3.h
> @@ -37,13 +37,7 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU
> *cpu)
> return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
> }
>
> -static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
> -{
> - PPCVirtualHypervisorClass *vhc =
> - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> -
> - return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> -}
> +bool ppc64_radix(PowerPCCPU *cpu);
>
> int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
> int mmu_idx);
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 4dc6b3968ec0..7e2ac64b6eeb 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -106,6 +106,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
> /*
> * Partition table definitions
> */
> +#define PTCR_PTAB_HR PPC_BIT(0) /* 1:Host
This isn't a bit in the partition table register, it is a bit in the
partition table entry. It should be defined in target/ppc/mmu-book3s-
v3.h as part of "/* Partition Table Entry Fields */"
Also to follow the naming, please call it:
#define PATBE0_HR PPC_BIT(0)
:)
> Radix 0:HPT */
> #define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition
> Table Base */
> #define PTCR_PTAS 0x000000000000001FULL /* Partition
> Table Size */
>
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index b1e660a4d16a..059863b99b2e 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -1286,7 +1286,7 @@ void dump_mmu(FILE *f, fprintf_function
> cpu_fprintf, CPUPPCState *env)
> dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> break;
> case POWERPC_MMU_VER_3_00:
> - if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> + if (ppc64_radix(ppc_env_get_cpu(env))) {
> /* TODO - Unsupported */
> } else {
> dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> @@ -1432,7 +1432,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState
> *cs, vaddr addr)
> case POWERPC_MMU_VER_2_07:
> return ppc_hash64_get_phys_page_debug(cpu, addr);
> case POWERPC_MMU_VER_3_00:
> - if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> + if (ppc64_radix(ppc_env_get_cpu(env))) {
> return ppc_radix64_get_phys_page_debug(cpu, addr);
> } else {
> return ppc_hash64_get_phys_page_debug(cpu, addr);
> diff --git a/target/ppc/translate_init.c
> b/target/ppc/translate_init.c
> index a6eaa74244ca..07012ee75e81 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8965,7 +8965,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu,
> PPCVirtualHypervisor *vhyp)
> * KVM but not under TCG. Update the default LPCR to keep
> new
> * CPUs in sync when radix is enabled.
> */
> - if (ppc64_radix_guest(cpu)) {
> + if (ppc64_radix(cpu)) {
> lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
> } else {
> lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 3/3] target/ppc: generalize check on radix when in HV mode
2018-02-02 2:43 ` Suraj Jitindar Singh
@ 2018-02-02 14:46 ` Cédric Le Goater
0 siblings, 0 replies; 10+ messages in thread
From: Cédric Le Goater @ 2018-02-02 14:46 UTC (permalink / raw)
To: Suraj Jitindar Singh, qemu-ppc, qemu-devel, David Gibson
On 02/02/2018 03:43 AM, Suraj Jitindar Singh wrote:
> On Wed, 2018-01-31 at 09:27 +0100, Cédric Le Goater wrote:
>> On a POWER9 processor, the first doubleword of the PTCR indicates
>> whether the partition uses HPT or Radix Trees translation. Use that
>> bit to check for radix mode on powernv QEMU machines.
>
> The above isn't quite right.
>
> On a POWER9 processor, the first doubleword of the partition table
> entry (as pointed to by the PTCR) indicates whether the host uses HPT
> or Radix Tree translation for that partition.
yes. This is better.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> target/ppc/mmu-book3s-v3.c | 17 ++++++++++++++++-
>> target/ppc/mmu-book3s-v3.h | 8 +-------
>> target/ppc/mmu-hash64.h | 1 +
>> target/ppc/mmu_helper.c | 4 ++--
>> target/ppc/translate_init.c | 2 +-
>> 5 files changed, 21 insertions(+), 11 deletions(-)
>>
>> diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
>> index e7798b3582b0..50b60fca3445 100644
>> --- a/target/ppc/mmu-book3s-v3.c
>> +++ b/target/ppc/mmu-book3s-v3.c
>> @@ -24,10 +24,25 @@
>> #include "mmu-book3s-v3.h"
>> #include "mmu-radix64.h"
>>
>> +bool ppc64_radix(PowerPCCPU *cpu)
>> +{
>> + CPUPPCState *env = &cpu->env;
>> +
>> + if (msr_hv) {
>
> I would prefer something like:
>
> uint64_t prtbe0 = ldq_phys(...);
> return prtbe0 & HR;
I will add a helper to retrieve the first partition table entry,
as we need it in other places in patch 2.
>> + return ldq_phys(CPU(cpu)->as, cpu->env.spr[SPR_PTCR] &
>> + PTCR_PTAB) & PTCR_PTAB_HR;
>> + } else {
>> + PPCVirtualHypervisorClass *vhc =
>> + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
>> +
>> + return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
>> + }
>> +}
>> +
>> int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
>> int mmu_idx)
>> {
>> - if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
>> + if (ppc64_radix(cpu)) { /* radix mode */
>> return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx,
>> mmu_idx);
>> } else { /* Guest uses hash */
>> return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx,
>> mmu_idx);
>> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
>> index 56095dab522c..3876cb51b35c 100644
>> --- a/target/ppc/mmu-book3s-v3.h
>> +++ b/target/ppc/mmu-book3s-v3.h
>> @@ -37,13 +37,7 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU
>> *cpu)
>> return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
>> }
>>
>> -static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
>> -{
>> - PPCVirtualHypervisorClass *vhc =
>> - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
>> -
>> - return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
>> -}
>> +bool ppc64_radix(PowerPCCPU *cpu);
>>
>> int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
>> int mmu_idx);
>> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
>> index 4dc6b3968ec0..7e2ac64b6eeb 100644
>> --- a/target/ppc/mmu-hash64.h
>> +++ b/target/ppc/mmu-hash64.h
>> @@ -106,6 +106,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
>> /*
>> * Partition table definitions
>> */
>> +#define PTCR_PTAB_HR PPC_BIT(0) /* 1:Host
>
> This isn't a bit in the partition table register, it is a bit in the
> partition table entry. It should be defined in target/ppc/mmu-book3s-
> v3.h as part of "/* Partition Table Entry Fields */"
>
> Also to follow the naming, please call it:
> #define PATBE0_HR PPC_BIT(0)
>
> :)
yeah sure.
Thanks,
C.
>> Radix 0:HPT */
>> #define PTCR_PTAB 0x0FFFFFFFFFFFF000ULL /* Partition
>> Table Base */
>> #define PTCR_PTAS 0x000000000000001FULL /* Partition
>> Table Size */
>>
>> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
>> index b1e660a4d16a..059863b99b2e 100644
>> --- a/target/ppc/mmu_helper.c
>> +++ b/target/ppc/mmu_helper.c
>> @@ -1286,7 +1286,7 @@ void dump_mmu(FILE *f, fprintf_function
>> cpu_fprintf, CPUPPCState *env)
>> dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
>> break;
>> case POWERPC_MMU_VER_3_00:
>> - if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
>> + if (ppc64_radix(ppc_env_get_cpu(env))) {
>> /* TODO - Unsupported */
>> } else {
>> dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
>> @@ -1432,7 +1432,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState
>> *cs, vaddr addr)
>> case POWERPC_MMU_VER_2_07:
>> return ppc_hash64_get_phys_page_debug(cpu, addr);
>> case POWERPC_MMU_VER_3_00:
>> - if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
>> + if (ppc64_radix(ppc_env_get_cpu(env))) {
>> return ppc_radix64_get_phys_page_debug(cpu, addr);
>> } else {
>> return ppc_hash64_get_phys_page_debug(cpu, addr);
>> diff --git a/target/ppc/translate_init.c
>> b/target/ppc/translate_init.c
>> index a6eaa74244ca..07012ee75e81 100644
>> --- a/target/ppc/translate_init.c
>> +++ b/target/ppc/translate_init.c
>> @@ -8965,7 +8965,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu,
>> PPCVirtualHypervisor *vhyp)
>> * KVM but not under TCG. Update the default LPCR to keep
>> new
>> * CPUs in sync when radix is enabled.
>> */
>> - if (ppc64_radix_guest(cpu)) {
>> + if (ppc64_radix(cpu)) {
>> lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
>> } else {
>> lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
^ permalink raw reply [flat|nested] 10+ messages in thread