From: Cornelia Huck <cohuck@redhat.com>
To: Pierre Morel <pmorel@linux.vnet.ibm.com>
Cc: Yi Min Zhao <zyimin@linux.vnet.ibm.com>,
qemu-devel@nongnu.org, borntraeger@de.ibm.com,
pasic@linux.vnet.ibm.com, alex.williamson@redhat.com,
marcel@redhat.com
Subject: Re: [Qemu-devel] [PATCH 3/3] s390x/pci: use the right pal and pba in reg_ioat()
Date: Thu, 1 Feb 2018 13:02:26 +0100 [thread overview]
Message-ID: <20180201130226.364e6c76.cohuck@redhat.com> (raw)
In-Reply-To: <b779846e-3e25-5c33-217b-1d9f5e85ec70@linux.vnet.ibm.com>
On Thu, 1 Feb 2018 12:33:01 +0100
Pierre Morel <pmorel@linux.vnet.ibm.com> wrote:
> On 31/01/2018 12:44, Cornelia Huck wrote:
> > On Tue, 30 Jan 2018 10:47:15 +0100
> > Yi Min Zhao <zyimin@linux.vnet.ibm.com> wrote:
> >
> >> When registering ioat, pba should be comprised of leftmost 52 bits and
> >> rightmost 12 binary zeros, and pal should be comprised of leftmost 52
> >> bits and right most 12 binary ones. Let's fixup this.
> >>
> >> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com>
> >> Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com>
> >> ---
> >> hw/s390x/s390-pci-inst.c | 2 ++
> >> 1 file changed, 2 insertions(+)
> >>
> >> diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
> >> index 997a9cc2e9..3fcc330fe3 100644
> >> --- a/hw/s390x/s390-pci-inst.c
> >> +++ b/hw/s390x/s390-pci-inst.c
> >> @@ -865,6 +865,8 @@ static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib,
> >> uint8_t dt = (g_iota >> 2) & 0x7;
> >> uint8_t t = (g_iota >> 11) & 0x1;
> >>
> >> + pba &= ~0xfff;
> >> + pal |= 0xfff;
> >> if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
> >> s390_program_interrupt(env, PGM_OPERAND, 6, ra);
> >> return -EINVAL;
> > It seems like pba and pal are part of the fib, which in turn seems to
> > be provided by the caller. Is that correct? If yes, is it valid for
> > them to not have the rightmost 12 bits as 0s resp. 1s?
> >
> > (Probably answered in the architecture, I know. Might make sense to be
> > a tad more explicit in the description.)
> >
> Yes it is, only word6 and the bits 0-19 of word 7 are used for PAL and
> the zPCI facility treats the right most 12 bits of the PAL as containing
> ones.
>
> For PBA words 4 and 0-19 bits of word 5 with 12 0 append on the right
> provides the PBA.
>
> The lower 12 bits of words 5 and 7 of the FIB are ignored by the facility.
>
> @Yi Min: may be add the last sentence to the commit message.
>
> @Conny: Is it clearer?
Yes, adding the last sentence makes it clearer. Thanks!
next prev parent reply other threads:[~2018-02-01 12:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-30 9:47 [Qemu-devel] [PATCH 0/3] s390x/pci: fixup and optimize IOTLB code Yi Min Zhao
2018-01-30 9:47 ` [Qemu-devel] [PATCH 1/3] s390x/pci: fixup the code walking IOMMU tables Yi Min Zhao
2018-01-31 7:42 ` Thomas Huth
2018-01-31 8:46 ` Yi Min Zhao
2018-01-31 10:58 ` Cornelia Huck
2018-02-01 11:28 ` Yi Min Zhao
2018-02-01 11:56 ` Pierre Morel
2018-02-01 12:15 ` Cornelia Huck
2018-02-01 13:17 ` Pierre Morel
2018-01-30 9:47 ` [Qemu-devel] [PATCH 2/3] s390x/pci: fixup global refresh Yi Min Zhao
2018-01-31 11:35 ` Cornelia Huck
2018-02-01 12:55 ` Pierre Morel
2018-01-30 9:47 ` [Qemu-devel] [PATCH 3/3] s390x/pci: use the right pal and pba in reg_ioat() Yi Min Zhao
2018-01-31 11:44 ` Cornelia Huck
2018-02-01 11:33 ` Pierre Morel
2018-02-01 12:02 ` Cornelia Huck [this message]
2018-02-02 3:50 ` Yi Min Zhao
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