* [Qemu-devel] [PATCH] target/arm/translate.c: Fix missing 'break' for TT insns
@ 2018-02-06 10:39 Peter Maydell
2018-02-06 12:01 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
0 siblings, 1 reply; 2+ messages in thread
From: Peter Maydell @ 2018-02-06 10:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: patches
The code where we added the TT instruction was accidentally
missing a 'break', which meant that after generating the code
to execute the TT we would fall through to 'goto illegal_op'
and generate code to take an UNDEF insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Doh...
target/arm/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 55826b7e5a..572c4d1cb6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9926,6 +9926,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(addr);
tcg_temp_free_i32(op);
store_reg(s, rd, ttresp);
+ break;
}
goto illegal_op;
}
--
2.16.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH] target/arm/translate.c: Fix missing 'break' for TT insns
2018-02-06 10:39 [Qemu-devel] [PATCH] target/arm/translate.c: Fix missing 'break' for TT insns Peter Maydell
@ 2018-02-06 12:01 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 2+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-02-06 12:01 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: patches
[-- Attachment #1: Type: text/plain, Size: 1063 bytes --]
On 02/06/2018 07:39 AM, Peter Maydell wrote:
> The code where we added the TT instruction was accidentally
"In 5158de241b0 ..."
> missing a 'break', which meant that after generating the code
> to execute the TT we would fall through to 'goto illegal_op'
> and generate code to take an UNDEF insn.>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Doh...
>
> target/arm/translate.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 55826b7e5a..572c4d1cb6 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -9926,6 +9926,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> tcg_temp_free_i32(addr);
> tcg_temp_free_i32(op);
> store_reg(s, rd, ttresp);
> + break;
> }
> goto illegal_op;
> }
>
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2018-02-06 10:39 [Qemu-devel] [PATCH] target/arm/translate.c: Fix missing 'break' for TT insns Peter Maydell
2018-02-06 12:01 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
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