From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Paolo Bonzini <pbonzini@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
qemu-devel@nongnu.org,
"Alistair Francis" <alistair.francis@xilinx.com>,
"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>
Subject: [Qemu-devel] [PATCH v11 13/30] sdhci: check Spec v2 capabilities (DMA and 64-bit bus)
Date: Thu, 8 Feb 2018 13:48:01 -0300 [thread overview]
Message-ID: <20180208164818.7961-14-f4bug@amsat.org> (raw)
In-Reply-To: <20180208164818.7961-1-f4bug@amsat.org>
Incorrect value will throw an error.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/sd/sdhci-internal.h | 14 +++++++-------
hw/sd/sdhci.c | 19 +++++++++++++++----
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index c5e26bf8f3..4ed9727ec3 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -89,12 +89,12 @@
FIELD(SDHC_HOSTCTL, LED_CTRL, 0, 1);
FIELD(SDHC_HOSTCTL, DATATRANSFERWIDTH, 1, 1); /* SD mode only */
FIELD(SDHC_HOSTCTL, HIGH_SPEED, 2, 1);
-#define SDHC_CTRL_DMA_CHECK_MASK 0x18
+FIELD(SDHC_HOSTCTL, DMA, 3, 2);
#define SDHC_CTRL_SDMA 0x00
-#define SDHC_CTRL_ADMA1_32 0x08
+#define SDHC_CTRL_ADMA1_32 0x08 /* NOT ALLOWED since v2 */
#define SDHC_CTRL_ADMA2_32 0x10
-#define SDHC_CTRL_ADMA2_64 0x18
-#define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK)
+#define SDHC_CTRL_ADMA2_64 0x18 /* only v1 & v2 (v3 optional) */
+#define SDHC_DMA_TYPE(x) ((x) & R_SDHC_HOSTCTL_DMA_MASK)
/* R/W Power Control Register 0x0 */
#define SDHC_PWRCON 0x29
@@ -185,19 +185,19 @@ FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1);
/* HWInit Capabilities Register 0x05E80080 */
#define SDHC_CAPAB 0x40
-#define SDHC_CAN_DO_ADMA2 0x00080000
-#define SDHC_CAN_DO_ADMA1 0x00100000
-#define SDHC_64_BIT_BUS_SUPPORT (1 << 28)
FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
FIELD(SDHC_CAPAB, TOUNIT, 7, 1);
FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8);
FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2);
+FIELD(SDHC_CAPAB, ADMA2, 19, 1); /* since v2 */
+FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */
FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1);
FIELD(SDHC_CAPAB, SDMA, 22, 1);
FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1);
FIELD(SDHC_CAPAB, V33, 24, 1);
FIELD(SDHC_CAPAB, V30, 25, 1);
FIELD(SDHC_CAPAB, V18, 26, 1);
+FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */
/* HWInit Maximum Current Capabilities Register 0x0 */
#define SDHC_MAXCURR 0x48
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 8962070f24..aa2cbcd981 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -90,6 +90,17 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp)
switch (s->sd_spec_version) {
case 2: /* default version */
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
+ trace_sdhci_capareg("ADMA2", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
+ trace_sdhci_capareg("ADMA1", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
+ trace_sdhci_capareg("64-bit system bus", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
/* fallback */
case 1:
@@ -832,7 +843,7 @@ static void sdhci_data_transfer(void *opaque)
break;
case SDHC_CTRL_ADMA1_32:
- if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
+ if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) {
trace_sdhci_error("ADMA1 not supported");
break;
}
@@ -840,7 +851,7 @@ static void sdhci_data_transfer(void *opaque)
sdhci_do_adma(s);
break;
case SDHC_CTRL_ADMA2_32:
- if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
+ if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) {
trace_sdhci_error("ADMA2 not supported");
break;
}
@@ -848,8 +859,8 @@ static void sdhci_data_transfer(void *opaque)
sdhci_do_adma(s);
break;
case SDHC_CTRL_ADMA2_64:
- if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
- !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
+ if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) ||
+ !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) {
trace_sdhci_error("64 bit ADMA not supported");
break;
}
--
2.16.1
next prev parent reply other threads:[~2018-02-08 16:49 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-08 16:47 [Qemu-devel] [PATCH v11 00/30] SDHCI: clean v1/2 Specs, UHS-I cards tuning sequence Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 01/30] sdhci: use error_propagate(local_err) in realize() Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 02/30] sdhci: add qtest to check the SD capabilities register Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 03/30] sdhci: add check_capab_readonly() qtest Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 04/30] sdhci: add a check_capab_baseclock() qtest Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 05/30] sdhci: add a check_capab_sdma() qtest Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 06/30] sdhci: add qtest to check the SD Spec version Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 07/30] sdhci: add a 'spec_version property' (default to v2) Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 08/30] sdhci: use a numeric value for the default CAPAB register Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 09/30] sdhci: simplify sdhci_get_fifolen() Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 10/30] sdhci: check the Spec v1 capabilities correctness Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 12/30] sdhci: Fix 64-bit ADMA2 Philippe Mathieu-Daudé
2018-02-08 16:48 ` Philippe Mathieu-Daudé [this message]
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 14/30] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64() Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 15/30] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2) Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 18/30] sdhci: rename the hostctl1 register Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 19/30] sdhci: implement the Host Control 2 register (tuning sequence) Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 20/30] sdbus: add trace events Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 21/30] sdhci: implement UHS-I voltage switch Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 22/30] sdhci: implement CMD/DAT[] fields in the Present State register Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 23/30] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3 Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 24/30] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 25/30] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 26/30] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 27/30] hw/arm/xilinx_zynqmp: enable the UHS-I mode Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 28/30] sdhci: check Spec v3 capabilities qtest Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 29/30] sdhci: add a check_capab_v3() qtest Philippe Mathieu-Daudé
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