qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Paolo Bonzini <pbonzini@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-devel@nongnu.org,
	"Alistair Francis" <alistair.francis@xilinx.com>,
	"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
	"Igor Mitsyanko" <i.mitsyanko@gmail.com>,
	"open list:Exynos" <qemu-arm@nongnu.org>
Subject: [Qemu-devel] [PATCH v11 14/30] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64()
Date: Thu,  8 Feb 2018 13:48:02 -0300	[thread overview]
Message-ID: <20180208164818.7961-15-f4bug@amsat.org> (raw)
In-Reply-To: <20180208164818.7961-1-f4bug@amsat.org>

We only set a 32-bit value, but this is a good practice in case this
code is used as reference.

(missed in 5efc9016e52)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
 hw/arm/exynos4210.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index e8e1d81e62..d89322c7ea 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -378,7 +378,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
         DriveInfo *di;
 
         dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
-        qdev_prop_set_uint32(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
+        qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
         qdev_init_nofail(dev);
 
         busdev = SYS_BUS_DEVICE(dev);
-- 
2.16.1

  parent reply	other threads:[~2018-02-08 16:49 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-08 16:47 [Qemu-devel] [PATCH v11 00/30] SDHCI: clean v1/2 Specs, UHS-I cards tuning sequence Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 01/30] sdhci: use error_propagate(local_err) in realize() Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 02/30] sdhci: add qtest to check the SD capabilities register Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 03/30] sdhci: add check_capab_readonly() qtest Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 04/30] sdhci: add a check_capab_baseclock() qtest Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 05/30] sdhci: add a check_capab_sdma() qtest Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 06/30] sdhci: add qtest to check the SD Spec version Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 07/30] sdhci: add a 'spec_version property' (default to v2) Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 08/30] sdhci: use a numeric value for the default CAPAB register Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 09/30] sdhci: simplify sdhci_get_fifolen() Philippe Mathieu-Daudé
2018-02-08 16:47 ` [Qemu-devel] [PATCH v11 10/30] sdhci: check the Spec v1 capabilities correctness Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 12/30] sdhci: Fix 64-bit ADMA2 Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 13/30] sdhci: check Spec v2 capabilities (DMA and 64-bit bus) Philippe Mathieu-Daudé
2018-02-08 16:48 ` Philippe Mathieu-Daudé [this message]
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 15/30] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2) Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 18/30] sdhci: rename the hostctl1 register Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 19/30] sdhci: implement the Host Control 2 register (tuning sequence) Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 20/30] sdbus: add trace events Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 21/30] sdhci: implement UHS-I voltage switch Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 22/30] sdhci: implement CMD/DAT[] fields in the Present State register Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 23/30] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3 Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 24/30] hw/arm/bcm2835_peripherals: change maximum block size to 1kB Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 25/30] hw/arm/fsl-imx6: implement SDHCI Spec. v3 Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 26/30] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 27/30] hw/arm/xilinx_zynqmp: enable the UHS-I mode Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 28/30] sdhci: check Spec v3 capabilities qtest Philippe Mathieu-Daudé
2018-02-08 16:48 ` [Qemu-devel] [PATCH v11 29/30] sdhci: add a check_capab_v3() qtest Philippe Mathieu-Daudé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180208164818.7961-15-f4bug@amsat.org \
    --to=f4bug@amsat.org \
    --cc=alistair.francis@xilinx.com \
    --cc=edgar.iglesias@xilinx.com \
    --cc=i.mitsyanko@gmail.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).