From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH 1/5] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
Date: Sat, 10 Feb 2018 15:05:26 -0800 [thread overview]
Message-ID: <20180210230530.8421-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180210230530.8421-1-richard.henderson@linaro.org>
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 180ab75458..4b102ec356 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4357,7 +4357,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static const ARMCPRegInfo zcr_el1_reginfo = {
.name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
+ .access = PL1_RW, .accessfn = zcr_access,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
.writefn = zcr_write, .raw_writefn = raw_write
};
@@ -4365,7 +4365,7 @@ static const ARMCPRegInfo zcr_el1_reginfo = {
static const ARMCPRegInfo zcr_el2_reginfo = {
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
+ .access = PL2_RW, .accessfn = zcr_access,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
.writefn = zcr_write, .raw_writefn = raw_write
};
@@ -4373,14 +4373,14 @@ static const ARMCPRegInfo zcr_el2_reginfo = {
static const ARMCPRegInfo zcr_no_el2_reginfo = {
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_64BIT,
+ .access = PL2_RW,
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
};
static const ARMCPRegInfo zcr_el3_reginfo = {
.name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL3_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
+ .access = PL3_RW, .accessfn = zcr_access,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
.writefn = zcr_write, .raw_writefn = raw_write
};
--
2.14.3
next prev parent reply other threads:[~2018-02-10 23:05 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-10 23:05 [Qemu-devel] [PATCH 0/5] target/arm: More SVE prep work Richard Henderson
2018-02-10 23:05 ` Richard Henderson [this message]
2018-02-10 23:05 ` [Qemu-devel] [PATCH 2/5] target/arm: Enforce FP access to FPCR/FPSR Richard Henderson
2018-02-10 23:05 ` [Qemu-devel] [PATCH 3/5] target/arm: Suppress TB end for FPCR/FPSR Richard Henderson
2018-02-10 23:05 ` [Qemu-devel] [PATCH 4/5] target/arm: Enforce access to ZCR_EL at translation Richard Henderson
2018-02-10 23:05 ` [Qemu-devel] [PATCH 5/5] target/arm: Handle SVE registers when using clear_vec_high Richard Henderson
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