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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 01/21] hw/arm/aspeed: directly map the serial device to the system address space
Date: Thu, 15 Feb 2018 13:56:42 +0000	[thread overview]
Message-ID: <20180215135702.1340-2-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180215135702.1340-1-peter.maydell@linaro.org>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

(qemu) info mtree
 address-space: cpu-memory-0
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom
     000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io
-      000000001e784000-000000001e78401f (prio 0, i/o): serial
     000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc
     000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1
     [...]
     000000001e720000-000000001e728fff (prio 0, ram): aspeed.sram
     000000001e782000-000000001e782fff (prio 0, i/o): aspeed.timer
+    000000001e784000-000000001e78401f (prio 0, i/o): serial
     000000001e785000-000000001e78501f (prio 0, i/o): aspeed.wdt
     000000001e785020-000000001e78503f (prio 0, i/o): aspeed.wdt

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 20180209085755.30414-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/aspeed_soc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c83b7e207b..2a5d041b3b 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -257,7 +257,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
     /* UART - attach an 8250 to the IO space as our UART5 */
     if (serial_hds[0]) {
         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
-        serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
+        serial_mm_init(get_system_memory(),
+                       ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
                        uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
     }
 
-- 
2.16.1

  reply	other threads:[~2018-02-15 13:57 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-15 13:56 [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell
2018-02-15 13:56 ` Peter Maydell [this message]
2018-02-15 13:56 ` [Qemu-devel] [PULL 02/21] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 03/21] bcm2836: Make CPU type configurable Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 04/21] raspi: Raspberry Pi 3 support Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 05/21] raspi: Add "raspi3" machine type Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 06/21] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 07/21] target/arm: Enforce FP access to FPCR/FPSR Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 08/21] target/arm: Suppress TB end for FPCR/FPSR Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 09/21] target/arm: Enforce access to ZCR_EL at translation Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 10/21] target/arm: Handle SVE registers when using clear_vec_high Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 11/21] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 12/21] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 13/21] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 14/21] hw/intc/armv7m_nvic: Implement v8M CPPWR register Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 15/21] hw/intc/armv7m_nvic: Implement cache ID registers Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 16/21] hw/intc/armv7m_nvic: Implement SCR Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 17/21] target/arm: Implement writing to CONTROL_NS for v8M Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 18/21] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions Peter Maydell
2018-02-15 13:57 ` [Qemu-devel] [PULL 19/21] target/arm: Add AIRCR to vmstate struct Peter Maydell
2018-02-15 13:57 ` [Qemu-devel] [PULL 20/21] target/arm: Migrate v7m.other_sp Peter Maydell
2018-02-15 13:57 ` [Qemu-devel] [PULL 21/21] target/arm: Implement v8M MSPLIM and PSPLIM registers Peter Maydell

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