qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 03/21] bcm2836: Make CPU type configurable
Date: Thu, 15 Feb 2018 13:56:44 +0000	[thread overview]
Message-ID: <20180215135702.1340-4-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180215135702.1340-1-peter.maydell@linaro.org>

From: Pekka Enberg <penberg@iki.fi>

This patch adds a "cpu-type" property to BCM2836 SoC in preparation for
reusing the code for the Raspberry Pi 3, which has a different processor
model.

Signed-off-by: Pekka Enberg <penberg@iki.fi>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2836.h |  1 +
 hw/arm/bcm2836.c         | 17 +++++++++--------
 hw/arm/raspi.c           |  3 +++
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index 76de1996af..4758b4ae54 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -25,6 +25,7 @@ typedef struct BCM2836State {
     DeviceState parent_obj;
     /*< public >*/
 
+    char *cpu_type;
     uint32_t enabled_cpus;
 
     ARMCPU cpus[BCM2836_NCPUS];
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 8c43291112..40e8b25a46 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -26,14 +26,6 @@
 static void bcm2836_init(Object *obj)
 {
     BCM2836State *s = BCM2836(obj);
-    int n;
-
-    for (n = 0; n < BCM2836_NCPUS; n++) {
-        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
-                          "cortex-a15-" TYPE_ARM_CPU);
-        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
-                                  &error_abort);
-    }
 
     object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
     object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
@@ -59,6 +51,14 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 
     /* common peripherals from bcm2835 */
 
+    obj = OBJECT(dev);
+    for (n = 0; n < BCM2836_NCPUS; n++) {
+        object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
+                          s->cpu_type);
+        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
+                                  &error_abort);
+    }
+
     obj = object_property_get_link(OBJECT(dev), "ram", &err);
     if (obj == NULL) {
         error_setg(errp, "%s: required ram link not found: %s",
@@ -150,6 +150,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
 }
 
 static Property bcm2836_props[] = {
+    DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
     DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
     DEFINE_PROP_END_OF_LIST()
 };
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index cd5fa8c3dc..c24a4a1b14 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -135,6 +135,8 @@ static void raspi2_init(MachineState *machine)
     /* Setup the SOC */
     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
                                    &error_abort);
+    object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
+                            &error_abort);
     object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
                             &error_abort);
     object_property_set_int(OBJECT(&s->soc), 0xa21041, "board-rev",
@@ -166,6 +168,7 @@ static void raspi2_machine_init(MachineClass *mc)
     mc->no_parallel = 1;
     mc->no_floppy = 1;
     mc->no_cdrom = 1;
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
     mc->max_cpus = BCM2836_NCPUS;
     mc->min_cpus = BCM2836_NCPUS;
     mc->default_cpus = BCM2836_NCPUS;
-- 
2.16.1

  parent reply	other threads:[~2018-02-15 13:57 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-15 13:56 [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 01/21] hw/arm/aspeed: directly map the serial device to the system address space Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 02/21] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io Peter Maydell
2018-02-15 13:56 ` Peter Maydell [this message]
2018-02-15 13:56 ` [Qemu-devel] [PULL 04/21] raspi: Raspberry Pi 3 support Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 05/21] raspi: Add "raspi3" machine type Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 06/21] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 07/21] target/arm: Enforce FP access to FPCR/FPSR Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 08/21] target/arm: Suppress TB end for FPCR/FPSR Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 09/21] target/arm: Enforce access to ZCR_EL at translation Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 10/21] target/arm: Handle SVE registers when using clear_vec_high Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 11/21] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 12/21] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 13/21] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 14/21] hw/intc/armv7m_nvic: Implement v8M CPPWR register Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 15/21] hw/intc/armv7m_nvic: Implement cache ID registers Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 16/21] hw/intc/armv7m_nvic: Implement SCR Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 17/21] target/arm: Implement writing to CONTROL_NS for v8M Peter Maydell
2018-02-15 13:56 ` [Qemu-devel] [PULL 18/21] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions Peter Maydell
2018-02-15 13:57 ` [Qemu-devel] [PULL 19/21] target/arm: Add AIRCR to vmstate struct Peter Maydell
2018-02-15 13:57 ` [Qemu-devel] [PULL 20/21] target/arm: Migrate v7m.other_sp Peter Maydell
2018-02-15 13:57 ` [Qemu-devel] [PULL 21/21] target/arm: Implement v8M MSPLIM and PSPLIM registers Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180215135702.1340-4-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).