From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36520) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emOPB-0006FH-B5 for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emOPA-0004Hg-L3 for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:13 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46446) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emOPA-0004H0-E2 for qemu-devel@nongnu.org; Thu, 15 Feb 2018 13:37:12 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1emOP9-00027G-ER for qemu-devel@nongnu.org; Thu, 15 Feb 2018 18:37:11 +0000 From: Peter Maydell Date: Thu, 15 Feb 2018 18:36:54 +0000 Message-Id: <20180215183700.26101-15-peter.maydell@linaro.org> In-Reply-To: <20180215183700.26101-1-peter.maydell@linaro.org> References: <20180215183700.26101-1-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 14/20] target/arm: Implement writing to CONTROL_NS for v8M List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org In commit 50f11062d4c896 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20180209165810.6668-8-peter.maydell@linaro.org --- target/arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 550dc3d290..1ae11997fb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10507,6 +10507,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } env->v7m.faultmask[M_REG_NS] = val & 1; return; + case 0x94: /* CONTROL_NS */ + if (!env->v7m.secure) { + return; + } + write_v7m_control_spsel_for_secstate(env, + val & R_V7M_CONTROL_SPSEL_MASK, + M_REG_NS); + env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK; + return; case 0x98: /* SP_NS */ { /* This gives the non-secure SP selected based on whether we're -- 2.16.1