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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 16/20] target/arm: Add AIRCR to vmstate struct
Date: Thu, 15 Feb 2018 18:36:56 +0000	[thread overview]
Message-ID: <20180215183700.26101-17-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180215183700.26101-1-peter.maydell@linaro.org>

In commit commit 3b2e934463121 we added support for the AIRCR
register holding state, but forgot to add it to the vmstate
structs. Since it only holds r/w state if the security extension
is implemented, we can just add it to vmstate_m_security.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-10-peter.maydell@linaro.org
---
 target/arm/machine.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/machine.c b/target/arm/machine.c
index 30fb1454a6..25cdf4d581 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -423,6 +423,10 @@ static const VMStateDescription vmstate_m_security = {
         VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate),
         VMSTATE_UINT32(env.sau.ctrl, ARMCPU),
         VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU),
+        /* AIRCR is not secure-only, but our implementation is R/O if the
+         * security extension is unimplemented, so we migrate it here.
+         */
+        VMSTATE_UINT32(env.v7m.aircr, ARMCPU),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.16.1

  parent reply	other threads:[~2018-02-15 18:37 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-15 18:36 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 01/20] hw/arm/aspeed: directly map the serial device to the system address space Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 02/20] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 03/20] target/arm: Remove ARM_CP_64BIT from ZCR_EL registers Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 04/20] target/arm: Enforce FP access to FPCR/FPSR Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 05/20] target/arm: Suppress TB end for FPCR/FPSR Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 06/20] target/arm: Enforce access to ZCR_EL at translation Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 07/20] target/arm: Handle SVE registers when using clear_vec_high Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 08/20] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 09/20] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 10/20] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 11/20] hw/intc/armv7m_nvic: Implement v8M CPPWR register Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 12/20] hw/intc/armv7m_nvic: Implement cache ID registers Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 13/20] hw/intc/armv7m_nvic: Implement SCR Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 14/20] target/arm: Implement writing to CONTROL_NS for v8M Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 15/20] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions Peter Maydell
2018-02-15 18:36 ` Peter Maydell [this message]
2018-02-15 18:36 ` [Qemu-devel] [PULL 17/20] target/arm: Migrate v7m.other_sp Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 18/20] target/arm: Implement v8M MSPLIM and PSPLIM registers Peter Maydell
2018-02-15 18:36 ` [Qemu-devel] [PULL 19/20] bcm2836: Make CPU type configurable Peter Maydell
2018-02-15 18:37 ` [Qemu-devel] [PULL 20/20] raspi: Raspberry Pi 3 support Peter Maydell
2018-02-15 19:41 ` [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell

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