From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en791-0008W9-P5 for qemu-devel@nongnu.org; Sat, 17 Feb 2018 13:23:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1en78z-0001Qv-JB for qemu-devel@nongnu.org; Sat, 17 Feb 2018 13:23:31 -0500 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:34788) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1en78z-0001QV-DD for qemu-devel@nongnu.org; Sat, 17 Feb 2018 13:23:29 -0500 Received: by mail-pl0-x242.google.com with SMTP id bd10so3449349plb.1 for ; Sat, 17 Feb 2018 10:23:29 -0800 (PST) From: Richard Henderson Date: Sat, 17 Feb 2018 10:22:17 -0800 Message-Id: <20180217182323.25885-2-richard.henderson@linaro.org> In-Reply-To: <20180217182323.25885-1-richard.henderson@linaro.org> References: <20180217182323.25885-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 01/67] target/arm: Enable SVE for aarch64-linux-user List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Enable ARM_FEATURE_SVE for the generic "any" cpu. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++++++ target/arm/cpu64.c | 1 + 2 files changed, 8 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b3ae62db6..10843994c3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -150,6 +150,13 @@ static void arm_cpu_reset(CPUState *s) env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); + /* and to the SVE instructions */ + env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); + env->cp15.cptr_el[3] |= CPTR_EZ; + /* with maximum vector length */ + env->vfp.zcr_el[1] = ARM_MAX_VQ - 1; + env->vfp.zcr_el[2] = ARM_MAX_VQ - 1; + env->vfp.zcr_el[3] = ARM_MAX_VQ - 1; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index efc519b49b..36ef9e9d9d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -231,6 +231,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); + set_feature(&cpu->env, ARM_FEATURE_SVE); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ } -- 2.14.3