[Qemu-devel] [PATCH v2 0/3] target/ppc: add hash MMU support for the POWER9 PowerNV machine

[Qemu-devel] [PATCH v2 0/3] target/ppc: add hash MMU support for the POWER9 PowerNV machine

[Cédric Le Goater]

Hello,

This adds support for the Hash Page Table MMU mode on POWER9 PowerNV
machines. The Radix Tree mode support for the host is still to be done
but we are getting close. 

Thanks,

C. 

Changes since v1:

 - introduced ppc64_v3_get_patbe0()
 - renamed ppc64_radix() in ppc64_v3_radix()
 - renamed partition table definitions to match ISA
 - moved definitions under mmu-book3s-v3.h
 
Cédric Le Goater (3):
  target/ppc: add basic support for PTCR on POWER9
  target/ppc: add hash MMU support on POWER9 for PowerNV only
  target/ppc: generalize check on radix when in HV mode

 hw/ppc/spapr_hcall.c        |  5 +++--
 target/ppc/cpu.h            |  2 ++
 target/ppc/helper.h         |  1 +
 target/ppc/misc_helper.c    | 12 ++++++++++++
 target/ppc/mmu-book3s-v3.c  | 16 ++++++++++++++-
 target/ppc/mmu-book3s-v3.h  | 22 +++++++++++++--------
 target/ppc/mmu-hash64.c     | 48 ++++++++++++++++++++++++++++++++++++---------
 target/ppc/mmu-hash64.h     | 34 ++++++++++++++++++++++++++++++--
 target/ppc/mmu_helper.c     | 32 ++++++++++++++++++++++++++++--
 target/ppc/translate.c      |  3 +++
 target/ppc/translate_init.c | 20 ++++++++++++++++++-
 11 files changed, 170 insertions(+), 25 deletions(-)

-- 
2.13.6

[Qemu-devel] [PATCH v2 1/3] target/ppc: add basic support for PTCR on POWER9

[Cédric Le Goater]

The Partition Table Control Register (PTCR) is a hypervisor privileged
SPR. It contains the host real address of the Partition Table and its
size.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 Changes since v1:

 - renamed partition table definitions to match ISA
 - moved definitions under mmu-book3s-v3.h
 
 target/ppc/cpu.h            |  2 ++
 target/ppc/helper.h         |  1 +
 target/ppc/misc_helper.c    | 12 ++++++++++++
 target/ppc/mmu-book3s-v3.h  |  6 ++++++
 target/ppc/mmu_helper.c     | 28 ++++++++++++++++++++++++++++
 target/ppc/translate.c      |  3 +++
 target/ppc/translate_init.c | 18 ++++++++++++++++++
 7 files changed, 70 insertions(+)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9f8cbbe7aa4d..53061229a0a8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1314,6 +1314,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
 
 #if !defined(CONFIG_USER_ONLY)
 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
+void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
 #endif /* !defined(CONFIG_USER_ONLY) */
 void ppc_store_msr (CPUPPCState *env, target_ulong value);
 
@@ -1605,6 +1606,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
 #define SPR_BOOKE_GIVOR13     (0x1BC)
 #define SPR_BOOKE_GIVOR14     (0x1BD)
 #define SPR_TIR               (0x1BE)
+#define SPR_PTCR              (0x1D0)
 #define SPR_BOOKE_SPEFSCR     (0x200)
 #define SPR_Exxx_BBEAR        (0x201)
 #define SPR_Exxx_BBTAR        (0x202)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5b739179b8b5..19453c68138a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
 #if !defined(CONFIG_USER_ONLY)
 #if defined(TARGET_PPC64)
 DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
+DEF_HELPER_2(store_ptcr, void, env, tl)
 #endif
 DEF_HELPER_2(store_sdr1, void, env, tl)
 DEF_HELPER_2(store_pidr, void, env, tl)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 0e4217821b8e..8c8cba5cc6f1 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
     }
 }
 
+#if defined(TARGET_PPC64)
+void helper_store_ptcr(CPUPPCState *env, target_ulong val)
+{
+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+    if (env->spr[SPR_PTCR] != val) {
+        ppc_store_ptcr(env, val);
+        tlb_flush(CPU(cpu));
+    }
+}
+#endif /* defined(TARGET_PPC64) */
+
 void helper_store_pidr(CPUPPCState *env, target_ulong val)
 {
     PowerPCCPU *cpu = ppc_env_get_cpu(env);
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index 56095dab522c..fdf80987d7b2 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -22,6 +22,12 @@
 
 #ifndef CONFIG_USER_ONLY
 
+/*
+ * Partition table definitions
+ */
+#define PTCR_PATB               0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
+#define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */
+
 /* Partition Table Entry Fields */
 #define PATBE1_GR 0x8000000000000000
 
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 5568d1642b34..82e63552f617 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2028,6 +2028,34 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
     env->spr[SPR_SDR1] = value;
 }
 
+#if defined(TARGET_PPC64)
+void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
+{
+    PowerPCCPU *cpu = ppc_env_get_cpu(env);
+    qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
+
+    assert(!cpu->vhyp);
+
+    if (env->mmu_model & POWERPC_MMU_V3) {
+        target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
+        target_ulong ptas = value & PTCR_PATS;
+
+        if (value & ~ptcr_mask) {
+            error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
+                         value & ~ptcr_mask);
+            value &= ptcr_mask;
+        }
+        if (ptas > 28) {
+            error_report("Invalid PTAS 0x" TARGET_FMT_lx" stored in PTCR",
+                         ptas);
+            return;
+        }
+    }
+    env->spr[SPR_PTCR] = value;
+}
+
+#endif /* defined(TARGET_PPC64) */
+
 /* Segment registers load and store */
 target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
 {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0a0c090c9978..58684d249ed9 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7131,6 +7131,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
         if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
             cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
         }
+        if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
+            cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
+        }
         cpu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",
                     env->spr[SPR_DAR], env->spr[SPR_DSISR]);
         break;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index cbaa343e040d..c998ac2ee405 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -419,6 +419,11 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
     tcg_temp_free(t0);
 }
+static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
+{
+    gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
+}
+
 #endif
 #endif
 
@@ -8166,6 +8171,18 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
 #endif
 }
 
+/* Page Table */
+static void gen_spr_power9_ptcr(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+    spr_register_hv(env, SPR_PTCR, "PTCR",
+                    SPR_NOACCESS, SPR_NOACCESS,
+                    SPR_NOACCESS, SPR_NOACCESS,
+                    &spr_read_generic, &spr_write_ptcr,
+                    0x00000000);
+#endif
+}
+
 static void init_proc_book3s_common(CPUPPCState *env)
 {
     gen_spr_ne_601(env);
@@ -8758,6 +8775,7 @@ static void init_proc_POWER9(CPUPPCState *env)
     gen_spr_power8_ic(env);
     gen_spr_power8_book4(env);
     gen_spr_power8_rpr(env);
+    gen_spr_power9_ptcr(env);
 
     /* POWER9 Specific registers */
     spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
-- 
2.13.6

[Qemu-devel] [PATCH v2 2/3] target/ppc: add hash MMU support on POWER9 for PowerNV only

[Cédric Le Goater]

The HPTE bits definitions are slightly modified in ISA v3.0. Let's add
some helpers to hide the differences in the hash MMU code.

On a POWER9 processor, the Partition Table is composed of a pair of
doublewords per partition. The first doubleword indicates whether the
partition uses HPT or Radix Trees translation and contains the address
of the host's translation table structure and size.

The first doubleword of the PTCR holds the Hash Page Table base
address for the host when the hash MMU is in use. Also add an helper
to retrieve the HPT base address depending on the MMU revision.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 Changes since v1:

 - introduced ppc64_v3_get_patbe0()
 
 hw/ppc/spapr_hcall.c       |  5 +++--
 target/ppc/mmu-book3s-v3.h |  5 +++++
 target/ppc/mmu-hash64.c    | 48 +++++++++++++++++++++++++++++++++++++---------
 target/ppc/mmu-hash64.h    | 34 ++++++++++++++++++++++++++++++--
 4 files changed, 79 insertions(+), 13 deletions(-)

diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 198656048063..738bf7cf5ed1 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -94,7 +94,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
         return H_PARAMETER;
     }
 
-    raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
+    raddr = (ptel & ppc_hash64_hpte_r_rpn(cpu)) & ~((1ULL << apshift) - 1);
 
     if (is_ram_address(spapr, raddr)) {
         /* Regular RAM - should have WIMG=0010 */
@@ -586,7 +586,8 @@ static int rehash_hpte(PowerPCCPU *cpu,
 
     base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
     assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
-    avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
+    avpn = ppc_hash64_hpte_v_avpn_val(cpu, pte0) &
+        ~(((1ULL << base_pg_shift) - 1) >> 23);
 
     if (pte0 & HPTE64_V_SECONDARY) {
         pteg = ~pteg;
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index fdf80987d7b2..a7ab580c3140 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -54,6 +54,11 @@ static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
 int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
                               int mmu_idx);
 
+static inline hwaddr ppc64_v3_get_patbe0(PowerPCCPU *cpu)
+{
+    return ldq_phys(CPU(cpu)->as, cpu->env.spr[SPR_PTCR] & PTCR_PATB);
+}
+
 #endif /* TARGET_PPC64 */
 
 #endif /* CONFIG_USER_ONLY */
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index c9b72b742956..acaeaf82d59c 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -289,6 +289,22 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
     return rt;
 }
 
+hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
+{
+    CPUPPCState *env = &cpu->env;
+
+    if (env->mmu_model & POWERPC_MMU_V3) {
+        if (msr_hv) {
+            return ppc64_v3_get_patbe0(cpu);
+        } else {
+            error_report("HPT Support Unimplemented");
+            exit(1);
+        }
+    } else {
+        return cpu->env.spr[SPR_SDR1];
+    }
+}
+
 /* Check No-Execute or Guarded Storage */
 static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
                                               ppc_hash_pte64_t pte)
@@ -451,8 +467,9 @@ void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
                         false, n * HASH_PTE_SIZE_64);
 }
 
-static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
-    uint64_t pte0, uint64_t pte1)
+static unsigned hpte_page_shift(PowerPCCPU *cpu,
+                                const struct ppc_one_seg_page_size *sps,
+                                uint64_t pte0, uint64_t pte1)
 {
     int i;
 
@@ -478,7 +495,7 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
             continue;
         }
 
-        mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
+        mask = ((1ULL << ps->page_shift) - 1) & ppc_hash64_hpte_r_rpn(cpu);
 
         if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
             return ps->page_shift;
@@ -488,6 +505,18 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
     return 0; /* Bad page size encoding */
 }
 
+static bool ppc_hash64_hpte_v_compare(PowerPCCPU *cpu, target_ulong pte0,
+                                      target_ulong ptem)
+{
+    CPUPPCState *env = &cpu->env;
+
+    if (env->mmu_model & POWERPC_MMU_V3) {
+        return HPTE64_V_COMPARE_3_0(pte0, ptem);
+    } else {
+        return HPTE64_V_COMPARE(pte0, ptem);
+    }
+}
+
 static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
                                      const struct ppc_one_seg_page_size *sps,
                                      target_ulong ptem,
@@ -508,8 +537,8 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
         pte1 = ppc_hash64_hpte1(cpu, pteg, i);
 
         /* This compares V, B, H (secondary) and the AVPN */
-        if (HPTE64_V_COMPARE(pte0, ptem)) {
-            *pshift = hpte_page_shift(sps, pte0, pte1);
+        if (ppc_hash64_hpte_v_compare(cpu, pte0, ptem)) {
+            *pshift = hpte_page_shift(cpu, sps, pte0, pte1);
             /*
              * If there is no match, ignore the PTE, it could simply
              * be for a different segment size encoding and the
@@ -569,7 +598,8 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
         epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
         hash = vsid ^ (epn >> sps->page_shift);
     }
-    ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
+    ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) &
+                                          ppc_hash64_hpte_v_avpn(cpu));
     ptem |= HPTE64_V_VALID;
 
     /* Page address translation */
@@ -624,7 +654,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
             break;
         }
 
-        shift = hpte_page_shift(sps, pte0, pte1);
+        shift = hpte_page_shift(cpu, sps, pte0, pte1);
         if (shift) {
             return shift;
         }
@@ -860,7 +890,7 @@ skip_slb_search:
 
     /* 7. Determine the real address from the PTE */
 
-    raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
+    raddr = deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, eaddr);
 
     tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
                  prot, mmu_idx, 1ULL << apshift);
@@ -910,7 +940,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
         return -1;
     }
 
-    return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
+    return deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, addr)
         & TARGET_PAGE_MASK;
 }
 
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index d297b97d3773..7796b4ff5f11 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -69,8 +69,12 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
 #define HPTE64_V_SSIZE_SHIFT    62
 #define HPTE64_V_AVPN_SHIFT     7
 #define HPTE64_V_AVPN           0x3fffffffffffff80ULL
+#define HPTE64_V_AVPN_3_0       0x000fffffffffff80ULL
 #define HPTE64_V_AVPN_VAL(x)    (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
+#define HPTE64_V_AVPN_VAL_3_0(x)                        \
+    (((x) & HPTE64_V_AVPN_3_0) >> HPTE64_V_AVPN_SHIFT)
 #define HPTE64_V_COMPARE(x, y)  (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
+#define HPTE64_V_COMPARE_3_0(x, y)  (!(((x) ^ (y)) & 0x3fffffffffffff83ULL))
 #define HPTE64_V_BOLTED         0x0000000000000010ULL
 #define HPTE64_V_LARGE          0x0000000000000004ULL
 #define HPTE64_V_SECONDARY      0x0000000000000002ULL
@@ -81,6 +85,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
 #define HPTE64_R_KEY_HI         0x3000000000000000ULL
 #define HPTE64_R_RPN_SHIFT      12
 #define HPTE64_R_RPN            0x0ffffffffffff000ULL
+#define HPTE64_R_RPN_3_0        0x01fffffffffff000ULL
 #define HPTE64_R_FLAGS          0x00000000000003ffULL
 #define HPTE64_R_PP             0x0000000000000003ULL
 #define HPTE64_R_N              0x0000000000000004ULL
@@ -98,9 +103,34 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
 #define HPTE64_V_1TB_SEG        0x4000000000000000ULL
 #define HPTE64_V_VRMA_MASK      0x4001ffffff000000ULL
 
+static inline target_ulong ppc_hash64_hpte_r_rpn(PowerPCCPU *cpu)
+{
+    CPUPPCState *env = &cpu->env;
+
+    return env->mmu_model & POWERPC_MMU_V3 ? HPTE64_R_RPN_3_0 : HPTE64_R_RPN;
+}
+
+static inline target_ulong ppc_hash64_hpte_v_avpn(PowerPCCPU *cpu)
+{
+    CPUPPCState *env = &cpu->env;
+
+    return env->mmu_model & POWERPC_MMU_V3 ? HPTE64_V_AVPN_3_0 : HPTE64_V_AVPN;
+}
+
+static inline target_ulong ppc_hash64_hpte_v_avpn_val(PowerPCCPU *cpu,
+                                                      target_ulong pte0)
+{
+    CPUPPCState *env = &cpu->env;
+
+    return env->mmu_model & POWERPC_MMU_V3 ?
+        HPTE64_V_AVPN_VAL_3_0(pte0) : HPTE64_V_AVPN_VAL(pte0);
+}
+
+hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu);
+
 static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
 {
-    return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
+    return ppc_hash64_hpt_reg(cpu) & SDR_64_HTABORG;
 }
 
 static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
@@ -110,7 +140,7 @@ static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
             PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
         return vhc->hpt_mask(cpu->vhyp);
     }
-    return (1ULL << ((cpu->env.spr[SPR_SDR1] & SDR_64_HTABSIZE) + 18 - 7)) - 1;
+    return (1ULL << ((ppc_hash64_hpt_reg(cpu) & SDR_64_HTABSIZE) + 18 - 7)) - 1;
 }
 
 struct ppc_hash_pte64 {
-- 
2.13.6

[Qemu-devel] [PATCH v2 3/3] target/ppc: generalize check on radix when in HV mode

[Cédric Le Goater]

On a POWER9 processor, the first doubleword of the partition table
entry (as pointed to by the PTCR) indicates whether the host uses HPT
or Radix Tree translation for that partition. Use that bit to check
for radix mode on pseries and powernv QEMU machines.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 Changes since v1:

 - fixed commit log
 - introduced ppc64_v3_get_patbe0()
 - renamed ppc64_radix() in ppc64_v3_radix()
 
 target/ppc/mmu-book3s-v3.c  | 16 +++++++++++++++-
 target/ppc/mmu-book3s-v3.h  | 11 +++--------
 target/ppc/mmu_helper.c     |  4 ++--
 target/ppc/translate_init.c |  2 +-
 4 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
index b60df4408f3b..9d05e07ef6bd 100644
--- a/target/ppc/mmu-book3s-v3.c
+++ b/target/ppc/mmu-book3s-v3.c
@@ -23,10 +23,24 @@
 #include "mmu-book3s-v3.h"
 #include "mmu-radix64.h"
 
+bool ppc64_v3_radix(PowerPCCPU *cpu)
+{
+    CPUPPCState *env = &cpu->env;
+
+    if (msr_hv) {
+        return ppc64_v3_get_patbe0(cpu) & PATBE0_HR;
+    } else  {
+        PPCVirtualHypervisorClass *vhc =
+            PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+
+        return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
+    }
+}
+
 int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
                               int mmu_idx)
 {
-    if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
+    if (ppc64_v3_radix(cpu)) { /* radix mode */
         return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
     } else { /* Guest uses hash */
         return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index a7ab580c3140..a12bb1e28b45 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -29,7 +29,8 @@
 #define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */
 
 /* Partition Table Entry Fields */
-#define PATBE1_GR 0x8000000000000000
+#define PATBE0_HR               PPC_BIT(0)            /* 1:Host Radix 0:HPT   */
+#define PATBE1_GR               PPC_BIT(0)            /* 1:Guest Radix 0:HPT  */
 
 /* Process Table Entry */
 struct prtb_entry {
@@ -43,13 +44,7 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
     return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
 }
 
-static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
-{
-    PPCVirtualHypervisorClass *vhc =
-        PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
-
-    return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
-}
+bool ppc64_v3_radix(PowerPCCPU *cpu);
 
 int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
                               int mmu_idx);
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 82e63552f617..81a43982e421 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1285,7 +1285,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
         dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
         break;
     case POWERPC_MMU_VER_3_00:
-        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
+        if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
             /* TODO - Unsupported */
         } else {
             dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
@@ -1431,7 +1431,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     case POWERPC_MMU_VER_2_07:
         return ppc_hash64_get_phys_page_debug(cpu, addr);
     case POWERPC_MMU_VER_3_00:
-        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
+        if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
             return ppc_radix64_get_phys_page_debug(cpu, addr);
         } else {
             return ppc_hash64_get_phys_page_debug(cpu, addr);
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index c998ac2ee405..21d5dcd15386 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8967,7 +8967,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
          * KVM but not under TCG. Update the default LPCR to keep new
          * CPUs in sync when radix is enabled.
          */
-        if (ppc64_radix_guest(cpu)) {
+        if (ppc64_v3_radix(cpu)) {
             lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
         } else {
             lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
-- 
2.13.6

Re: [Qemu-devel] [PATCH v2 1/3] target/ppc: add basic support for PTCR on POWER9

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 7623 bytes --]

On Fri, Feb 16, 2018 at 09:45:02AM +0100, Cédric Le Goater wrote:
> The Partition Table Control Register (PTCR) is a hypervisor privileged
> SPR. It contains the host real address of the Partition Table and its
> size.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> 
>  Changes since v1:
> 
>  - renamed partition table definitions to match ISA
>  - moved definitions under mmu-book3s-v3.h
>  
>  target/ppc/cpu.h            |  2 ++
>  target/ppc/helper.h         |  1 +
>  target/ppc/misc_helper.c    | 12 ++++++++++++
>  target/ppc/mmu-book3s-v3.h  |  6 ++++++
>  target/ppc/mmu_helper.c     | 28 ++++++++++++++++++++++++++++
>  target/ppc/translate.c      |  3 +++
>  target/ppc/translate_init.c | 18 ++++++++++++++++++
>  7 files changed, 70 insertions(+)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 9f8cbbe7aa4d..53061229a0a8 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1314,6 +1314,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
>  
>  #if !defined(CONFIG_USER_ONLY)
>  void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
>  #endif /* !defined(CONFIG_USER_ONLY) */
>  void ppc_store_msr (CPUPPCState *env, target_ulong value);
>  
> @@ -1605,6 +1606,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
>  #define SPR_BOOKE_GIVOR13     (0x1BC)
>  #define SPR_BOOKE_GIVOR14     (0x1BD)
>  #define SPR_TIR               (0x1BE)
> +#define SPR_PTCR              (0x1D0)
>  #define SPR_BOOKE_SPEFSCR     (0x200)
>  #define SPR_Exxx_BBEAR        (0x201)
>  #define SPR_Exxx_BBTAR        (0x202)
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 5b739179b8b5..19453c68138a 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
>  #if !defined(CONFIG_USER_ONLY)
>  #if defined(TARGET_PPC64)
>  DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
> +DEF_HELPER_2(store_ptcr, void, env, tl)
>  #endif
>  DEF_HELPER_2(store_sdr1, void, env, tl)
>  DEF_HELPER_2(store_pidr, void, env, tl)
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index 0e4217821b8e..8c8cba5cc6f1 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
>      }
>  }
>  
> +#if defined(TARGET_PPC64)
> +void helper_store_ptcr(CPUPPCState *env, target_ulong val)
> +{
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> +    if (env->spr[SPR_PTCR] != val) {
> +        ppc_store_ptcr(env, val);
> +        tlb_flush(CPU(cpu));
> +    }
> +}
> +#endif /* defined(TARGET_PPC64) */
> +
>  void helper_store_pidr(CPUPPCState *env, target_ulong val)
>  {
>      PowerPCCPU *cpu = ppc_env_get_cpu(env);
> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
> index 56095dab522c..fdf80987d7b2 100644
> --- a/target/ppc/mmu-book3s-v3.h
> +++ b/target/ppc/mmu-book3s-v3.h
> @@ -22,6 +22,12 @@
>  
>  #ifndef CONFIG_USER_ONLY
>  
> +/*
> + * Partition table definitions
> + */
> +#define PTCR_PATB               0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
> +#define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */
> +
>  /* Partition Table Entry Fields */
>  #define PATBE1_GR 0x8000000000000000
>  
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 5568d1642b34..82e63552f617 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -2028,6 +2028,34 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
>      env->spr[SPR_SDR1] = value;
>  }
>  
> +#if defined(TARGET_PPC64)
> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
> +{
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +    qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
> +
> +    assert(!cpu->vhyp);
> +
> +    if (env->mmu_model & POWERPC_MMU_V3) {

If it's not MMUv3, the PTCR shouldn't exist, right?  So couldn't this
just be an assert?

> +        target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
> +        target_ulong ptas = value & PTCR_PATS;

Any reason it's "ptas" on the left and "PATS" on the right?

> +
> +        if (value & ~ptcr_mask) {
> +            error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
> +                         value & ~ptcr_mask);
> +            value &= ptcr_mask;
> +        }
> +        if (ptas > 28) {
> +            error_report("Invalid PTAS 0x" TARGET_FMT_lx" stored in PTCR",
> +                         ptas);
> +            return;
> +        }

Is masking / ignoring incorrect values correct, or should it generate
a 0x700?

> +    }
> +    env->spr[SPR_PTCR] = value;
> +}
> +
> +#endif /* defined(TARGET_PPC64) */
> +
>  /* Segment registers load and store */
>  target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
>  {
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 0a0c090c9978..58684d249ed9 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7131,6 +7131,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>          if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
>              cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
>          }
> +        if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
> +            cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
> +        }
>          cpu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",
>                      env->spr[SPR_DAR], env->spr[SPR_DSISR]);
>          break;
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index cbaa343e040d..c998ac2ee405 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -419,6 +419,11 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
>      tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
>      tcg_temp_free(t0);
>  }
> +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> +{
> +    gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
> +}
> +
>  #endif
>  #endif
>  
> @@ -8166,6 +8171,18 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
>  #endif
>  }
>  
> +/* Page Table */
> +static void gen_spr_power9_ptcr(CPUPPCState *env)

Is this the only POWER9 MMU related register?  Otherwise renaming the
function and putting them all here (eventually) would make sense.

> +{
> +#if !defined(CONFIG_USER_ONLY)
> +    spr_register_hv(env, SPR_PTCR, "PTCR",
> +                    SPR_NOACCESS, SPR_NOACCESS,
> +                    SPR_NOACCESS, SPR_NOACCESS,
> +                    &spr_read_generic, &spr_write_ptcr,
> +                    0x00000000);
> +#endif
> +}
> +
>  static void init_proc_book3s_common(CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> @@ -8758,6 +8775,7 @@ static void init_proc_POWER9(CPUPPCState *env)
>      gen_spr_power8_ic(env);
>      gen_spr_power8_book4(env);
>      gen_spr_power8_rpr(env);
> +    gen_spr_power9_ptcr(env);
>  
>      /* POWER9 Specific registers */
>      spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [Qemu-devel] [PATCH v2 2/3] target/ppc: add hash MMU support on POWER9 for PowerNV only

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 10817 bytes --]

On Fri, Feb 16, 2018 at 09:45:03AM +0100, Cédric Le Goater wrote:
> The HPTE bits definitions are slightly modified in ISA v3.0. Let's add
> some helpers to hide the differences in the hash MMU code.
> 
> On a POWER9 processor, the Partition Table is composed of a pair of
> doublewords per partition. The first doubleword indicates whether the
> partition uses HPT or Radix Trees translation and contains the address
> of the host's translation table structure and size.
> 
> The first doubleword of the PTCR holds the Hash Page Table base
> address for the host when the hash MMU is in use. Also add an helper
> to retrieve the HPT base address depending on the MMU revision.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> 
>  Changes since v1:
> 
>  - introduced ppc64_v3_get_patbe0()
>  
>  hw/ppc/spapr_hcall.c       |  5 +++--
>  target/ppc/mmu-book3s-v3.h |  5 +++++
>  target/ppc/mmu-hash64.c    | 48 +++++++++++++++++++++++++++++++++++++---------
>  target/ppc/mmu-hash64.h    | 34 ++++++++++++++++++++++++++++++--
>  4 files changed, 79 insertions(+), 13 deletions(-)
> 
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 198656048063..738bf7cf5ed1 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -94,7 +94,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>          return H_PARAMETER;
>      }
>  
> -    raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
> +    raddr = (ptel & ppc_hash64_hpte_r_rpn(cpu)) & ~((1ULL << apshift) - 1);
>  
>      if (is_ram_address(spapr, raddr)) {
>          /* Regular RAM - should have WIMG=0010 */
> @@ -586,7 +586,8 @@ static int rehash_hpte(PowerPCCPU *cpu,
>  
>      base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
>      assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
> -    avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
> +    avpn = ppc_hash64_hpte_v_avpn_val(cpu, pte0) &
> +        ~(((1ULL << base_pg_shift) - 1) >> 23);
>  
>      if (pte0 & HPTE64_V_SECONDARY) {
>          pteg = ~pteg;
> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
> index fdf80987d7b2..a7ab580c3140 100644
> --- a/target/ppc/mmu-book3s-v3.h
> +++ b/target/ppc/mmu-book3s-v3.h
> @@ -54,6 +54,11 @@ static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
>  int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
>                                int mmu_idx);
>  
> +static inline hwaddr ppc64_v3_get_patbe0(PowerPCCPU *cpu)
> +{
> +    return ldq_phys(CPU(cpu)->as, cpu->env.spr[SPR_PTCR] & PTCR_PATB);
> +}
> +
>  #endif /* TARGET_PPC64 */
>  
>  #endif /* CONFIG_USER_ONLY */
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index c9b72b742956..acaeaf82d59c 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -289,6 +289,22 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
>      return rt;
>  }
>  
> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
> +{
> +    CPUPPCState *env = &cpu->env;
> +
> +    if (env->mmu_model & POWERPC_MMU_V3) {
> +        if (msr_hv) {
> +            return ppc64_v3_get_patbe0(cpu);

This is the only caller, I think you might as well just open-code the
load here.

> +        } else {
> +            error_report("HPT Support Unimplemented");
> +            exit(1);
> +        }
> +    } else {
> +        return cpu->env.spr[SPR_SDR1];
> +    }
> +}
> +
>  /* Check No-Execute or Guarded Storage */
>  static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
>                                                ppc_hash_pte64_t pte)
> @@ -451,8 +467,9 @@ void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
>                          false, n * HASH_PTE_SIZE_64);
>  }
>  
> -static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
> -    uint64_t pte0, uint64_t pte1)
> +static unsigned hpte_page_shift(PowerPCCPU *cpu,
> +                                const struct ppc_one_seg_page_size *sps,
> +                                uint64_t pte0, uint64_t pte1)
>  {
>      int i;
>  
> @@ -478,7 +495,7 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
>              continue;
>          }
>  
> -        mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
> +        mask = ((1ULL << ps->page_shift) - 1) & ppc_hash64_hpte_r_rpn(cpu);
>  
>          if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
>              return ps->page_shift;
> @@ -488,6 +505,18 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
>      return 0; /* Bad page size encoding */
>  }
>  
> +static bool ppc_hash64_hpte_v_compare(PowerPCCPU *cpu, target_ulong pte0,
> +                                      target_ulong ptem)
> +{
> +    CPUPPCState *env = &cpu->env;
> +
> +    if (env->mmu_model & POWERPC_MMU_V3) {
> +        return HPTE64_V_COMPARE_3_0(pte0, ptem);
> +    } else {
> +        return HPTE64_V_COMPARE(pte0, ptem);
> +    }
> +}
> +
>  static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
>                                       const struct ppc_one_seg_page_size *sps,
>                                       target_ulong ptem,
> @@ -508,8 +537,8 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
>          pte1 = ppc_hash64_hpte1(cpu, pteg, i);
>  
>          /* This compares V, B, H (secondary) and the AVPN */
> -        if (HPTE64_V_COMPARE(pte0, ptem)) {
> -            *pshift = hpte_page_shift(sps, pte0, pte1);
> +        if (ppc_hash64_hpte_v_compare(cpu, pte0, ptem)) {
> +            *pshift = hpte_page_shift(cpu, sps, pte0, pte1);
>              /*
>               * If there is no match, ignore the PTE, it could simply
>               * be for a different segment size encoding and the
> @@ -569,7 +598,8 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
>          epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
>          hash = vsid ^ (epn >> sps->page_shift);
>      }
> -    ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
> +    ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) &
> +                                          ppc_hash64_hpte_v_avpn(cpu));
>      ptem |= HPTE64_V_VALID;
>  
>      /* Page address translation */
> @@ -624,7 +654,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
>              break;
>          }
>  
> -        shift = hpte_page_shift(sps, pte0, pte1);
> +        shift = hpte_page_shift(cpu, sps, pte0, pte1);
>          if (shift) {
>              return shift;
>          }
> @@ -860,7 +890,7 @@ skip_slb_search:
>  
>      /* 7. Determine the real address from the PTE */
>  
> -    raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
> +    raddr = deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, eaddr);
>  
>      tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
>                   prot, mmu_idx, 1ULL << apshift);
> @@ -910,7 +940,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
>          return -1;
>      }
>  
> -    return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
> +    return deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, addr)
>          & TARGET_PAGE_MASK;
>  }
>  
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index d297b97d3773..7796b4ff5f11 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -69,8 +69,12 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
>  #define HPTE64_V_SSIZE_SHIFT    62
>  #define HPTE64_V_AVPN_SHIFT     7
>  #define HPTE64_V_AVPN           0x3fffffffffffff80ULL
> +#define HPTE64_V_AVPN_3_0       0x000fffffffffff80ULL
>  #define HPTE64_V_AVPN_VAL(x)    (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
> +#define HPTE64_V_AVPN_VAL_3_0(x)                        \
> +    (((x) & HPTE64_V_AVPN_3_0) >> HPTE64_V_AVPN_SHIFT)
>  #define HPTE64_V_COMPARE(x, y)  (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
> +#define HPTE64_V_COMPARE_3_0(x, y)  (!(((x) ^ (y)) & 0x3fffffffffffff83ULL))
>  #define HPTE64_V_BOLTED         0x0000000000000010ULL
>  #define HPTE64_V_LARGE          0x0000000000000004ULL
>  #define HPTE64_V_SECONDARY      0x0000000000000002ULL
> @@ -81,6 +85,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
>  #define HPTE64_R_KEY_HI         0x3000000000000000ULL
>  #define HPTE64_R_RPN_SHIFT      12
>  #define HPTE64_R_RPN            0x0ffffffffffff000ULL
> +#define HPTE64_R_RPN_3_0        0x01fffffffffff000ULL
>  #define HPTE64_R_FLAGS          0x00000000000003ffULL
>  #define HPTE64_R_PP             0x0000000000000003ULL
>  #define HPTE64_R_N              0x0000000000000004ULL
> @@ -98,9 +103,34 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
>  #define HPTE64_V_1TB_SEG        0x4000000000000000ULL
>  #define HPTE64_V_VRMA_MASK      0x4001ffffff000000ULL
>  
> +static inline target_ulong ppc_hash64_hpte_r_rpn(PowerPCCPU *cpu)
> +{
> +    CPUPPCState *env = &cpu->env;
> +
> +    return env->mmu_model & POWERPC_MMU_V3 ? HPTE64_R_RPN_3_0 : HPTE64_R_RPN;
> +}
> +
> +static inline target_ulong ppc_hash64_hpte_v_avpn(PowerPCCPU *cpu)
> +{
> +    CPUPPCState *env = &cpu->env;
> +
> +    return env->mmu_model & POWERPC_MMU_V3 ? HPTE64_V_AVPN_3_0 : HPTE64_V_AVPN;
> +}
> +
> +static inline target_ulong ppc_hash64_hpte_v_avpn_val(PowerPCCPU *cpu,
> +                                                      target_ulong pte0)
> +{
> +    CPUPPCState *env = &cpu->env;
> +
> +    return env->mmu_model & POWERPC_MMU_V3 ?
> +        HPTE64_V_AVPN_VAL_3_0(pte0) : HPTE64_V_AVPN_VAL(pte0);
> +}
> +
> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu);
> +
>  static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
>  {
> -    return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
> +    return ppc_hash64_hpt_reg(cpu) & SDR_64_HTABORG;
>  }
>  
>  static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
> @@ -110,7 +140,7 @@ static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
>              PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
>          return vhc->hpt_mask(cpu->vhyp);
>      }
> -    return (1ULL << ((cpu->env.spr[SPR_SDR1] & SDR_64_HTABSIZE) + 18 - 7)) - 1;
> +    return (1ULL << ((ppc_hash64_hpt_reg(cpu) & SDR_64_HTABSIZE) + 18 - 7)) - 1;
>  }
>  
>  struct ppc_hash_pte64 {

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 3/3] target/ppc: generalize check on radix when in HV mode

[David Gibson]

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On Fri, Feb 16, 2018 at 09:45:04AM +0100, Cédric Le Goater wrote:
> On a POWER9 processor, the first doubleword of the partition table
> entry (as pointed to by the PTCR) indicates whether the host uses HPT
> or Radix Tree translation for that partition. Use that bit to check
> for radix mode on pseries and powernv QEMU machines.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  Changes since v1:
> 
>  - fixed commit log
>  - introduced ppc64_v3_get_patbe0()
>  - renamed ppc64_radix() in ppc64_v3_radix()
>  
>  target/ppc/mmu-book3s-v3.c  | 16 +++++++++++++++-
>  target/ppc/mmu-book3s-v3.h  | 11 +++--------
>  target/ppc/mmu_helper.c     |  4 ++--
>  target/ppc/translate_init.c |  2 +-
>  4 files changed, 21 insertions(+), 12 deletions(-)
> 
> diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
> index b60df4408f3b..9d05e07ef6bd 100644
> --- a/target/ppc/mmu-book3s-v3.c
> +++ b/target/ppc/mmu-book3s-v3.c
> @@ -23,10 +23,24 @@
>  #include "mmu-book3s-v3.h"
>  #include "mmu-radix64.h"
>  
> +bool ppc64_v3_radix(PowerPCCPU *cpu)
> +{
> +    CPUPPCState *env = &cpu->env;
> +
> +    if (msr_hv) {
> +        return ppc64_v3_get_patbe0(cpu) & PATBE0_HR;
> +    } else  {
> +        PPCVirtualHypervisorClass *vhc =
> +            PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> +
> +        return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> +    }

I think this is backwards.  If cpu->vhyp is set, you should always the
get_patbe() hook, before you go looking at anything else.

This is also wrong if you have a powernv platform but msr_hv is not
set - which is what you'll have once you get to the point of trying to
run guests within an emulated powernv machine.

> +}
> +
>  int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
>                                int mmu_idx)
>  {
> -    if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
> +    if (ppc64_v3_radix(cpu)) { /* radix mode */
>          return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
>      } else { /* Guest uses hash */
>          return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
> index a7ab580c3140..a12bb1e28b45 100644
> --- a/target/ppc/mmu-book3s-v3.h
> +++ b/target/ppc/mmu-book3s-v3.h
> @@ -29,7 +29,8 @@
>  #define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */
>  
>  /* Partition Table Entry Fields */
> -#define PATBE1_GR 0x8000000000000000
> +#define PATBE0_HR               PPC_BIT(0)            /* 1:Host Radix 0:HPT   */
> +#define PATBE1_GR               PPC_BIT(0)            /* 1:Guest Radix 0:HPT  */
>  
>  /* Process Table Entry */
>  struct prtb_entry {
> @@ -43,13 +44,7 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
>      return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
>  }
>  
> -static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
> -{
> -    PPCVirtualHypervisorClass *vhc =
> -        PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> -
> -    return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> -}
> +bool ppc64_v3_radix(PowerPCCPU *cpu);
>  
>  int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
>                                int mmu_idx);
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 82e63552f617..81a43982e421 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -1285,7 +1285,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
>          dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
>          break;
>      case POWERPC_MMU_VER_3_00:
> -        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> +        if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
>              /* TODO - Unsupported */
>          } else {
>              dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> @@ -1431,7 +1431,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>      case POWERPC_MMU_VER_2_07:
>          return ppc_hash64_get_phys_page_debug(cpu, addr);
>      case POWERPC_MMU_VER_3_00:
> -        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> +        if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
>              return ppc_radix64_get_phys_page_debug(cpu, addr);
>          } else {
>              return ppc_hash64_get_phys_page_debug(cpu, addr);
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index c998ac2ee405..21d5dcd15386 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8967,7 +8967,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
>           * KVM but not under TCG. Update the default LPCR to keep new
>           * CPUs in sync when radix is enabled.
>           */
> -        if (ppc64_radix_guest(cpu)) {
> +        if (ppc64_v3_radix(cpu)) {
>              lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
>          } else {
>              lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 1/3] target/ppc: add basic support for PTCR on POWER9

[Cédric Le Goater]

On 02/19/2018 01:21 AM, David Gibson wrote:
> On Fri, Feb 16, 2018 at 09:45:02AM +0100, Cédric Le Goater wrote:
>> The Partition Table Control Register (PTCR) is a hypervisor privileged
>> SPR. It contains the host real address of the Partition Table and its
>> size.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>
>>  Changes since v1:
>>
>>  - renamed partition table definitions to match ISA
>>  - moved definitions under mmu-book3s-v3.h
>>  
>>  target/ppc/cpu.h            |  2 ++
>>  target/ppc/helper.h         |  1 +
>>  target/ppc/misc_helper.c    | 12 ++++++++++++
>>  target/ppc/mmu-book3s-v3.h  |  6 ++++++
>>  target/ppc/mmu_helper.c     | 28 ++++++++++++++++++++++++++++
>>  target/ppc/translate.c      |  3 +++
>>  target/ppc/translate_init.c | 18 ++++++++++++++++++
>>  7 files changed, 70 insertions(+)
>>
>> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
>> index 9f8cbbe7aa4d..53061229a0a8 100644
>> --- a/target/ppc/cpu.h
>> +++ b/target/ppc/cpu.h
>> @@ -1314,6 +1314,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
>>  
>>  #if !defined(CONFIG_USER_ONLY)
>>  void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
>> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
>>  #endif /* !defined(CONFIG_USER_ONLY) */
>>  void ppc_store_msr (CPUPPCState *env, target_ulong value);
>>  
>> @@ -1605,6 +1606,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
>>  #define SPR_BOOKE_GIVOR13     (0x1BC)
>>  #define SPR_BOOKE_GIVOR14     (0x1BD)
>>  #define SPR_TIR               (0x1BE)
>> +#define SPR_PTCR              (0x1D0)
>>  #define SPR_BOOKE_SPEFSCR     (0x200)
>>  #define SPR_Exxx_BBEAR        (0x201)
>>  #define SPR_Exxx_BBTAR        (0x202)
>> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
>> index 5b739179b8b5..19453c68138a 100644
>> --- a/target/ppc/helper.h
>> +++ b/target/ppc/helper.h
>> @@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
>>  #if !defined(CONFIG_USER_ONLY)
>>  #if defined(TARGET_PPC64)
>>  DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
>> +DEF_HELPER_2(store_ptcr, void, env, tl)
>>  #endif
>>  DEF_HELPER_2(store_sdr1, void, env, tl)
>>  DEF_HELPER_2(store_pidr, void, env, tl)
>> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
>> index 0e4217821b8e..8c8cba5cc6f1 100644
>> --- a/target/ppc/misc_helper.c
>> +++ b/target/ppc/misc_helper.c
>> @@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
>>      }
>>  }
>>  
>> +#if defined(TARGET_PPC64)
>> +void helper_store_ptcr(CPUPPCState *env, target_ulong val)
>> +{
>> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>> +
>> +    if (env->spr[SPR_PTCR] != val) {
>> +        ppc_store_ptcr(env, val);
>> +        tlb_flush(CPU(cpu));
>> +    }
>> +}
>> +#endif /* defined(TARGET_PPC64) */
>> +
>>  void helper_store_pidr(CPUPPCState *env, target_ulong val)
>>  {
>>      PowerPCCPU *cpu = ppc_env_get_cpu(env);
>> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
>> index 56095dab522c..fdf80987d7b2 100644
>> --- a/target/ppc/mmu-book3s-v3.h
>> +++ b/target/ppc/mmu-book3s-v3.h
>> @@ -22,6 +22,12 @@
>>  
>>  #ifndef CONFIG_USER_ONLY
>>  
>> +/*
>> + * Partition table definitions
>> + */
>> +#define PTCR_PATB               0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
>> +#define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */
>> +
>>  /* Partition Table Entry Fields */
>>  #define PATBE1_GR 0x8000000000000000
>>  
>> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
>> index 5568d1642b34..82e63552f617 100644
>> --- a/target/ppc/mmu_helper.c
>> +++ b/target/ppc/mmu_helper.c
>> @@ -2028,6 +2028,34 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
>>      env->spr[SPR_SDR1] = value;
>>  }
>>  
>> +#if defined(TARGET_PPC64)
>> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
>> +{
>> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>> +    qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
>> +
>> +    assert(!cpu->vhyp);
>> +
>> +    if (env->mmu_model & POWERPC_MMU_V3) {
> 
> If it's not MMUv3, the PTCR shouldn't exist, right?  So couldn't this
> just be an assert?

yes. I will change that.

> 
>> +        target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
>> +        target_ulong ptas = value & PTCR_PATS;
> 
> Any reason it's "ptas" on the left and "PATS" on the right?

nah. the sed expression I used missed the lower case. 
 
>> +
>> +        if (value & ~ptcr_mask) {
>> +            error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
>> +                         value & ~ptcr_mask);
>> +            value &= ptcr_mask;
>> +        }
>> +        if (ptas > 28) {

This should be 24.

>> +            error_report("Invalid PTAS 0x" TARGET_FMT_lx" stored in PTCR",
>> +                         ptas);
>> +            return;
>> +        }
> 
> Is masking / ignoring incorrect values correct, or should it generate
> a 0x700?

I didn't see anything in the ISA regarding incorrect values for the PTCR.
There are some build checks in the kernel though. When I have some HW, 
I will try some bogus values to see what is reported. 
 
>> +    }
>> +    env->spr[SPR_PTCR] = value;
>> +}
>> +
>> +#endif /* defined(TARGET_PPC64) */
>> +
>>  /* Segment registers load and store */
>>  target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
>>  {
>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
>> index 0a0c090c9978..58684d249ed9 100644
>> --- a/target/ppc/translate.c
>> +++ b/target/ppc/translate.c
>> @@ -7131,6 +7131,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>>          if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
>>              cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
>>          }
>> +        if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
>> +            cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
>> +        }
>>          cpu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",
>>                      env->spr[SPR_DAR], env->spr[SPR_DSISR]);
>>          break;
>> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
>> index cbaa343e040d..c998ac2ee405 100644
>> --- a/target/ppc/translate_init.c
>> +++ b/target/ppc/translate_init.c
>> @@ -419,6 +419,11 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
>>      tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
>>      tcg_temp_free(t0);
>>  }
>> +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
>> +{
>> +    gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
>> +}
>> +
>>  #endif
>>  #endif
>>  
>> @@ -8166,6 +8171,18 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
>>  #endif
>>  }
>>  
>> +/* Page Table */
>> +static void gen_spr_power9_ptcr(CPUPPCState *env)
> 
> Is this the only POWER9 MMU related register?  Otherwise renaming the
> function and putting them all here (eventually) would make sense.

I don't think there are any other POWER9 MMU SPRs but nevertheless,
a '_mmu' prefix has a better signification. 

Thanks,

C. 

>> +{
>> +#if !defined(CONFIG_USER_ONLY)
>> +    spr_register_hv(env, SPR_PTCR, "PTCR",
>> +                    SPR_NOACCESS, SPR_NOACCESS,
>> +                    SPR_NOACCESS, SPR_NOACCESS,
>> +                    &spr_read_generic, &spr_write_ptcr,
>> +                    0x00000000);
>> +#endif
>> +}
>> +
>>  static void init_proc_book3s_common(CPUPPCState *env)
>>  {
>>      gen_spr_ne_601(env);
>> @@ -8758,6 +8775,7 @@ static void init_proc_POWER9(CPUPPCState *env)
>>      gen_spr_power8_ic(env);
>>      gen_spr_power8_book4(env);
>>      gen_spr_power8_rpr(env);
>> +    gen_spr_power9_ptcr(env);
>>  
>>      /* POWER9 Specific registers */
>>      spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
> 

Re: [Qemu-devel] [PATCH v2 2/3] target/ppc: add hash MMU support on POWER9 for PowerNV only

[Cédric Le Goater]

>>  
>> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
>> +{
>> +    CPUPPCState *env = &cpu->env;
>> +
>> +    if (env->mmu_model & POWERPC_MMU_V3) {
>> +        if (msr_hv) {
>> +            return ppc64_v3_get_patbe0(cpu);
> 
> This is the only caller, I think you might as well just open-code the
> load here.

It is used in patch 3/3.

Thanks,

C.

Re: [Qemu-devel] [PATCH v2 3/3] target/ppc: generalize check on radix when in HV mode

[Cédric Le Goater]

On 02/19/2018 04:29 AM, David Gibson wrote:
> On Fri, Feb 16, 2018 at 09:45:04AM +0100, Cédric Le Goater wrote:
>> On a POWER9 processor, the first doubleword of the partition table
>> entry (as pointed to by the PTCR) indicates whether the host uses HPT
>> or Radix Tree translation for that partition. Use that bit to check
>> for radix mode on pseries and powernv QEMU machines.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>  Changes since v1:
>>
>>  - fixed commit log
>>  - introduced ppc64_v3_get_patbe0()
>>  - renamed ppc64_radix() in ppc64_v3_radix()
>>  
>>  target/ppc/mmu-book3s-v3.c  | 16 +++++++++++++++-
>>  target/ppc/mmu-book3s-v3.h  | 11 +++--------
>>  target/ppc/mmu_helper.c     |  4 ++--
>>  target/ppc/translate_init.c |  2 +-
>>  4 files changed, 21 insertions(+), 12 deletions(-)
>>
>> diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
>> index b60df4408f3b..9d05e07ef6bd 100644
>> --- a/target/ppc/mmu-book3s-v3.c
>> +++ b/target/ppc/mmu-book3s-v3.c
>> @@ -23,10 +23,24 @@
>>  #include "mmu-book3s-v3.h"
>>  #include "mmu-radix64.h"
>>  
>> +bool ppc64_v3_radix(PowerPCCPU *cpu)
>> +{
>> +    CPUPPCState *env = &cpu->env;
>> +
>> +    if (msr_hv) {
>> +        return ppc64_v3_get_patbe0(cpu) & PATBE0_HR;
>> +    } else  {
>> +        PPCVirtualHypervisorClass *vhc =
>> +            PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
>> +
>> +        return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
>> +    }
> 
> I think this is backwards.  If cpu->vhyp is set, you should always the
> get_patbe() hook, before you go looking at anything else.

OK. So, we should probably change the ppc64_radix_guest() name to 
reflect its relation to spapr. How about ppc64_v3_radix_spapr() ? 
 
> This is also wrong if you have a powernv platform but msr_hv is not
> set - which is what you'll have once you get to the point of trying to
> run guests within an emulated powernv machine.

That is a good goal to reach ! I will add an error for the !msr_hv
case.

Thanks,

C.


>> +}
>> +
>>  int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
>>                                int mmu_idx)
>>  {
>> -    if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
>> +    if (ppc64_v3_radix(cpu)) { /* radix mode */
>>          return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
>>      } else { /* Guest uses hash */
>>          return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
>> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
>> index a7ab580c3140..a12bb1e28b45 100644
>> --- a/target/ppc/mmu-book3s-v3.h
>> +++ b/target/ppc/mmu-book3s-v3.h
>> @@ -29,7 +29,8 @@
>>  #define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */
>>  
>>  /* Partition Table Entry Fields */
>> -#define PATBE1_GR 0x8000000000000000
>> +#define PATBE0_HR               PPC_BIT(0)            /* 1:Host Radix 0:HPT   */
>> +#define PATBE1_GR               PPC_BIT(0)            /* 1:Guest Radix 0:HPT  */
>>  
>>  /* Process Table Entry */
>>  struct prtb_entry {
>> @@ -43,13 +44,7 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
>>      return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
>>  }
>>  
>> -static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
>> -{
>> -    PPCVirtualHypervisorClass *vhc =
>> -        PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
>> -
>> -    return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
>> -}
>> +bool ppc64_v3_radix(PowerPCCPU *cpu);
>>  
>>  int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
>>                                int mmu_idx);
>> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
>> index 82e63552f617..81a43982e421 100644
>> --- a/target/ppc/mmu_helper.c
>> +++ b/target/ppc/mmu_helper.c
>> @@ -1285,7 +1285,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
>>          dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
>>          break;
>>      case POWERPC_MMU_VER_3_00:
>> -        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
>> +        if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
>>              /* TODO - Unsupported */
>>          } else {
>>              dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
>> @@ -1431,7 +1431,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>>      case POWERPC_MMU_VER_2_07:
>>          return ppc_hash64_get_phys_page_debug(cpu, addr);
>>      case POWERPC_MMU_VER_3_00:
>> -        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
>> +        if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
>>              return ppc_radix64_get_phys_page_debug(cpu, addr);
>>          } else {
>>              return ppc_hash64_get_phys_page_debug(cpu, addr);
>> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
>> index c998ac2ee405..21d5dcd15386 100644
>> --- a/target/ppc/translate_init.c
>> +++ b/target/ppc/translate_init.c
>> @@ -8967,7 +8967,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
>>           * KVM but not under TCG. Update the default LPCR to keep new
>>           * CPUs in sync when radix is enabled.
>>           */
>> -        if (ppc64_radix_guest(cpu)) {
>> +        if (ppc64_v3_radix(cpu)) {
>>              lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
>>          } else {
>>              lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
> 

Re: [Qemu-devel] [PATCH v2 3/3] target/ppc: generalize check on radix when in HV mode

[David Gibson]

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On Mon, Mar 12, 2018 at 07:36:05PM +0100, Cédric Le Goater wrote:
> On 02/19/2018 04:29 AM, David Gibson wrote:
> > On Fri, Feb 16, 2018 at 09:45:04AM +0100, Cédric Le Goater wrote:
> >> On a POWER9 processor, the first doubleword of the partition table
> >> entry (as pointed to by the PTCR) indicates whether the host uses HPT
> >> or Radix Tree translation for that partition. Use that bit to check
> >> for radix mode on pseries and powernv QEMU machines.
> >>
> >> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >> ---
> >>  Changes since v1:
> >>
> >>  - fixed commit log
> >>  - introduced ppc64_v3_get_patbe0()
> >>  - renamed ppc64_radix() in ppc64_v3_radix()
> >>  
> >>  target/ppc/mmu-book3s-v3.c  | 16 +++++++++++++++-
> >>  target/ppc/mmu-book3s-v3.h  | 11 +++--------
> >>  target/ppc/mmu_helper.c     |  4 ++--
> >>  target/ppc/translate_init.c |  2 +-
> >>  4 files changed, 21 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
> >> index b60df4408f3b..9d05e07ef6bd 100644
> >> --- a/target/ppc/mmu-book3s-v3.c
> >> +++ b/target/ppc/mmu-book3s-v3.c
> >> @@ -23,10 +23,24 @@
> >>  #include "mmu-book3s-v3.h"
> >>  #include "mmu-radix64.h"
> >>  
> >> +bool ppc64_v3_radix(PowerPCCPU *cpu)
> >> +{
> >> +    CPUPPCState *env = &cpu->env;
> >> +
> >> +    if (msr_hv) {
> >> +        return ppc64_v3_get_patbe0(cpu) & PATBE0_HR;
> >> +    } else  {
> >> +        PPCVirtualHypervisorClass *vhc =
> >> +            PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> >> +
> >> +        return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> >> +    }
> > 
> > I think this is backwards.  If cpu->vhyp is set, you should always the
> > get_patbe() hook, before you go looking at anything else.
> 
> OK. So, we should probably change the ppc64_radix_guest() name to 
> reflect its relation to spapr. How about ppc64_v3_radix_spapr() ?

Um.. why?  The existing name is accurate AFAICT.  It already says
"guest", and even in the unlikely event of a non PAPR guest, the
vhyp->get_patbe method can abstract that correctly.

> > This is also wrong if you have a powernv platform but msr_hv is not
> > set - which is what you'll have once you get to the point of trying to
> > run guests within an emulated powernv machine.
> 
> That is a good goal to reach ! I will add an error for the !msr_hv
> case.
> 
> Thanks,
> 
> C.
> 
> 
> >> +}
> >> +
> >>  int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
> >>                                int mmu_idx)
> >>  {
> >> -    if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
> >> +    if (ppc64_v3_radix(cpu)) { /* radix mode */
> >>          return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
> >>      } else { /* Guest uses hash */
> >>          return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
> >> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
> >> index a7ab580c3140..a12bb1e28b45 100644
> >> --- a/target/ppc/mmu-book3s-v3.h
> >> +++ b/target/ppc/mmu-book3s-v3.h
> >> @@ -29,7 +29,8 @@
> >>  #define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */
> >>  
> >>  /* Partition Table Entry Fields */
> >> -#define PATBE1_GR 0x8000000000000000
> >> +#define PATBE0_HR               PPC_BIT(0)            /* 1:Host Radix 0:HPT   */
> >> +#define PATBE1_GR               PPC_BIT(0)            /* 1:Guest Radix 0:HPT  */
> >>  
> >>  /* Process Table Entry */
> >>  struct prtb_entry {
> >> @@ -43,13 +44,7 @@ static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
> >>      return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
> >>  }
> >>  
> >> -static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
> >> -{
> >> -    PPCVirtualHypervisorClass *vhc =
> >> -        PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> >> -
> >> -    return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> >> -}
> >> +bool ppc64_v3_radix(PowerPCCPU *cpu);
> >>  
> >>  int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
> >>                                int mmu_idx);
> >> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> >> index 82e63552f617..81a43982e421 100644
> >> --- a/target/ppc/mmu_helper.c
> >> +++ b/target/ppc/mmu_helper.c
> >> @@ -1285,7 +1285,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
> >>          dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> >>          break;
> >>      case POWERPC_MMU_VER_3_00:
> >> -        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> >> +        if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
> >>              /* TODO - Unsupported */
> >>          } else {
> >>              dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> >> @@ -1431,7 +1431,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> >>      case POWERPC_MMU_VER_2_07:
> >>          return ppc_hash64_get_phys_page_debug(cpu, addr);
> >>      case POWERPC_MMU_VER_3_00:
> >> -        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> >> +        if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
> >>              return ppc_radix64_get_phys_page_debug(cpu, addr);
> >>          } else {
> >>              return ppc_hash64_get_phys_page_debug(cpu, addr);
> >> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> >> index c998ac2ee405..21d5dcd15386 100644
> >> --- a/target/ppc/translate_init.c
> >> +++ b/target/ppc/translate_init.c
> >> @@ -8967,7 +8967,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
> >>           * KVM but not under TCG. Update the default LPCR to keep new
> >>           * CPUs in sync when radix is enabled.
> >>           */
> >> -        if (ppc64_radix_guest(cpu)) {
> >> +        if (ppc64_v3_radix(cpu)) {
> >>              lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
> >>          } else {
> >>              lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
> > 
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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