From: "Emilio G. Cota" <cota@braap.org>
To: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
Cc: qemu-devel@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Petar Jovanovic" <petar.jovanovic@mips.com>,
"Fam Zheng" <famz@redhat.com>,
"Aleksandar Markovic" <aleksandar.markovic@mips.com>,
"Raghu Gandham" <raghu.gandham@mips.com>,
"Yongbok Kim" <yongbok.kim@mips.com>,
"Riku Voipio" <riku.voipio@iki.fi>,
"Laurent Vivier" <laurent@vivier.eu>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Goran Ferenc" <goran.ferenc@mips.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Miodrag Dinic" <miodrag.dinic@mips.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Richard Henderson" <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH v2 2/6] target/mips: reimplement SC instruction emulation and use cmpxchg
Date: Thu, 22 Feb 2018 17:33:27 -0500 [thread overview]
Message-ID: <20180222223327.GA25701@flamenco> (raw)
In-Reply-To: <1519324303-5674-3-git-send-email-aleksandar.markovic@rt-rk.com>
On Thu, Feb 22, 2018 at 19:31:39 +0100, Aleksandar Markovic wrote:
> From: Leon Alrae <lean.alrae@imgtec.com>
>
> Completely rewrite conditional stores handling. Use cmpxchg.
>
> This eliminates need for separate implementations of SC instruction
> emulation for user and system emulation.
>
> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com>
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
> Reviewed-by: Richard Henderson <rth@twiddle.net>
Tested-by: Emilio G. Cota <cota@braap.org>
Got some stats with qht-bench on mipsel-user -- note that I think
you'd get more meaningful numbers with qht-bench than with
atomic_add-bench, since the latter isn't representative of a useful
workload--rather it's a pathological case unless that doesn't
scale at all unless you increase the range quite a bit.
Also, you might want to add perf numbers to the appropriate commit
log, otherwise they'll be absent from the commit history.
Here are some numbers I just gathered for qht-bench, feel
free to include them in this commit's log:
mipsel-linux-user tests/qht-bench -d 5 -n 1 -u 20 -g 10000
Host: AMD Opteron(tm) Processor 6376
120 +-+-+---------+----------+---------+---------#D-+-+
| + + + + ## + |
| master ***B*** ## |
100 +MTTCGv2 ###D### ### +-+
| ## |
| ## |
80 +-+ ### +-+
| ## |
| # ## |
60 +-+ #D# +-+
| ### |
| ## |
40 +-+ ### +-+
| #D# |
| ## |
20 +-+ D# +-+
| ## |
| +## + + + + |
0 +-+-B****B****B**********B********************B-+-+
1 16 Threads 48 64
png: https://imgur.com/hTwhw70
Thanks for doing this work!
Emilio
next prev parent reply other threads:[~2018-02-22 22:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-22 18:31 [Qemu-devel] [PATCH v2 0/6] target-mips: support MTTCG feature Aleksandar Markovic
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 1/6] target/mips: compare virtual addresses in LL/SC sequence Aleksandar Markovic
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 2/6] target/mips: reimplement SC instruction emulation and use cmpxchg Aleksandar Markovic
2018-02-22 22:33 ` Emilio G. Cota [this message]
2018-02-22 22:39 ` Emilio G. Cota
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 3/6] hw/mips_int: hold BQL for all interrupt requests Aleksandar Markovic
2018-04-04 10:23 ` Alex Bennée
2018-04-04 11:23 ` Paolo Bonzini
2018-04-04 13:44 ` Alex Bennée
2018-04-04 14:42 ` Paolo Bonzini
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 4/6] target/mips: hold BQL in mips_vpe_wake() Aleksandar Markovic
2018-04-04 10:24 ` Alex Bennée
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 5/6] hw/mips_cpc: kick a VP when putting it into Run state Aleksandar Markovic
2018-04-04 10:25 ` Alex Bennée
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 6/6] target/mips: introduce MTTCG-enabled builds Aleksandar Markovic
2018-04-04 10:25 ` Alex Bennée
2018-04-04 10:27 ` [Qemu-devel] [PATCH v2 0/6] target-mips: support MTTCG feature Alex Bennée
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