From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org,
"Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Crosthwaite" <crosthwaite.peter@gmail.com>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v3 01/31] include/exec/helper-head.h: support f16 in helper calls
Date: Fri, 23 Feb 2018 15:36:06 +0000 [thread overview]
Message-ID: <20180223153636.29809-2-alex.bennee@linaro.org> (raw)
In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org>
This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/helper-head.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index e1fd08f2ba..15b6a68de3 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -26,6 +26,7 @@
#define dh_alias_int i32
#define dh_alias_i64 i64
#define dh_alias_s64 i64
+#define dh_alias_f16 i32
#define dh_alias_f32 i32
#define dh_alias_f64 i64
#define dh_alias_ptr ptr
@@ -38,6 +39,7 @@
#define dh_ctype_int int
#define dh_ctype_i64 uint64_t
#define dh_ctype_s64 int64_t
+#define dh_ctype_f16 float16
#define dh_ctype_f32 float32
#define dh_ctype_f64 float64
#define dh_ctype_ptr void *
@@ -94,6 +96,7 @@
#define dh_is_signed_s32 1
#define dh_is_signed_i64 0
#define dh_is_signed_s64 1
+#define dh_is_signed_f16 0
#define dh_is_signed_f32 0
#define dh_is_signed_f64 0
#define dh_is_signed_tl 0
--
2.15.1
next prev parent reply other threads:[~2018-02-23 15:36 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-23 15:36 [Qemu-devel] [PATCH v3 00/31] Add ARMv8.2 half-precision functions Alex Bennée
2018-02-23 15:36 ` Alex Bennée [this message]
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 02/31] target/arm/cpu64: introduce ARM_V8_FP16 feature bit Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values Alex Bennée
2018-02-23 23:30 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags Alex Bennée
2018-02-23 23:51 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 05/31] target/arm/helper: pass explicit fpst to set_rmode Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 06/31] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 07/31] arm/translate-a64: handle_3same_64 comment fix Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 09/31] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 11/31] arm/translate-a64: add FP16 FMULA/X/S " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 12/31] arm/translate-a64: add FP16 FR[ECP/SQRT]S " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 Alex Bennée
2018-02-23 23:59 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 14/31] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed Alex Bennée
2018-02-24 0:03 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 15/31] arm/translate-a64: add FP16 x2 ops for simd_indexed Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 16/31] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 17/31] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 Alex Bennée
2018-02-24 0:13 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 18/31] arm/translate-a64: add FCVTxx " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 19/31] arm/translate-a64: add FP16 FCMxx (zero) " Alex Bennée
2018-02-24 0:19 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 20/31] arm/translate-a64: add FP16 SCVTF/UCVFT " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 21/31] arm/translate-a64: add FP16 FNEG/FABS " Alex Bennée
2018-02-24 0:28 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 22/31] arm/helper.c: re-factor recpe and add recepe_f16 Alex Bennée
2018-02-24 0:34 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 23/31] arm/translate-a64: add FP16 FRECPE Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 24/31] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 25/31] arm/translate-a64: add FP16 FSQRT " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 26/31] arm/helper.c: re-factor rsqrte and add rsqrte_f16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 27/31] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 28/31] arm/translate-a64: add FP16 FMOV to simd_mod_imm Alex Bennée
2018-02-24 0:42 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 29/31] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 30/31] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 Alex Bennée
2018-02-24 0:49 ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 31/31] arm/translate-a64: add all single op FP16 to handle_fp_1src_half Alex Bennée
2018-02-24 0:53 ` Richard Henderson
2018-02-24 0:58 ` [Qemu-devel] [PATCH v3 00/31] Add ARMv8.2 half-precision functions Richard Henderson
2018-02-24 7:59 ` no-reply
2018-02-24 12:36 ` no-reply
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