From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46064) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFUm-00005O-2X for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFUl-0005sb-6b for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:48 -0500 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:42892) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFUl-0005qn-0p for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:47 -0500 Received: by mail-wr0-x243.google.com with SMTP id k9so14528642wre.9 for ; Fri, 23 Feb 2018 07:42:46 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Fri, 23 Feb 2018 15:36:28 +0000 Message-Id: <20180223153636.29809-24-alex.bennee@linaro.org> In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 23/31] arm/translate-a64: add FP16 FRECPE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Now we have added f16 during the re-factoring we can simply call the helper. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 00b04d34f9..56de5711fe 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11311,6 +11311,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6d: /* FCMLE (zero) */ handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); return; + case 0x3d: /* FRECPE */ + break; case 0x18: /* FRINTN */ need_rmode = true; only_in_vector = true; @@ -11431,6 +11433,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x3b: /* FCVTZS */ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ @@ -11466,6 +11471,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x3b: /* FCVTZS */ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ -- 2.15.1