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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>
Subject: [Qemu-devel] [PATCH v3 07/31] arm/translate-a64: handle_3same_64 comment fix
Date: Fri, 23 Feb 2018 15:36:12 +0000	[thread overview]
Message-ID: <20180223153636.29809-8-alex.bennee@linaro.org> (raw)
In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org>

We do implement all the opcodes.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ebaf4571ac..5dd54b7ac4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7278,8 +7278,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
     /* Handle 64x64->64 opcodes which are shared between the scalar
      * and vector 3-same groups. We cover every opcode where size == 3
      * is valid in either the three-reg-same (integer, not pairwise)
-     * or scalar-three-reg-same groups. (Some opcodes are not yet
-     * implemented.)
+     * or scalar-three-reg-same groups.
      */
     TCGCond cond;
 
-- 
2.15.1

  parent reply	other threads:[~2018-02-23 15:36 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-23 15:36 [Qemu-devel] [PATCH v3 00/31] Add ARMv8.2 half-precision functions Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 01/31] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 02/31] target/arm/cpu64: introduce ARM_V8_FP16 feature bit Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values Alex Bennée
2018-02-23 23:30   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags Alex Bennée
2018-02-23 23:51   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 05/31] target/arm/helper: pass explicit fpst to set_rmode Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 06/31] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
2018-02-23 15:36 ` Alex Bennée [this message]
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 09/31] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 11/31] arm/translate-a64: add FP16 FMULA/X/S " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 12/31] arm/translate-a64: add FP16 FR[ECP/SQRT]S " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 Alex Bennée
2018-02-23 23:59   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 14/31] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed Alex Bennée
2018-02-24  0:03   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 15/31] arm/translate-a64: add FP16 x2 ops for simd_indexed Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 16/31] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 17/31] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 Alex Bennée
2018-02-24  0:13   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 18/31] arm/translate-a64: add FCVTxx " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 19/31] arm/translate-a64: add FP16 FCMxx (zero) " Alex Bennée
2018-02-24  0:19   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 20/31] arm/translate-a64: add FP16 SCVTF/UCVFT " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 21/31] arm/translate-a64: add FP16 FNEG/FABS " Alex Bennée
2018-02-24  0:28   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 22/31] arm/helper.c: re-factor recpe and add recepe_f16 Alex Bennée
2018-02-24  0:34   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 23/31] arm/translate-a64: add FP16 FRECPE Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 24/31] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 25/31] arm/translate-a64: add FP16 FSQRT " Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 26/31] arm/helper.c: re-factor rsqrte and add rsqrte_f16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 27/31] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 28/31] arm/translate-a64: add FP16 FMOV to simd_mod_imm Alex Bennée
2018-02-24  0:42   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 29/31] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise Alex Bennée
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 30/31] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 Alex Bennée
2018-02-24  0:49   ` Richard Henderson
2018-02-23 15:36 ` [Qemu-devel] [PATCH v3 31/31] arm/translate-a64: add all single op FP16 to handle_fp_1src_half Alex Bennée
2018-02-24  0:53   ` Richard Henderson
2018-02-24  0:58 ` [Qemu-devel] [PATCH v3 00/31] Add ARMv8.2 half-precision functions Richard Henderson
2018-02-24  7:59 ` no-reply
2018-02-24 12:36 ` no-reply

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