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From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Michael Clark <mjc@sifive.com>
Cc: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission
Date: Mon, 26 Feb 2018 10:47:23 +0000	[thread overview]
Message-ID: <20180226104723.GH14196@redhat.com> (raw)
In-Reply-To: <CAHNT7NvMMAD6sAT60RnLgFXwdFPWHEXtysMQt04Qejnpw30Bkg@mail.gmail.com>

On Sat, Feb 24, 2018 at 09:05:49AM +1300, Michael Clark wrote:
> Dear Daniel,
> 
> We've had this discussion on a recent pull request where some code was
> going to be copied directly from hw/arm/virt.c to hw/riscv/virt.c and we
> have subsequently relicensed the recipient file as GPLv2+. This code has
> not yet been incorporated into the port. Besides naming conventions and use
> of some common APIs, however the logic in hw/riscv/virt.c is original work.
> Try diffing them. I wrote the device tree code from scratch and we have a
> unique memory map, and the other functions are dervied from other RISC-V
> machines which are MIT licensed.
> 
> - https://github.com/riscv/riscv-qemu/pull/109
> 
> In any case, SiFive are happy to license their contributions as GPLv2+.
> We'll need to get the main contributors to agree to re-license to GPLv2+ or
> fall back to having GPLv2+ prefix the MIT license, as MIT is compatible
> with GPLv2+. Stefan O'Rear has commented that he is happy for his code to
> be GPLv2+ and so is SiFive, but we'll need to get confirmation from Sagar,
> one of the main port contributors, and potentially the whole list of
> contributors to do complete due diligence on re-licensing. i.e. if we want
> to eradicate MIT license from the code-base.
> 
> SiFive have made substantial changes to all of the non-GPLv2+ files in the
> port, and SiFive can license their contributions as GPLv2+ which would
> allow us to prefix all files in hw/riscv with GPLv2+. The only issue is
> that we must get approval from contributors to completely remove the MIT
> license, as the original contributors licensed their code under that
> license, as is the case for all of Fabrice's original code and many other
> parts of the code base e.g. GPEX hw/pci-host/gpex.c.
> 
> SiFive have made substantial changes to all files in the RISC-V port, so we
> would be empowered to at least prefix the MIT license with GPLv2+.
> 
> Is that acceptable? the MIT terms are compatible with GPLv2+ as MIT is a
> "permissive-license".

I accept that MIT is compatible with GPLv2+, so that's not an immediate legal
problem. The issue is that as we add more & more different licenses to QEMU,
it becomes a maintenance burden to developers, especially when doing code
refactoring across files. You have to be careful you're not taking a piece
of GPLv2+ code and copying/moving it into a file that's MIT licensed, as
that would be non-compliant. We already suffer this problem with our mixture
of GPLv2-only and GPLv2+ and LGPLv2+ and BSD licensed code. So I'm personally
loathe to see us add yet another license to the mix.

Ultimately though, Peter Maydall is the one who has the final say on whether
we'll pull the patch series. So I'll defer to him for a definitive answer on
whether its OK for riscv files to add MIT license to the mix, either long
term or as a temporary state.


> 
> 'cc Sagar, Bastian, as they have been main contributors to the port in the
> past...
> 
> Regards,
> Michael.
> 
> On Fri, Feb 23, 2018 at 11:10 PM, Daniel P. Berrangé <berrange@redhat.com>
> wrote:
> 
> > On Fri, Feb 23, 2018 at 01:11:46PM +1300, Michael Clark wrote:
> > > QEMU RISC-V Emulation Support (RV64GC, RV32GC)
> > >
> > > This is hopefully the "fix remaining issues in-tree" release.
> >
> > This code seems to be a mixture of LGPLv2+ and MIT licensed code. The
> > preferred license for QEMU contributions is GPLv2+. Is there a reason
> > you need to diverge from this or can it be changed to be all GPLv2+ ?

Regards,
Daniel
-- 
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  reply	other threads:[~2018-02-26 10:47 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-23  0:11 [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 01/23] RISC-V Maintainers Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 02/23] RISC-V ELF Machine Definition Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 03/23] RISC-V CPU Core Definition Michael Clark
2018-02-26 15:52   ` Igor Mammedov
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 04/23] RISC-V Disassembler Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 05/23] RISC-V CPU Helpers Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 06/23] RISC-V FPU Support Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 07/23] RISC-V GDB Stub Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 08/23] RISC-V TCG Code Generation Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 09/23] RISC-V Physical Memory Protection Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 10/23] RISC-V Linux User Emulation Michael Clark
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 11/23] Add symbol table callback function interface to load_elf Michael Clark
2018-02-23 21:19   ` Richard Henderson
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 12/23] RISC-V HTIF Console Michael Clark
2018-02-23 21:24   ` Richard Henderson
2018-02-23  0:11 ` [Qemu-devel] [PATCH v6 13/23] RISC-V HART Array Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 14/23] SiFive RISC-V CLINT Block Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 15/23] SiFive RISC-V PLIC Block Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 16/23] RISC-V Spike Machines Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 17/23] RISC-V VirtIO Machine Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 18/23] SiFive RISC-V UART Device Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 19/23] SiFive RISC-V PRCI Block Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 20/23] SiFive RISC-V Test Finisher Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 21/23] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 22/23] SiFive Freedom U500 " Michael Clark
2018-02-23  0:12 ` [Qemu-devel] [PATCH v6 23/23] RISC-V Build Infrastructure Michael Clark
2018-02-23  0:39 ` [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission no-reply
2018-02-23 10:10 ` Daniel P. Berrangé
2018-02-23 20:05   ` Michael Clark
2018-02-26 10:47     ` Daniel P. Berrangé [this message]
2018-02-26 11:57       ` Peter Maydell
2018-02-26 12:03         ` Daniel P. Berrangé
2018-02-26 12:32           ` Peter Maydell
2018-02-26 13:03             ` Laurent Desnogues
2018-02-23 21:31 ` Richard Henderson
2018-02-23 22:24   ` Michael Clark
2018-02-24 16:18 ` no-reply
2018-02-26 11:30 ` Richard W.M. Jones
2018-02-26 11:56 ` Andreas Schwab

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