From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: [Qemu-devel] [PATCH v4 00/31] Add ARMv8.2 half-precision functions
Date: Tue, 27 Feb 2018 14:38:21 +0000 [thread overview]
Message-ID: <20180227143852.11175-1-alex.bennee@linaro.org> (raw)
A few minor fixes and a chunk of Richard's r-b tags. Now all that is
left is:
patch 0014/arm translate a64 add FP16 FMULX MLS FMLA to simd.patch needs review
Otherwise see comments bellow --- for other changes
Alex Bennée (31):
include/exec/helper-head.h: support f16 in helper calls
target/arm/cpu64: introduce ARM_V8_FP16 feature bit
target/arm/cpu.h: update comment for half-precision values
target/arm/cpu.h: add additional float_status flags
target/arm/helper: pass explicit fpst to set_rmode
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
arm/translate-a64: handle_3same_64 comment fix
arm/translate-a64: initial decode for simd_three_reg_same_fp16
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to
simd_three_reg_same_fp16
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to
simd_three_reg_same_fp16
arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
arm/translate-a64: add FP16 x2 ops for simd_indexed
arm/translate-a64: initial decode for simd_two_reg_misc_fp16
arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
arm/helper.c: re-factor recpe and add recepe_f16
arm/translate-a64: add FP16 FRECPE
arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
arm/helper.c: re-factor rsqrte and add rsqrte_f16
arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
arm/translate-a64: add FP16 FMOV to simd_mod_imm
arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
arm/translate-a64: implement simd_scalar_three_reg_same_fp16
arm/translate-a64: add all single op FP16 to handle_fp_1src_half
include/exec/helper-head.h | 3 +
include/fpu/softfloat.h | 16 +-
target/arm/cpu.h | 34 +-
target/arm/cpu64.c | 1 +
target/arm/helper-a64.c | 269 ++++++++++
target/arm/helper-a64.h | 33 ++
target/arm/helper.c | 479 +++++++++--------
target/arm/helper.h | 14 +-
target/arm/translate-a64.c | 1260 +++++++++++++++++++++++++++++++++++++-------
target/arm/translate.c | 12 +-
10 files changed, 1694 insertions(+), 427 deletions(-)
--
2.15.1
next reply other threads:[~2018-02-27 14:39 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-27 14:38 Alex Bennée [this message]
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 01/31] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 02/31] target/arm/cpu64: introduce ARM_V8_FP16 feature bit Alex Bennée
2018-02-27 18:09 ` Peter Maydell
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 03/31] target/arm/cpu.h: update comment for half-precision values Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 04/31] target/arm/cpu.h: add additional float_status flags Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 05/31] target/arm/helper: pass explicit fpst to set_rmode Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 06/31] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 07/31] arm/translate-a64: handle_3same_64 comment fix Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 09/31] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] " Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 11/31] arm/translate-a64: add FP16 FMULA/X/S " Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 12/31] arm/translate-a64: add FP16 FR[ECP/SQRT]S " Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 14/31] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed Alex Bennée
2018-02-27 17:09 ` Richard Henderson
2018-02-27 17:52 ` Alex Bennée
2018-02-27 17:57 ` Peter Maydell
2018-02-27 18:17 ` Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 15/31] arm/translate-a64: add FP16 x2 ops for simd_indexed Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 16/31] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 17/31] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 18/31] arm/translate-a64: add FCVTxx " Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 19/31] arm/translate-a64: add FP16 FCMxx (zero) " Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 20/31] arm/translate-a64: add FP16 SCVTF/UCVFT " Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 21/31] arm/translate-a64: add FP16 FNEG/FABS " Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 22/31] arm/helper.c: re-factor recpe and add recepe_f16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 23/31] arm/translate-a64: add FP16 FRECPE Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 24/31] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 25/31] arm/translate-a64: add FP16 FSQRT " Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 26/31] arm/helper.c: re-factor rsqrte and add rsqrte_f16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 27/31] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 28/31] arm/translate-a64: add FP16 FMOV to simd_mod_imm Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 29/31] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 30/31] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 Alex Bennée
2018-02-27 14:38 ` [Qemu-devel] [PATCH v4 31/31] arm/translate-a64: add all single op FP16 to handle_fp_1src_half Alex Bennée
2018-02-27 15:14 ` [Qemu-devel] [PATCH v4 00/31] Add ARMv8.2 half-precision functions no-reply
2018-02-27 15:14 ` no-reply
2018-02-27 18:11 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2018-02-28 13:32 ` Alex Bennée
2018-02-28 15:02 ` Peter Maydell
2018-02-28 16:58 ` Richard Henderson
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