[Qemu-devel] [RISU 0/3] ARM additions for v8.1-simd and v8.3-compnum

[Qemu-devel] [RISU 0/3] ARM additions for v8.1-simd and v8.3-compnum

[Richard Henderson]

I've rebased these onto master.  There don't seem to be any
consistent examples of how extensions are to be named in this
new group-enabled world, but it's my opinion that the bike
shed should be green.

Since fp16 support is not yet present on the AArch32 side,
I have disabled generation of those instructions here.


r~


Richard Henderson (3):
  Add aa64 sqrdml[as]h
  Add aa64 fcadd + fcmla
  Add arm and thumb vqrdml[as]h, vcadd, vcmla

 aarch64.risu | 37 +++++++++++++++++++++++++++++++++++++
 arm.risu     | 25 +++++++++++++++++++++++++
 thumb.risu   | 25 +++++++++++++++++++++++++
 3 files changed, 87 insertions(+)

-- 
2.14.3

[Qemu-devel] [RISU 1/3] Add aa64 sqrdml[as]h

[Richard Henderson]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 aarch64.risu | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/aarch64.risu b/aarch64.risu
index 02e9183..c1a29f6 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2932,6 +2932,30 @@ FCVTZUsi A64_V sf:1 0011110 type:2 1 11 001 000000 rn:5 rd:5 \
 # UnallocatedEncoding: type >= 2
 FCVTZUsi_RES A64_V sf:1 0011110 1 type:1 1 11 001 000000 rn:5 rd:5
 
+#
+# AdvSIMD v8.1 extensions
+#
+
+@v8_1_simd
+
+# SQRDMLAH (vector, scalar)
+SQRDMLAHvs  A64_V81  01111110 size:2 0 rm:5 100001 rn:5 rd:5
+# SQRDMLAH (vector, vector)
+SQRDMLAHv   A64_V81  0 q:1 101110 size:2 0 rm:5 100001 rn:5 rd:5
+# SQRDMLAH (element, scalar)
+SQRDMLAHse  A64_V81  01111111 size:2 l:1 m:1 rm:4 1101 h:1 0 rn:5 rd:5
+# SQRDMLAH (element, vector)
+SQRDMLAHve  A64_V81  0 q:1 101111 size:2 l:1 m:1 rm:4 1101 h:1 0 rn:5 rd:5
+
+# SQRDMLSH (vector, scalar)
+SQRDMLSHvs  A64_V81  01111110 size:2 0 rm:5 100011 rn:5 rd:5
+# SQRDMLSH (vector, vector)
+SQRDMLSHv   A64_V81  0 q:1 101110 size:2 0 rm:5 100011 rn:5 rd:5
+# SQRDMLSH (element, scalar)
+SQRDMLSHse  A64_V81  01111111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5
+# SQRDMLSH (element, vector)
+SQRDMLSHve  A64_V81  0 q:1 101111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5
+
 @
 # End of:
 # Data processing - SIMD and floating point
-- 
2.14.3

[Qemu-devel] [PATCH] decodetree: Propagate return value from translate subroutines

[Richard Henderson]

Allow the translate subroutines to return false for invalid insns.

At present we can of course invoke an invalid insn exception from within
the translate subroutine, but in the short term this consolidates code.
In the long term it would allow the decodetree language to support
overlapping patterns for ISA extensions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---

Since this makes an ABI change to the translate functions called by the
decode function, let's make it now before there are any in-tree users.

My SVE branch over-decodes in quite a lot of cases -- e.g. things like
the 2-bit size field must be 1-3 for fp operands, and so size==0 is
unallocated.  Returning false for these cases allows the actual call
to unallocated_encoding to be done in one place instead of hundreds.

Longer term, I'm thinking of how to handle decode of overlapping ISA
extensions.  One could allow (specific) overlapping patterns and
prioritize them in some way (e.g. first in file is first matched).
My thought is that trans_insn_a would check a cpu feature bit and
return false if not enabled.  Then trans_insn_b would be given its
chance to handle the insn.


r~
---
 scripts/decodetree.py | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 6a33f8f8dd..41301c84aa 100755
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -461,7 +461,7 @@ class Pattern(General):
         global translate_prefix
         output('typedef ', self.base.base.struct_name(),
                ' arg_', self.name, ';\n')
-        output(translate_scope, 'void ', translate_prefix, '_', self.name,
+        output(translate_scope, 'bool ', translate_prefix, '_', self.name,
                '(DisasContext *ctx, arg_', self.name,
                ' *a, ', insntype, ' insn);\n')
 
@@ -474,9 +474,8 @@ class Pattern(General):
             output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n')
         for n, f in self.fields.items():
             output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n')
-        output(ind, translate_prefix, '_', self.name,
+        output(ind, 'return ', translate_prefix, '_', self.name,
                '(ctx, &u.f_', arg, ', insn);\n')
-        output(ind, 'return true;\n')
 # end Pattern
 
 
-- 
2.14.3

Re: [Qemu-devel] [PATCH] decodetree: Propagate return value from translate subroutines

[Peter Maydell]

On 28 February 2018 at 16:48, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Allow the translate subroutines to return false for invalid insns.
>
> At present we can of course invoke an invalid insn exception from within
> the translate subroutine, but in the short term this consolidates code.
> In the long term it would allow the decodetree language to support
> overlapping patterns for ISA extensions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>
> Since this makes an ABI change to the translate functions called by the
> decode function, let's make it now before there are any in-tree users.
>
> My SVE branch over-decodes in quite a lot of cases -- e.g. things like
> the 2-bit size field must be 1-3 for fp operands, and so size==0 is
> unallocated.  Returning false for these cases allows the actual call
> to unallocated_encoding to be done in one place instead of hundreds.
>
> Longer term, I'm thinking of how to handle decode of overlapping ISA
> extensions.  One could allow (specific) overlapping patterns and
> prioritize them in some way (e.g. first in file is first matched).
> My thought is that trans_insn_a would check a cpu feature bit and
> return false if not enabled.  Then trans_insn_b would be given its
> chance to handle the insn.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

I'll put this into target-arm.next, unless you'd prefer it to go
in via some other route.

thanks
-- PMM

Re: [Qemu-devel] [PATCH] decodetree: Propagate return value from translate subroutines

[Richard Henderson]

On 03/01/2018 03:59 AM, Peter Maydell wrote:
> On 28 February 2018 at 16:48, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> Allow the translate subroutines to return false for invalid insns.
>>
>> At present we can of course invoke an invalid insn exception from within
>> the translate subroutine, but in the short term this consolidates code.
>> In the long term it would allow the decodetree language to support
>> overlapping patterns for ISA extensions.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>
>> Since this makes an ABI change to the translate functions called by the
>> decode function, let's make it now before there are any in-tree users.
>>
>> My SVE branch over-decodes in quite a lot of cases -- e.g. things like
>> the 2-bit size field must be 1-3 for fp operands, and so size==0 is
>> unallocated.  Returning false for these cases allows the actual call
>> to unallocated_encoding to be done in one place instead of hundreds.
>>
>> Longer term, I'm thinking of how to handle decode of overlapping ISA
>> extensions.  One could allow (specific) overlapping patterns and
>> prioritize them in some way (e.g. first in file is first matched).
>> My thought is that trans_insn_a would check a cpu feature bit and
>> return false if not enabled.  Then trans_insn_b would be given its
>> chance to handle the insn.
> 
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> 
> I'll put this into target-arm.next, unless you'd prefer it to go
> in via some other route.

That's fine.  Thanks!


r~

[Qemu-devel] [RISU 2/3] Add aa64 fcadd + fcmla

[Richard Henderson]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 aarch64.risu | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/aarch64.risu b/aarch64.risu
index c1a29f6..a5c92e9 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2956,6 +2956,19 @@ SQRDMLSHse  A64_V81  01111111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5
 # SQRDMLSH (element, vector)
 SQRDMLSHve  A64_V81  0 q:1 101111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5
 
+#
+# AdvSIMD v8.3 extensions
+#
+@v8_3_compnum
+
+# FCADD (three registers of the same type)
+FCADD      A64_V83  0 q:1 101110 size:2 0 rm:5 111 rot:1 01 rn:5 rd:5
+
+# FCMLA (three registers of the same type)
+FCMLA      A64_V83  0 q:1 101110 size:2 0 rm:5 110 rot:2 1 rn:5 rd:5
+# FCMLA (vector x indexed element)
+FCMLA_idx  A64_V83  0 q:1 101111 size:2 l:1 m:1 rm:4 0 rot:2 1 h:1 0 rn:5 rd:5
+
 @
 # End of:
 # Data processing - SIMD and floating point
-- 
2.14.3

[Qemu-devel] [RISU 3/3] Add arm and thumb vqrdml[as]h, vcadd, vcmla

[Richard Henderson]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 arm.risu   | 25 +++++++++++++++++++++++++
 thumb.risu | 25 +++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/arm.risu b/arm.risu
index 13ea019..af73345 100644
--- a/arm.risu
+++ b/arm.risu
@@ -831,3 +831,28 @@ VCVT_rm_neon A1 1111 00111 d 11 size:2 11 vd:4 00 rm:2 op q m 0 vm:4
 # Note that sz == 0b11 is UNPREDICTABLE (either UNDEF, NOP or as if == 0b10)
 # as is cond != 1110 (either UNDEF, NOP, cond-exec or unconditional exec)
 CRC32 A1 1110 00010 sz:2 0 rn:4 rd:4 00 c 0 0100 rm:4 !constraints { $sz != 3; }
+
+#
+# ARMv8.1 extensions
+#
+@v8_1_simd
+
+VQRDMLAH    A1 111100110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4
+VQRDMLAH_s  A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4
+
+VQRDMLSH    A1 111100110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4
+VQRDMLSH_s  A1 1111001 q:1 1 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4
+
+#
+# ARMv8.3 extensions
+#
+@v8_3_compnum
+
+# Disable fp16 until qemu supports it.
+VCADD       A1 1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
+!constraints { $s != 0; }
+
+VCMLA       A1 1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
+!constraints { $s != 0; }
+VCMLA_s     A1 11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
+!constraints { $s != 0; }
diff --git a/thumb.risu b/thumb.risu
index bf7556b..b8afa59 100644
--- a/thumb.risu
+++ b/thumb.risu
@@ -437,3 +437,28 @@ STR T2 11111 000 0100 rn:4 rt:4 000000 imm:2 rm:4 \
 
 # V8 only instructions
 CRC32 T1 111 1101 011 0 c rn:4 1111 rd:4 10 sz:2 rm:4 !constraints { $sz != 3; }
+
+#
+# ARMv8.1 extensions
+#
+@v8_1_simd
+
+VQRDMLAH    T1  111111110 d:1 size:2 vn:4 vd:4 1011 n:1 q:1 m:1 1 vm:4
+VQRDMLAH_s  T1  111 q:1 11111 d:1 size:2 vn:4 vd:4 1110 n:1 1 m:1 0 vm:4
+
+VQRDMLSH    T1  111111110 d:1 size:2 vn:4 vd:4 1100 n:1 q:1 m:1 1 vm:4
+VQRDMLSH_s  T1  111 q:1 11111 d:1 size:2 vn:4 vd:4 1111 n:1 1 m:1 0 vm:4
+
+#
+# ARMv8.3 extensions
+#
+@v8_3_compnum
+
+# Disable fp16 until qemu supports it.
+VCADD       T1  1111110 rot:1 1 d:1 0 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
+!constraints { $s != 0; }
+
+VCMLA       T1  1111110 rot:2 d:1 1 s:1 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
+!constraints { $s != 0; }
+VCMLA_s     T1  11111110 s:1 d:1 rot:2 vn:4 vd:4 1000 n:1 q:1 m:1 0 vm:4 \
+!constraints { $s != 0; }
-- 
2.14.3

Re: [Qemu-devel] [Qemu-arm] [RISU 0/3] ARM additions for v8.1-simd and v8.3-compnum

[Peter Maydell]

On 28 February 2018 at 16:48, Richard Henderson
<richard.henderson@linaro.org> wrote:
> I've rebased these onto master.  There don't seem to be any
> consistent examples of how extensions are to be named in this
> new group-enabled world, but it's my opinion that the bike
> shed should be green.
>
> Since fp16 support is not yet present on the AArch32 side,
> I have disabled generation of those instructions here.

Applied to risu master, thanks.

-- PMM