From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [Qemu-devel] [RISU 2/3] Add aa64 fcadd + fcmla
Date: Wed, 28 Feb 2018 08:48:15 -0800 [thread overview]
Message-ID: <20180228164816.24110-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180228164816.24110-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
aarch64.risu | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/aarch64.risu b/aarch64.risu
index c1a29f6..a5c92e9 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2956,6 +2956,19 @@ SQRDMLSHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5
# SQRDMLSH (element, vector)
SQRDMLSHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5
+#
+# AdvSIMD v8.3 extensions
+#
+@v8_3_compnum
+
+# FCADD (three registers of the same type)
+FCADD A64_V83 0 q:1 101110 size:2 0 rm:5 111 rot:1 01 rn:5 rd:5
+
+# FCMLA (three registers of the same type)
+FCMLA A64_V83 0 q:1 101110 size:2 0 rm:5 110 rot:2 1 rn:5 rd:5
+# FCMLA (vector x indexed element)
+FCMLA_idx A64_V83 0 q:1 101111 size:2 l:1 m:1 rm:4 0 rot:2 1 h:1 0 rn:5 rd:5
+
@
# End of:
# Data processing - SIMD and floating point
--
2.14.3
next prev parent reply other threads:[~2018-02-28 16:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-28 16:48 [Qemu-devel] [RISU 0/3] ARM additions for v8.1-simd and v8.3-compnum Richard Henderson
2018-02-28 16:48 ` [Qemu-devel] [RISU 1/3] Add aa64 sqrdml[as]h Richard Henderson
2018-02-28 16:48 ` [Qemu-devel] [PATCH] decodetree: Propagate return value from translate subroutines Richard Henderson
2018-03-01 11:59 ` Peter Maydell
2018-03-01 17:01 ` Richard Henderson
2018-02-28 16:48 ` Richard Henderson [this message]
2018-02-28 16:48 ` [Qemu-devel] [RISU 3/3] Add arm and thumb vqrdml[as]h, vcadd, vcmla Richard Henderson
2018-03-01 11:50 ` [Qemu-devel] [Qemu-arm] [RISU 0/3] ARM additions for v8.1-simd and v8.3-compnum Peter Maydell
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