* [Qemu-devel] [PATCH v3 01/16] target/arm: Add ARM_FEATURE_V8_RDM
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 02/16] target/arm: Refactor disas_simd_indexed decode Richard Henderson
` (14 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Not enabled anywhere yet.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 1 +
linux-user/elfload.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2b9740878b..7c8e87544a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1427,6 +1427,7 @@ enum arm_features {
ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */
ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
+ ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */
ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
};
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 8bb9a2c3e8..63cadae1b4 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -551,6 +551,7 @@ static uint32_t get_elf_hwcap(void)
GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3);
GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4);
GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512);
+ GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM);
#undef GET_FEATURE
return hwcaps;
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 02/16] target/arm: Refactor disas_simd_indexed decode
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 01/16] target/arm: Add ARM_FEATURE_V8_RDM Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-03-01 13:12 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 03/16] target/arm: Refactor disas_simd_indexed size checks Richard Henderson
` (13 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Include the U bit in the switches rather than testing separately.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 129 +++++++++++++++++++++------------------------
1 file changed, 61 insertions(+), 68 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 32811dc8b0..fc928b61f6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11787,49 +11787,39 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
int index;
TCGv_ptr fpst;
- switch (opcode) {
- case 0x0: /* MLA */
- case 0x4: /* MLS */
- if (!u || is_scalar) {
+ switch (16 * u + opcode) {
+ case 0x08: /* MUL */
+ case 0x10: /* MLA */
+ case 0x14: /* MLS */
+ if (is_scalar) {
unallocated_encoding(s);
return;
}
break;
- case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
- case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
- case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
+ case 0x02: /* SMLAL, SMLAL2 */
+ case 0x12: /* UMLAL, UMLAL2 */
+ case 0x06: /* SMLSL, SMLSL2 */
+ case 0x16: /* UMLSL, UMLSL2 */
+ case 0x0a: /* SMULL, SMULL2 */
+ case 0x1a: /* UMULL, UMULL2 */
if (is_scalar) {
unallocated_encoding(s);
return;
}
is_long = true;
break;
- case 0x3: /* SQDMLAL, SQDMLAL2 */
- case 0x7: /* SQDMLSL, SQDMLSL2 */
- case 0xb: /* SQDMULL, SQDMULL2 */
+ case 0x03: /* SQDMLAL, SQDMLAL2 */
+ case 0x07: /* SQDMLSL, SQDMLSL2 */
+ case 0x0b: /* SQDMULL, SQDMULL2 */
is_long = true;
- /* fall through */
- case 0xc: /* SQDMULH */
- case 0xd: /* SQRDMULH */
- if (u) {
- unallocated_encoding(s);
- return;
- }
break;
- case 0x8: /* MUL */
- if (u || is_scalar) {
- unallocated_encoding(s);
- return;
- }
+ case 0x0c: /* SQDMULH */
+ case 0x0d: /* SQRDMULH */
break;
- case 0x1: /* FMLA */
- case 0x5: /* FMLS */
- if (u) {
- unallocated_encoding(s);
- return;
- }
- /* fall through */
- case 0x9: /* FMUL, FMULX */
+ case 0x01: /* FMLA */
+ case 0x05: /* FMLS */
+ case 0x09: /* FMUL */
+ case 0x19: /* FMULX */
if (size == 1) {
unallocated_encoding(s);
return;
@@ -11909,21 +11899,20 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
read_vec_element(s, tcg_op, rn, pass, MO_64);
- switch (opcode) {
- case 0x5: /* FMLS */
+ switch (16 * u + opcode) {
+ case 0x05: /* FMLS */
/* As usual for ARM, separate negation for fused multiply-add */
gen_helper_vfp_negd(tcg_op, tcg_op);
/* fall through */
- case 0x1: /* FMLA */
+ case 0x01: /* FMLA */
read_vec_element(s, tcg_res, rd, pass, MO_64);
gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
break;
- case 0x9: /* FMUL, FMULX */
- if (u) {
- gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst);
- } else {
- gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst);
- }
+ case 0x09: /* FMUL */
+ gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst);
+ break;
+ case 0x19: /* FMULX */
+ gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst);
break;
default:
g_assert_not_reached();
@@ -11966,10 +11955,10 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
- switch (opcode) {
- case 0x0: /* MLA */
- case 0x4: /* MLS */
- case 0x8: /* MUL */
+ switch (16 * u + opcode) {
+ case 0x08: /* MUL */
+ case 0x10: /* MLA */
+ case 0x14: /* MLS */
{
static NeonGenTwoOpFn * const fns[2][2] = {
{ gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
@@ -11991,8 +11980,8 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
genfn(tcg_res, tcg_op, tcg_res);
break;
}
- case 0x5: /* FMLS */
- case 0x1: /* FMLA */
+ case 0x05: /* FMLS */
+ case 0x01: /* FMLA */
read_vec_element_i32(s, tcg_res, rd, pass,
is_scalar ? size : MO_32);
switch (size) {
@@ -12023,39 +12012,43 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
g_assert_not_reached();
}
break;
- case 0x9: /* FMUL, FMULX */
+ case 0x09: /* FMUL */
switch (size) {
case 1:
- if (u) {
- if (is_scalar) {
- gen_helper_advsimd_mulxh(tcg_res, tcg_op,
- tcg_idx, fpst);
- } else {
- gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
- tcg_idx, fpst);
- }
+ if (is_scalar) {
+ gen_helper_advsimd_mulh(tcg_res, tcg_op,
+ tcg_idx, fpst);
} else {
- if (is_scalar) {
- gen_helper_advsimd_mulh(tcg_res, tcg_op,
- tcg_idx, fpst);
- } else {
- gen_helper_advsimd_mul2h(tcg_res, tcg_op,
- tcg_idx, fpst);
- }
+ gen_helper_advsimd_mul2h(tcg_res, tcg_op,
+ tcg_idx, fpst);
}
break;
case 2:
- if (u) {
- gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
- } else {
- gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
- }
+ gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
break;
default:
g_assert_not_reached();
}
break;
- case 0xc: /* SQDMULH */
+ case 0x19: /* FMULX */
+ switch (size) {
+ case 1:
+ if (is_scalar) {
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op,
+ tcg_idx, fpst);
+ } else {
+ gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
+ tcg_idx, fpst);
+ }
+ break;
+ case 2:
+ gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+ case 0x0c: /* SQDMULH */
if (size == 1) {
gen_helper_neon_qdmulh_s16(tcg_res, cpu_env,
tcg_op, tcg_idx);
@@ -12064,7 +12057,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
tcg_op, tcg_idx);
}
break;
- case 0xd: /* SQRDMULH */
+ case 0x0d: /* SQRDMULH */
if (size == 1) {
gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
tcg_op, tcg_idx);
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 03/16] target/arm: Refactor disas_simd_indexed size checks
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 01/16] target/arm: Add ARM_FEATURE_V8_RDM Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 02/16] target/arm: Refactor disas_simd_indexed decode Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-03-01 13:19 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 04/16] target/arm: Decode aa64 armv8.1 scalar three same extra Richard Henderson
` (12 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
The integer size check was already outside of the opcode switch;
move the floating-point size check outside as well. Unify the
size vs index adjustment between fp and integer paths.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 65 +++++++++++++++++++++++-----------------------
1 file changed, 32 insertions(+), 33 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fc928b61f6..cbb4510e3a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11820,10 +11820,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
case 0x05: /* FMLS */
case 0x09: /* FMUL */
case 0x19: /* FMULX */
- if (size == 1) {
- unallocated_encoding(s);
- return;
- }
is_fp = true;
break;
default:
@@ -11834,45 +11830,48 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
if (is_fp) {
/* convert insn encoded size to TCGMemOp size */
switch (size) {
- case 2: /* single precision */
- size = MO_32;
- index = h << 1 | l;
- rm |= (m << 4);
- break;
- case 3: /* double precision */
- size = MO_64;
- if (l || !is_q) {
+ case 0: /* half-precision */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s);
return;
}
- index = h;
- rm |= (m << 4);
- break;
- case 0: /* half precision */
size = MO_16;
- index = h << 2 | l << 1 | m;
- is_fp16 = true;
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
- break;
- }
- /* fallthru */
- default: /* unallocated */
- unallocated_encoding(s);
- return;
- }
- } else {
- switch (size) {
- case 1:
- index = h << 2 | l << 1 | m;
break;
- case 2:
- index = h << 1 | l;
- rm |= (m << 4);
+ case MO_32: /* single precision */
+ case MO_64: /* double precision */
break;
default:
unallocated_encoding(s);
return;
}
+ } else {
+ switch (size) {
+ case MO_8:
+ case MO_64:
+ unallocated_encoding(s);
+ return;
+ }
+ }
+
+ /* Given TCGMemOp size, adjust register and indexing. */
+ switch (size) {
+ case MO_16:
+ index = h << 2 | l << 1 | m;
+ break;
+ case MO_32:
+ index = h << 1 | l;
+ rm |= m << 4;
+ break;
+ case MO_64:
+ if (l || !is_q) {
+ unallocated_encoding(s);
+ return;
+ }
+ index = h;
+ rm |= m << 4;
+ break;
+ default:
+ g_assert_not_reached();
}
if (!fp_access_check(s)) {
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 04/16] target/arm: Decode aa64 armv8.1 scalar three same extra
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (2 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 03/16] target/arm: Refactor disas_simd_indexed size checks Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 05/16] target/arm: Decode aa64 armv8.1 " Richard Henderson
` (11 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 4 ++
target/arm/translate-a64.c | 84 ++++++++++++++++++++++++++++++++++
target/arm/vec_helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++
target/arm/Makefile.objs | 2 +-
4 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 target/arm/vec_helper.c
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 6dd8504ec3..2075c143d7 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -365,8 +365,12 @@ DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32)
+DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32)
+DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32)
DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32)
DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32)
+DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32)
+DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32)
DEF_HELPER_1(neon_narrow_u8, i32, i64)
DEF_HELPER_1(neon_narrow_u16, i32, i64)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index cbb4510e3a..746ab0e63a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7971,6 +7971,89 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
tcg_temp_free_ptr(fpst);
}
+/* AdvSIMD scalar three same extra
+ * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
+ * +-----+---+-----------+------+---+------+---+--------+---+----+----+
+ * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
+ * +-----+---+-----------+------+---+------+---+--------+---+----+----+
+ */
+static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
+ uint32_t insn)
+{
+ int rd = extract32(insn, 0, 5);
+ int rn = extract32(insn, 5, 5);
+ int opcode = extract32(insn, 11, 4);
+ int rm = extract32(insn, 16, 5);
+ int size = extract32(insn, 22, 2);
+ bool u = extract32(insn, 29, 1);
+ TCGv_i32 ele1, ele2, ele3;
+ TCGv_i64 res;
+ int feature;
+
+ switch (u * 16 + opcode) {
+ case 0x10: /* SQRDMLAH (vector) */
+ case 0x11: /* SQRDMLSH (vector) */
+ if (size != 1 && size != 2) {
+ unallocated_encoding(s);
+ return;
+ }
+ feature = ARM_FEATURE_V8_RDM;
+ break;
+ default:
+ unallocated_encoding(s);
+ return;
+ }
+ if (!arm_dc_feature(s, feature)) {
+ unallocated_encoding(s);
+ return;
+ }
+ if (!fp_access_check(s)) {
+ return;
+ }
+
+ /* Do a single operation on the lowest element in the vector.
+ * We use the standard Neon helpers and rely on 0 OP 0 == 0
+ * with no side effects for all these operations.
+ * OPTME: special-purpose helpers would avoid doing some
+ * unnecessary work in the helper for the 16 bit cases.
+ */
+ ele1 = tcg_temp_new_i32();
+ ele2 = tcg_temp_new_i32();
+ ele3 = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, ele1, rn, 0, size);
+ read_vec_element_i32(s, ele2, rm, 0, size);
+ read_vec_element_i32(s, ele3, rd, 0, size);
+
+ switch (opcode) {
+ case 0x0: /* SQRDMLAH */
+ if (size == 1) {
+ gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3);
+ } else {
+ gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3);
+ }
+ break;
+ case 0x1: /* SQRDMLSH */
+ if (size == 1) {
+ gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3);
+ } else {
+ gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_i32(ele1);
+ tcg_temp_free_i32(ele2);
+
+ res = tcg_temp_new_i64();
+ tcg_gen_extu_i32_i64(res, ele3);
+ tcg_temp_free_i32(ele3);
+
+ write_fp_dreg(s, rd, res);
+ tcg_temp_free_i64(res);
+}
+
static void handle_2misc_64(DisasContext *s, int opcode, bool u,
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
@@ -12798,6 +12881,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
{ 0x2e000000, 0xbf208400, disas_simd_ext },
{ 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same },
+ { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra },
{ 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
{ 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
new file mode 100644
index 0000000000..9febdff69c
--- /dev/null
+++ b/target/arm/vec_helper.c
@@ -0,0 +1,109 @@
+/*
+ * ARM AdvSIMD / SVE Vector Operations
+ *
+ * Copyright (c) 2018 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "tcg/tcg-gvec-desc.h"
+
+
+#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
+
+/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
+static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1,
+ int16_t src2, int16_t src3)
+{
+ /* Simplify:
+ * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
+ * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
+ */
+ int32_t ret = (int32_t)src1 * src2;
+ ret = ((int32_t)src3 << 15) + ret + (1 << 14);
+ ret >>= 15;
+ if (ret != (int16_t)ret) {
+ SET_QC();
+ ret = (ret < 0 ? -0x8000 : 0x7fff);
+ }
+ return ret;
+}
+
+uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
+ uint32_t src2, uint32_t src3)
+{
+ uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3);
+ uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
+ return deposit32(e1, 16, 16, e2);
+}
+
+/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
+static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1,
+ int16_t src2, int16_t src3)
+{
+ /* Similarly, using subtraction:
+ * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
+ * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
+ */
+ int32_t ret = (int32_t)src1 * src2;
+ ret = ((int32_t)src3 << 15) - ret + (1 << 14);
+ ret >>= 15;
+ if (ret != (int16_t)ret) {
+ SET_QC();
+ ret = (ret < 0 ? -0x8000 : 0x7fff);
+ }
+ return ret;
+}
+
+uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
+ uint32_t src2, uint32_t src3)
+{
+ uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3);
+ uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
+ return deposit32(e1, 16, 16, e2);
+}
+
+/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
+uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
+ int32_t src2, int32_t src3)
+{
+ /* Simplify similarly to int_qrdmlah_s16 above. */
+ int64_t ret = (int64_t)src1 * src2;
+ ret = ((int64_t)src3 << 31) + ret + (1 << 30);
+ ret >>= 31;
+ if (ret != (int32_t)ret) {
+ SET_QC();
+ ret = (ret < 0 ? INT32_MIN : INT32_MAX);
+ }
+ return ret;
+}
+
+/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
+uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
+ int32_t src2, int32_t src3)
+{
+ /* Simplify similarly to int_qrdmlsh_s16 above. */
+ int64_t ret = (int64_t)src1 * src2;
+ ret = ((int64_t)src3 << 31) - ret + (1 << 30);
+ ret >>= 31;
+ if (ret != (int32_t)ret) {
+ SET_QC();
+ ret = (ret < 0 ? INT32_MIN : INT32_MAX);
+ }
+ return ret;
+}
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 847fb52ee0..1297bead5f 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -5,7 +5,7 @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-y += neon_helper.o iwmmxt_helper.o
+obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o
obj-y += gdbstub.o
obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
obj-y += crypto_helper.o
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 05/16] target/arm: Decode aa64 armv8.1 three same extra
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (3 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 04/16] target/arm: Decode aa64 armv8.1 scalar three same extra Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 06/16] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element Richard Henderson
` (10 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 9 +++++
target/arm/translate-a64.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++
target/arm/vec_helper.c | 74 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 166 insertions(+)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 2075c143d7..7f0d3b2d84 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -569,6 +569,15 @@ DEF_HELPER_2(dc_zva, void, env, i64)
DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#endif
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 746ab0e63a..ae16313eb0 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -701,6 +701,18 @@ static void gen_gvec_op3(DisasContext *s, bool is_q, int rd,
vec_full_reg_size(s), gvec_op);
}
+/* Expand a 3-operand + env pointer operation using
+ * an out-of-line helper.
+ */
+static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd,
+ int rn, int rm, gen_helper_gvec_3_ptr *fn)
+{
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), cpu_env,
+ is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
+}
+
/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
* than the 32 bit equivalent.
*/
@@ -10789,6 +10801,76 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
clear_vec_high(s, is_q, rd);
}
+/* AdvSIMD three same extra
+ * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
+ * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
+ * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
+ * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
+ */
+static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
+{
+ int rd = extract32(insn, 0, 5);
+ int rn = extract32(insn, 5, 5);
+ int opcode = extract32(insn, 11, 4);
+ int rm = extract32(insn, 16, 5);
+ int size = extract32(insn, 22, 2);
+ bool u = extract32(insn, 29, 1);
+ bool is_q = extract32(insn, 30, 1);
+ int feature;
+
+ switch (u * 16 + opcode) {
+ case 0x10: /* SQRDMLAH (vector) */
+ case 0x11: /* SQRDMLSH (vector) */
+ if (size != 1 && size != 2) {
+ unallocated_encoding(s);
+ return;
+ }
+ feature = ARM_FEATURE_V8_RDM;
+ break;
+ default:
+ unallocated_encoding(s);
+ return;
+ }
+ if (!arm_dc_feature(s, feature)) {
+ unallocated_encoding(s);
+ return;
+ }
+ if (!fp_access_check(s)) {
+ return;
+ }
+
+ switch (opcode) {
+ case 0x0: /* SQRDMLAH (vector) */
+ switch (size) {
+ case 1:
+ gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16);
+ break;
+ case 2:
+ gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return;
+
+ case 0x1: /* SQRDMLSH (vector) */
+ switch (size) {
+ case 1:
+ gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16);
+ break;
+ case 2:
+ gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
int size, int rn, int rd)
{
@@ -12869,6 +12951,7 @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
static const AArch64DecodeTable data_proc_simd[] = {
/* pattern , mask , fn */
{ 0x0e200400, 0x9f200400, disas_simd_three_reg_same },
+ { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra },
{ 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff },
{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
{ 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 9febdff69c..3072df4d77 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -26,6 +26,16 @@
#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
+static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
+{
+ uint64_t *d = vd + opr_sz;
+ uintptr_t i;
+
+ for (i = opr_sz; i < max_sz; i += 8) {
+ *d++ = 0;
+ }
+}
+
/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1,
int16_t src2, int16_t src3)
@@ -52,6 +62,22 @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
return deposit32(e1, 16, 16, e2);
}
+void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
+ void *ve, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ int16_t *d = vd;
+ int16_t *n = vn;
+ int16_t *m = vm;
+ CPUARMState *env = ve;
+ uintptr_t i;
+
+ for (i = 0; i < opr_sz / 2; ++i) {
+ d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1,
int16_t src2, int16_t src3)
@@ -78,6 +104,22 @@ uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
return deposit32(e1, 16, 16, e2);
}
+void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
+ void *ve, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ int16_t *d = vd;
+ int16_t *n = vn;
+ int16_t *m = vm;
+ CPUARMState *env = ve;
+ uintptr_t i;
+
+ for (i = 0; i < opr_sz / 2; ++i) {
+ d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
int32_t src2, int32_t src3)
@@ -93,6 +135,22 @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
return ret;
}
+void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
+ void *ve, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ int32_t *d = vd;
+ int32_t *n = vn;
+ int32_t *m = vm;
+ CPUARMState *env = ve;
+ uintptr_t i;
+
+ for (i = 0; i < opr_sz / 4; ++i) {
+ d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
int32_t src2, int32_t src3)
@@ -107,3 +165,19 @@ uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
}
return ret;
}
+
+void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
+ void *ve, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ int32_t *d = vd;
+ int32_t *n = vn;
+ int32_t *m = vm;
+ CPUARMState *env = ve;
+ uintptr_t i;
+
+ for (i = 0; i < opr_sz / 4; ++i) {
+ d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 06/16] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (4 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 05/16] target/arm: Decode aa64 armv8.1 " Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 07/16] target/arm: Decode aa32 armv8.1 three same Richard Henderson
` (9 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ae16313eb0..e4d2d548ba 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11987,6 +11987,13 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
case 0x19: /* FMULX */
is_fp = true;
break;
+ case 0x1d: /* SQRDMLAH */
+ case 0x1f: /* SQRDMLSH */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
default:
unallocated_encoding(s);
return;
@@ -12230,6 +12237,28 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
tcg_op, tcg_idx);
}
break;
+ case 0x1d: /* SQRDMLAH */
+ read_vec_element_i32(s, tcg_res, rd, pass,
+ is_scalar ? size : MO_32);
+ if (size == 1) {
+ gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
+ } else {
+ gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
+ }
+ break;
+ case 0x1f: /* SQRDMLSH */
+ read_vec_element_i32(s, tcg_res, rd, pass,
+ is_scalar ? size : MO_32);
+ if (size == 1) {
+ gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
+ } else {
+ gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env,
+ tcg_op, tcg_idx, tcg_res);
+ }
+ break;
default:
g_assert_not_reached();
}
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 07/16] target/arm: Decode aa32 armv8.1 three same
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (5 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 06/16] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 08/16] target/arm: Decode aa32 armv8.1 two reg and a scalar Richard Henderson
` (8 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 86 +++++++++++++++++++++++++++++++++++++++-----------
1 file changed, 67 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index aa6dcaa577..05fa6a53f9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -25,6 +25,7 @@
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
+#include "tcg-op-gvec.h"
#include "qemu/log.h"
#include "qemu/bitops.h"
#include "arm_ldst.h"
@@ -5374,9 +5375,9 @@ static void gen_neon_narrow_op(int op, int u, int size,
#define NEON_3R_VPMAX 20
#define NEON_3R_VPMIN 21
#define NEON_3R_VQDMULH_VQRDMULH 22
-#define NEON_3R_VPADD 23
+#define NEON_3R_VPADD_VQRDMLAH 23
#define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */
-#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */
+#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */
#define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
#define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
@@ -5408,9 +5409,9 @@ static const uint8_t neon_3r_sizes[] = {
[NEON_3R_VPMAX] = 0x7,
[NEON_3R_VPMIN] = 0x7,
[NEON_3R_VQDMULH_VQRDMULH] = 0x6,
- [NEON_3R_VPADD] = 0x7,
+ [NEON_3R_VPADD_VQRDMLAH] = 0x7,
[NEON_3R_SHA] = 0xf, /* size field encodes op type */
- [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */
+ [NEON_3R_VFM_VQRDMLSH] = 0x7, /* For VFM, size bit 1 encodes op */
[NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
[NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
[NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
@@ -5589,6 +5590,22 @@ static const uint8_t neon_2rm_sizes[] = {
[NEON_2RM_VCVT_UF] = 0x4,
};
+
+/* Expand v8.1 simd helper. */
+static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
+ int q, int rd, int rn, int rm)
+{
+ if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
+ int opr_sz = (1 + q) * 8;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
+ vfp_reg_offset(1, rn),
+ vfp_reg_offset(1, rm), cpu_env,
+ opr_sz, opr_sz, 0, fn);
+ return 0;
+ }
+ return 1;
+}
+
/* Translate a NEON data processing instruction. Return nonzero if the
instruction is invalid.
We process data in a mixture of 32-bit and 64-bit chunks.
@@ -5641,12 +5658,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
if (q && ((rd | rn | rm) & 1)) {
return 1;
}
- /*
- * The SHA-1/SHA-256 3-register instructions require special treatment
- * here, as their size field is overloaded as an op type selector, and
- * they all consume their input in a single pass.
- */
- if (op == NEON_3R_SHA) {
+ switch (op) {
+ case NEON_3R_SHA:
+ /* The SHA-1/SHA-256 3-register instructions require special
+ * treatment here, as their size field is overloaded as an
+ * op type selector, and they all consume their input in a
+ * single pass.
+ */
if (!q) {
return 1;
}
@@ -5683,6 +5701,40 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_ptr(ptr2);
tcg_temp_free_ptr(ptr3);
return 0;
+
+ case NEON_3R_VPADD_VQRDMLAH:
+ if (!u) {
+ break; /* VPADD */
+ }
+ /* VQRDMLAH */
+ switch (size) {
+ case 1:
+ return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16,
+ q, rd, rn, rm);
+ case 2:
+ return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32,
+ q, rd, rn, rm);
+ }
+ return 1;
+
+ case NEON_3R_VFM_VQRDMLSH:
+ if (!u) {
+ /* VFM, VFMS */
+ if (size == 1) {
+ return 1;
+ }
+ break;
+ }
+ /* VQRDMLSH */
+ switch (size) {
+ case 1:
+ return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16,
+ q, rd, rn, rm);
+ case 2:
+ return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32,
+ q, rd, rn, rm);
+ }
+ return 1;
}
if (size == 3 && op != NEON_3R_LOGIC) {
/* 64-bit element instructions. */
@@ -5768,11 +5820,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
rm = rtmp;
}
break;
- case NEON_3R_VPADD:
- if (u) {
- return 1;
- }
- /* Fall through */
+ case NEON_3R_VPADD_VQRDMLAH:
case NEON_3R_VPMAX:
case NEON_3R_VPMIN:
pairwise = 1;
@@ -5806,8 +5854,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
return 1;
}
break;
- case NEON_3R_VFM:
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) {
+ case NEON_3R_VFM_VQRDMLSH:
+ if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
return 1;
}
break;
@@ -6004,7 +6052,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
}
break;
- case NEON_3R_VPADD:
+ case NEON_3R_VPADD_VQRDMLAH:
switch (size) {
case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
@@ -6103,7 +6151,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
}
break;
- case NEON_3R_VFM:
+ case NEON_3R_VFM_VQRDMLSH:
{
/* VFMA, VFMS: fused multiply-add */
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 08/16] target/arm: Decode aa32 armv8.1 two reg and a scalar
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (6 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 07/16] target/arm: Decode aa32 armv8.1 three same Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 09/16] target/arm: Enable ARM_FEATURE_V8_RDM Richard Henderson
` (7 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 46 ++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 42 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 05fa6a53f9..9169b6b367 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -76,6 +76,10 @@ static const char *regnames[] =
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
+/* Function prototypes for gen_ functions calling Neon helpers. */
+typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
+ TCGv_i32, TCGv_i32);
+
/* initialize TCG globals. */
void arm_translate_init(void)
{
@@ -6985,11 +6989,45 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
neon_store_reg64(cpu_V0, rd + pass);
}
-
-
break;
- default: /* 14 and 15 are RESERVED */
- return 1;
+ case 14: /* VQRDMLAH scalar */
+ case 15: /* VQRDMLSH scalar */
+ {
+ NeonGenThreeOpEnvFn *fn;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
+ return 1;
+ }
+ if (u && ((rd | rn) & 1)) {
+ return 1;
+ }
+ if (op == 14) {
+ if (size == 1) {
+ fn = gen_helper_neon_qrdmlah_s16;
+ } else {
+ fn = gen_helper_neon_qrdmlah_s32;
+ }
+ } else {
+ if (size == 1) {
+ fn = gen_helper_neon_qrdmlsh_s16;
+ } else {
+ fn = gen_helper_neon_qrdmlsh_s32;
+ }
+ }
+
+ tmp2 = neon_get_scalar(size, rm);
+ for (pass = 0; pass < (u ? 4 : 2); pass++) {
+ tmp = neon_load_reg(rn, pass);
+ tmp3 = neon_load_reg(rd, pass);
+ fn(tmp, cpu_env, tmp, tmp2, tmp3);
+ tcg_temp_free_i32(tmp3);
+ neon_store_reg(rd, pass, tmp);
+ }
+ tcg_temp_free_i32(tmp2);
+ }
+ break;
+ default:
+ g_assert_not_reached();
}
}
} else { /* size == 3 */
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 09/16] target/arm: Enable ARM_FEATURE_V8_RDM
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (7 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 08/16] target/arm: Decode aa32 armv8.1 two reg and a scalar Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-03-01 13:19 ` Peter Maydell
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 10/16] target/arm: Add ARM_FEATURE_V8_FCMA Richard Henderson
` (6 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Enable it for the "any" CPU used by *-linux-user.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1b3ae62db6..ca5fb1162a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1650,6 +1650,7 @@ static void arm_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
cpu->midr = 0xffffffff;
}
#endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 9743bdc8c3..7246866e7d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -230,6 +230,7 @@ static void aarch64_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [PATCH v3 09/16] target/arm: Enable ARM_FEATURE_V8_RDM
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 09/16] target/arm: Enable ARM_FEATURE_V8_RDM Richard Henderson
@ 2018-03-01 13:19 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 13:19 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 28 February 2018 at 19:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Enable it for the "any" CPU used by *-linux-user.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.c | 1 +
> target/arm/cpu64.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 1b3ae62db6..ca5fb1162a 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1650,6 +1650,7 @@ static void arm_any_initfn(Object *obj)
> set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
> set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> set_feature(&cpu->env, ARM_FEATURE_CRC);
> + set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
> cpu->midr = 0xffffffff;
> }
> #endif
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 9743bdc8c3..7246866e7d 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -230,6 +230,7 @@ static void aarch64_any_initfn(Object *obj)
> set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
> set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> set_feature(&cpu->env, ARM_FEATURE_CRC);
> + set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
> set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
> cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
> cpu->dcz_blocksize = 7; /* 512 bytes */
> --
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PATCH v3 10/16] target/arm: Add ARM_FEATURE_V8_FCMA
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (8 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 09/16] target/arm: Enable ARM_FEATURE_V8_RDM Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 11/16] target/arm: Decode aa64 armv8.3 fcadd Richard Henderson
` (5 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Not enabled anywhere yet.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 1 +
linux-user/elfload.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7c8e87544a..f67f357724 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1429,6 +1429,7 @@ enum arm_features {
ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */
ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
+ ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */
};
static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 63cadae1b4..3ead6ed807 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -552,6 +552,7 @@ static uint32_t get_elf_hwcap(void)
GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4);
GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512);
GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM);
+ GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA);
#undef GET_FEATURE
return hwcaps;
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 11/16] target/arm: Decode aa64 armv8.3 fcadd
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (9 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 10/16] target/arm: Add ARM_FEATURE_V8_FCMA Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla Richard Henderson
` (4 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 7 ++++
target/arm/translate-a64.c | 48 ++++++++++++++++++++++-
target/arm/vec_helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 151 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 7f0d3b2d84..1e2d7025de 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -578,6 +578,13 @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#endif
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e4d2d548ba..efed4fd9d2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -713,6 +713,21 @@ static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd,
is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
}
+/* Expand a 3-operand + fpstatus pointer + simd data value operation using
+ * an out-of-line helper.
+ */
+static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
+ int rm, bool is_fp16, int data,
+ gen_helper_gvec_3_ptr *fn)
+{
+ TCGv_ptr fpst = get_fpstatus_ptr(is_fp16);
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), fpst,
+ is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
+ tcg_temp_free_ptr(fpst);
+}
+
/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
* than the 32 bit equivalent.
*/
@@ -10816,7 +10831,7 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
int size = extract32(insn, 22, 2);
bool u = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
- int feature;
+ int feature, rot;
switch (u * 16 + opcode) {
case 0x10: /* SQRDMLAH (vector) */
@@ -10827,6 +10842,16 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
feature = ARM_FEATURE_V8_RDM;
break;
+ case 0xc: /* FCADD, #90 */
+ case 0xe: /* FCADD, #270 */
+ if (size == 0
+ || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
+ || (size == 3 && !is_q)) {
+ unallocated_encoding(s);
+ return;
+ }
+ feature = ARM_FEATURE_V8_FCMA;
+ break;
default:
unallocated_encoding(s);
return;
@@ -10866,6 +10891,27 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
return;
+ case 0xc: /* FCADD, #90 */
+ case 0xe: /* FCADD, #270 */
+ rot = extract32(opcode, 1, 1);
+ switch (size) {
+ case 1:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
+ gen_helper_gvec_fcaddh);
+ break;
+ case 2:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
+ gen_helper_gvec_fcadds);
+ break;
+ case 3:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
+ gen_helper_gvec_fcaddd);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return;
+
default:
g_assert_not_reached();
}
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 3072df4d77..a868ca6aac 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -22,8 +22,21 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
+#include "fpu/softfloat.h"
+/* Note that vector data is stored in host-endian 64-bit chunks,
+ so addressing units smaller than that needs a host-endian fixup. */
+#ifdef HOST_WORDS_BIGENDIAN
+#define H1(x) ((x) ^ 7)
+#define H2(x) ((x) ^ 3)
+#define H4(x) ((x) ^ 1)
+#else
+#define H1(x) (x)
+#define H2(x) (x)
+#define H4(x) (x)
+#endif
+
#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
@@ -181,3 +194,87 @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
+
+void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ float16 *d = vd;
+ float16 *n = vn;
+ float16 *m = vm;
+ float_status *fpst = vfpst;
+ uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t neg_imag = neg_real ^ 1;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<= 15;
+ neg_imag <<= 15;
+
+ for (i = 0; i < opr_sz / 2; i += 2) {
+ float16 e0 = n[H2(i)];
+ float16 e1 = m[H2(i + 1)] ^ neg_imag;
+ float16 e2 = n[H2(i + 1)];
+ float16 e3 = m[H2(i)] ^ neg_real;
+
+ d[H2(i)] = float16_add(e0, e1, fpst);
+ d[H2(i + 1)] = float16_add(e2, e3, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ float32 *d = vd;
+ float32 *n = vn;
+ float32 *m = vm;
+ float_status *fpst = vfpst;
+ uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t neg_imag = neg_real ^ 1;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<= 31;
+ neg_imag <<= 31;
+
+ for (i = 0; i < opr_sz / 4; i += 2) {
+ float32 e0 = n[H4(i)];
+ float32 e1 = m[H4(i + 1)] ^ neg_imag;
+ float32 e2 = n[H4(i + 1)];
+ float32 e3 = m[H4(i)] ^ neg_real;
+
+ d[H4(i)] = float32_add(e0, e1, fpst);
+ d[H4(i + 1)] = float32_add(e2, e3, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ float64 *d = vd;
+ float64 *n = vn;
+ float64 *m = vm;
+ float_status *fpst = vfpst;
+ uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
+ uint64_t neg_imag = neg_real ^ 1;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<= 63;
+ neg_imag <<= 63;
+
+ for (i = 0; i < opr_sz / 8; i += 2) {
+ float64 e0 = n[i];
+ float64 e1 = m[i + 1] ^ neg_imag;
+ float64 e2 = n[i + 1];
+ float64 e3 = m[i] ^ neg_real;
+
+ d[i] = float64_add(e0, e1, fpst);
+ d[i + 1] = float64_add(e2, e3, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (10 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 11/16] target/arm: Decode aa64 armv8.3 fcadd Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-03-01 13:33 ` Peter Maydell
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 13/16] target/arm: Decode aa32 armv8.3 3-same Richard Henderson
` (3 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 11 ++++
target/arm/translate-a64.c | 94 +++++++++++++++++++++++++---
target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 246 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 1e2d7025de..0d2094f2be 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -585,6 +585,17 @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#endif
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index efed4fd9d2..31ff0479e6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10842,6 +10842,10 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
feature = ARM_FEATURE_V8_RDM;
break;
+ case 0x8: /* FCMLA, #0 */
+ case 0x9: /* FCMLA, #90 */
+ case 0xa: /* FCMLA, #180 */
+ case 0xb: /* FCMLA, #270 */
case 0xc: /* FCADD, #90 */
case 0xe: /* FCADD, #270 */
if (size == 0
@@ -10891,6 +10895,29 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
return;
+ case 0x8: /* FCMLA, #0 */
+ case 0x9: /* FCMLA, #90 */
+ case 0xa: /* FCMLA, #180 */
+ case 0xb: /* FCMLA, #270 */
+ rot = extract32(opcode, 0, 2);
+ switch (size) {
+ case 1:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot,
+ gen_helper_gvec_fcmlah);
+ break;
+ case 2:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
+ gen_helper_gvec_fcmlas);
+ break;
+ case 3:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
+ gen_helper_gvec_fcmlad);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return;
+
case 0xc: /* FCADD, #90 */
case 0xe: /* FCADD, #270 */
rot = extract32(opcode, 1, 1);
@@ -11993,7 +12020,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
bool is_long = false;
- bool is_fp = false;
+ int is_fp = 0;
bool is_fp16 = false;
int index;
TCGv_ptr fpst;
@@ -12031,7 +12058,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
case 0x05: /* FMLS */
case 0x09: /* FMUL */
case 0x19: /* FMULX */
- is_fp = true;
+ is_fp = 1;
break;
case 0x1d: /* SQRDMLAH */
case 0x1f: /* SQRDMLSH */
@@ -12040,20 +12067,28 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
return;
}
break;
+ case 0x11: /* FCMLA #0 */
+ case 0x13: /* FCMLA #90 */
+ case 0x15: /* FCMLA #180 */
+ case 0x17: /* FCMLA #270 */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) {
+ unallocated_encoding(s);
+ return;
+ }
+ is_fp = 2;
+ break;
default:
unallocated_encoding(s);
return;
}
- if (is_fp) {
+ switch (is_fp) {
+ case 1: /* normal fp */
/* convert insn encoded size to TCGMemOp size */
switch (size) {
case 0: /* half-precision */
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
- unallocated_encoding(s);
- return;
- }
size = MO_16;
+ is_fp16 = true;
break;
case MO_32: /* single precision */
case MO_64: /* double precision */
@@ -12062,13 +12097,39 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
return;
}
- } else {
+ break;
+
+ case 2: /* complex fp */
+ /* Each indexable element is a complex pair. */
+ size <<= 1;
+ switch (size) {
+ case MO_32:
+ if (h && !is_q) {
+ unallocated_encoding(s);
+ return;
+ }
+ is_fp16 = true;
+ break;
+ case MO_64:
+ break;
+ default:
+ unallocated_encoding(s);
+ return;
+ }
+ break;
+
+ default: /* integer */
switch (size) {
case MO_8:
case MO_64:
unallocated_encoding(s);
return;
}
+ break;
+ }
+ if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ unallocated_encoding(s);
+ return;
}
/* Given TCGMemOp size, adjust register and indexing. */
@@ -12102,6 +12163,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
fpst = NULL;
}
+ switch (16 * u + opcode) {
+ case 0x11: /* FCMLA #0 */
+ case 0x13: /* FCMLA #90 */
+ case 0x15: /* FCMLA #180 */
+ case 0x17: /* FCMLA #270 */
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_reg_offset(s, rm, index, size), fpst,
+ is_q ? 16 : 8, vec_full_reg_size(s),
+ extract32(insn, 13, 2), /* rot */
+ size == MO_64
+ ? gen_helper_gvec_fcmlas_idx
+ : gen_helper_gvec_fcmlah_idx);
+ tcg_temp_free_ptr(fpst);
+ return;
+ }
+
if (size == 3) {
TCGv_i64 tcg_idx = tcg_temp_new_i64();
int pass;
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index a868ca6aac..d81eb7730d 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -278,3 +278,152 @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
+
+void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ float16 *d = vd;
+ float16 *n = vn;
+ float16 *m = vm;
+ float_status *fpst = vfpst;
+ intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint32_t neg_real = flip ^ neg_imag;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<= 15;
+ neg_imag <<= 15;
+
+ for (i = 0; i < opr_sz / 2; i += 2) {
+ float16 e1 = n[H2(i + flip)];
+ float16 e2 = m[H2(i + flip)] ^ neg_real;
+ float16 e3 = e1;
+ float16 e4 = m[H2(i + 1 - flip)] ^ neg_imag;
+
+ d[H2(i)] = float16_muladd(e1, e2, d[H2(i)], 0, fpst);
+ d[H2(i + 1)] = float16_muladd(e3, e4, d[H2(i + 1)], 0, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ float16 *d = vd;
+ float16 *n = vn;
+ float16 *m = vm;
+ float_status *fpst = vfpst;
+ intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint32_t neg_real = flip ^ neg_imag;
+ uintptr_t i;
+ float16 e2 = m[H2(flip)];
+ float16 e4 = m[H2(1 - flip)];
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<= 15;
+ neg_imag <<= 15;
+ e2 ^= neg_real;
+ e4 ^= neg_imag;
+
+ for (i = 0; i < opr_sz / 2; i += 2) {
+ float16 e1 = n[H2(i + flip)];
+ float16 e3 = e1;
+
+ d[H2(i)] = float16_muladd(e1, e2, d[H2(i)], 0, fpst);
+ d[H2(i + 1)] = float16_muladd(e3, e4, d[H2(i + 1)], 0, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ float32 *d = vd;
+ float32 *n = vn;
+ float32 *m = vm;
+ float_status *fpst = vfpst;
+ intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint32_t neg_real = flip ^ neg_imag;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<= 31;
+ neg_imag <<= 31;
+
+ for (i = 0; i < opr_sz / 4; i += 2) {
+ float32 e1 = n[H4(i + flip)];
+ float32 e2 = m[H4(i + flip)] ^ neg_real;
+ float32 e3 = e1;
+ float32 e4 = m[H4(i + 1 - flip)] ^ neg_imag;
+
+ d[H4(i)] = float32_muladd(e1, e2, d[H4(i)], 0, fpst);
+ d[H4(i + 1)] = float32_muladd(e3, e4, d[H4(i + 1)], 0, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ float32 *d = vd;
+ float32 *n = vn;
+ float32 *m = vm;
+ float_status *fpst = vfpst;
+ intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint32_t neg_real = flip ^ neg_imag;
+ uintptr_t i;
+ float32 e2 = m[H4(flip)];
+ float32 e4 = m[H4(1 - flip)];
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<= 31;
+ neg_imag <<= 31;
+ e2 ^= neg_real;
+ e4 ^= neg_imag;
+
+ for (i = 0; i < opr_sz / 4; i += 2) {
+ float32 e1 = n[H4(i + flip)];
+ float32 e3 = e1;
+
+ d[H4(i)] = float32_muladd(e1, e2, d[H4(i)], 0, fpst);
+ d[H4(i + 1)] = float32_muladd(e3, e4, d[H4(i + 1)], 0, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz = simd_oprsz(desc);
+ float64 *d = vd;
+ float64 *n = vn;
+ float64 *m = vm;
+ float_status *fpst = vfpst;
+ intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint64_t neg_real = flip ^ neg_imag;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<= 63;
+ neg_imag <<= 63;
+
+ for (i = 0; i < opr_sz / 8; i += 2) {
+ float64 e1 = n[i + flip];
+ float64 e2 = m[i + flip] ^ neg_real;
+ float64 e3 = e1;
+ float64 e4 = m[i + 1 - flip] ^ neg_imag;
+
+ d[i] = float64_muladd(e1, e2, d[i], 0, fpst);
+ d[i + 1] = float64_muladd(e3, e4, d[i + 1], 0, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla Richard Henderson
@ 2018-03-01 13:33 ` Peter Maydell
2018-03-01 14:27 ` Peter Maydell
2018-03-01 15:28 ` Peter Maydell
0 siblings, 2 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 13:33 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 28 February 2018 at 19:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.h | 11 ++++
> target/arm/translate-a64.c | 94 +++++++++++++++++++++++++---
> target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 246 insertions(+), 8 deletions(-)
>
> diff --git a/target/arm/helper.h b/target/arm/helper.h
> index 1e2d7025de..0d2094f2be 100644
> --- a/target/arm/helper.h
> +++ b/target/arm/helper.h
> @@ -585,6 +585,17 @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
> DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
> void, ptr, ptr, ptr, ptr, i32)
>
> +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG,
> + void, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG,
> + void, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG,
> + void, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG,
> + void, ptr, ptr, ptr, ptr, i32)
> +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG,
> + void, ptr, ptr, ptr, ptr, i32)
> +
> #ifdef TARGET_AARCH64
> #include "helper-a64.h"
> #endif
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index efed4fd9d2..31ff0479e6 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -10842,6 +10842,10 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
> }
> feature = ARM_FEATURE_V8_RDM;
> break;
> + case 0x8: /* FCMLA, #0 */
> + case 0x9: /* FCMLA, #90 */
> + case 0xa: /* FCMLA, #180 */
> + case 0xb: /* FCMLA, #270 */
> case 0xc: /* FCADD, #90 */
> case 0xe: /* FCADD, #270 */
> if (size == 0
> @@ -10891,6 +10895,29 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
> }
> return;
>
> + case 0x8: /* FCMLA, #0 */
> + case 0x9: /* FCMLA, #90 */
> + case 0xa: /* FCMLA, #180 */
> + case 0xb: /* FCMLA, #270 */
> + rot = extract32(opcode, 0, 2);
> + switch (size) {
> + case 1:
> + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot,
> + gen_helper_gvec_fcmlah);
> + break;
> + case 2:
> + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
> + gen_helper_gvec_fcmlas);
> + break;
> + case 3:
> + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
> + gen_helper_gvec_fcmlad);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + return;
> +
> case 0xc: /* FCADD, #90 */
> case 0xe: /* FCADD, #270 */
> rot = extract32(opcode, 1, 1);
Shouldn't there be a feature check on ARM_FEATURE_V8_FCMA somewhere
in the three_reg_same_extra code path?
> diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
> index a868ca6aac..d81eb7730d 100644
> --- a/target/arm/vec_helper.c
> +++ b/target/arm/vec_helper.c
> @@ -278,3 +278,152 @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
> }
> clear_tail(d, opr_sz, simd_maxsz(desc));
> }
> +
> +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
> + void *vfpst, uint32_t desc)
> +{
> + uintptr_t opr_sz = simd_oprsz(desc);
> + float16 *d = vd;
> + float16 *n = vn;
> + float16 *m = vm;
> + float_status *fpst = vfpst;
> + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
> + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
> + uint32_t neg_real = flip ^ neg_imag;
> + uintptr_t i;
> +
> + /* Shift boolean to the sign bit so we can xor to negate. */
> + neg_real <<= 15;
> + neg_imag <<= 15;
> +
> + for (i = 0; i < opr_sz / 2; i += 2) {
> + float16 e1 = n[H2(i + flip)];
> + float16 e2 = m[H2(i + flip)] ^ neg_real;
> + float16 e3 = e1;
> + float16 e4 = m[H2(i + 1 - flip)] ^ neg_imag;
These don't match up with the element1 ... element4 in the
Arm ARM pseudocode. It's e2 and e4 that are always the same,
not e1 and e3. Ditto in the other functions.
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla
2018-03-01 13:33 ` Peter Maydell
@ 2018-03-01 14:27 ` Peter Maydell
2018-03-01 15:28 ` Peter Maydell
1 sibling, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 14:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 1 March 2018 at 13:33, Peter Maydell <peter.maydell@linaro.org> wrote:
> Shouldn't there be a feature check on ARM_FEATURE_V8_FCMA somewhere
> in the three_reg_same_extra code path?
Oh, there is, because FCADD &c are also (feature bit name
notwithstanding) under that feature bit.
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla
2018-03-01 13:33 ` Peter Maydell
2018-03-01 14:27 ` Peter Maydell
@ 2018-03-01 15:28 ` Peter Maydell
2018-03-01 15:37 ` Peter Maydell
1 sibling, 1 reply; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 15:28 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 1 March 2018 at 13:33, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 February 2018 at 19:31, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/helper.h | 11 ++++
>> target/arm/translate-a64.c | 94 +++++++++++++++++++++++++---
>> target/arm/vec_helper.c | 149 +++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 246 insertions(+), 8 deletions(-)
>>
>> diff --git a/target/arm/helper.h b/target/arm/helper.h
>> index 1e2d7025de..0d2094f2be 100644
>> --- a/target/arm/helper.h
>> +++ b/target/arm/helper.h
>> @@ -585,6 +585,17 @@ DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
>> DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
>> void, ptr, ptr, ptr, ptr, i32)
>>
>> +DEF_HELPER_FLAGS_5(gvec_fcmlah, TCG_CALL_NO_RWG,
>> + void, ptr, ptr, ptr, ptr, i32)
>> +DEF_HELPER_FLAGS_5(gvec_fcmlah_idx, TCG_CALL_NO_RWG,
>> + void, ptr, ptr, ptr, ptr, i32)
>> +DEF_HELPER_FLAGS_5(gvec_fcmlas, TCG_CALL_NO_RWG,
>> + void, ptr, ptr, ptr, ptr, i32)
>> +DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG,
>> + void, ptr, ptr, ptr, ptr, i32)
>> +DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG,
>> + void, ptr, ptr, ptr, ptr, i32)
>> +
>> #ifdef TARGET_AARCH64
>> #include "helper-a64.h"
>> #endif
>> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
>> index efed4fd9d2..31ff0479e6 100644
>> --- a/target/arm/translate-a64.c
>> +++ b/target/arm/translate-a64.c
>> @@ -10842,6 +10842,10 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
>> }
>> feature = ARM_FEATURE_V8_RDM;
>> break;
>> + case 0x8: /* FCMLA, #0 */
>> + case 0x9: /* FCMLA, #90 */
>> + case 0xa: /* FCMLA, #180 */
>> + case 0xb: /* FCMLA, #270 */
>> case 0xc: /* FCADD, #90 */
>> case 0xe: /* FCADD, #270 */
>> if (size == 0
>> @@ -10891,6 +10895,29 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
>> }
>> return;
>>
>> + case 0x8: /* FCMLA, #0 */
>> + case 0x9: /* FCMLA, #90 */
>> + case 0xa: /* FCMLA, #180 */
>> + case 0xb: /* FCMLA, #270 */
>> + rot = extract32(opcode, 0, 2);
>> + switch (size) {
>> + case 1:
>> + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot,
>> + gen_helper_gvec_fcmlah);
>> + break;
>> + case 2:
>> + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
>> + gen_helper_gvec_fcmlas);
>> + break;
>> + case 3:
>> + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
>> + gen_helper_gvec_fcmlad);
>> + break;
>> + default:
>> + g_assert_not_reached();
>> + }
>> + return;
>> +
>> case 0xc: /* FCADD, #90 */
>> case 0xe: /* FCADD, #270 */
>> rot = extract32(opcode, 1, 1);
>
> Shouldn't there be a feature check on ARM_FEATURE_V8_FCMA somewhere
> in the three_reg_same_extra code path?
>
>
>> diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
>> index a868ca6aac..d81eb7730d 100644
>> --- a/target/arm/vec_helper.c
>> +++ b/target/arm/vec_helper.c
>> @@ -278,3 +278,152 @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
>> }
>> clear_tail(d, opr_sz, simd_maxsz(desc));
>> }
>> +
>> +void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
>> + void *vfpst, uint32_t desc)
>> +{
>> + uintptr_t opr_sz = simd_oprsz(desc);
>> + float16 *d = vd;
>> + float16 *n = vn;
>> + float16 *m = vm;
>> + float_status *fpst = vfpst;
>> + intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
>> + uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
>> + uint32_t neg_real = flip ^ neg_imag;
>> + uintptr_t i;
>> +
>> + /* Shift boolean to the sign bit so we can xor to negate. */
>> + neg_real <<= 15;
>> + neg_imag <<= 15;
>> +
>> + for (i = 0; i < opr_sz / 2; i += 2) {
>> + float16 e1 = n[H2(i + flip)];
>> + float16 e2 = m[H2(i + flip)] ^ neg_real;
>> + float16 e3 = e1;
>> + float16 e4 = m[H2(i + 1 - flip)] ^ neg_imag;
>
> These don't match up with the element1 ... element4 in the
> Arm ARM pseudocode. It's e2 and e4 that are always the same,
> not e1 and e3. Ditto in the other functions.
Specifically I think:
this code pseudocode
e1 element2
e2 element1
e3 element4
e4 element2
So if we renumber these to match the pseudocode
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla
2018-03-01 15:28 ` Peter Maydell
@ 2018-03-01 15:37 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 15:37 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 1 March 2018 at 15:28, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 1 March 2018 at 13:33, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 28 February 2018 at 19:31, Richard Henderson
>> <richard.henderson@linaro.org> wrote:
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> These don't match up with the element1 ... element4 in the
>> Arm ARM pseudocode. It's e2 and e4 that are always the same,
>> not e1 and e3. Ditto in the other functions.
>
> Specifically I think:
> this code pseudocode
> e1 element2
> e2 element1
> e3 element4
> e4 element2
>
> So if we renumber these to match the pseudocode
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Since this is the only issue in this patchset I propose to squash
in this:
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index d81eb7730d..ec705cfca5 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -297,13 +297,13 @@ void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
neg_imag <<= 15;
for (i = 0; i < opr_sz / 2; i += 2) {
- float16 e1 = n[H2(i + flip)];
- float16 e2 = m[H2(i + flip)] ^ neg_real;
- float16 e3 = e1;
- float16 e4 = m[H2(i + 1 - flip)] ^ neg_imag;
+ float16 e2 = n[H2(i + flip)];
+ float16 e1 = m[H2(i + flip)] ^ neg_real;
+ float16 e4 = e2;
+ float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag;
- d[H2(i)] = float16_muladd(e1, e2, d[H2(i)], 0, fpst);
- d[H2(i + 1)] = float16_muladd(e3, e4, d[H2(i + 1)], 0, fpst);
+ d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
+ d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
@@ -320,21 +320,21 @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm,
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
uint32_t neg_real = flip ^ neg_imag;
uintptr_t i;
- float16 e2 = m[H2(flip)];
- float16 e4 = m[H2(1 - flip)];
+ float16 e1 = m[H2(flip)];
+ float16 e3 = m[H2(1 - flip)];
/* Shift boolean to the sign bit so we can xor to negate. */
neg_real <<= 15;
neg_imag <<= 15;
- e2 ^= neg_real;
- e4 ^= neg_imag;
+ e1 ^= neg_real;
+ e3 ^= neg_imag;
for (i = 0; i < opr_sz / 2; i += 2) {
- float16 e1 = n[H2(i + flip)];
- float16 e3 = e1;
+ float16 e2 = n[H2(i + flip)];
+ float16 e4 = e2;
- d[H2(i)] = float16_muladd(e1, e2, d[H2(i)], 0, fpst);
- d[H2(i + 1)] = float16_muladd(e3, e4, d[H2(i + 1)], 0, fpst);
+ d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
+ d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
@@ -357,13 +357,13 @@ void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm,
neg_imag <<= 31;
for (i = 0; i < opr_sz / 4; i += 2) {
- float32 e1 = n[H4(i + flip)];
- float32 e2 = m[H4(i + flip)] ^ neg_real;
- float32 e3 = e1;
- float32 e4 = m[H4(i + 1 - flip)] ^ neg_imag;
+ float32 e2 = n[H4(i + flip)];
+ float32 e1 = m[H4(i + flip)] ^ neg_real;
+ float32 e4 = e2;
+ float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag;
- d[H4(i)] = float32_muladd(e1, e2, d[H4(i)], 0, fpst);
- d[H4(i + 1)] = float32_muladd(e3, e4, d[H4(i + 1)], 0, fpst);
+ d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
+ d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
@@ -380,21 +380,21 @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm,
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
uint32_t neg_real = flip ^ neg_imag;
uintptr_t i;
- float32 e2 = m[H4(flip)];
- float32 e4 = m[H4(1 - flip)];
+ float32 e1 = m[H4(flip)];
+ float32 e3 = m[H4(1 - flip)];
/* Shift boolean to the sign bit so we can xor to negate. */
neg_real <<= 31;
neg_imag <<= 31;
- e2 ^= neg_real;
- e4 ^= neg_imag;
+ e1 ^= neg_real;
+ e3 ^= neg_imag;
for (i = 0; i < opr_sz / 4; i += 2) {
- float32 e1 = n[H4(i + flip)];
- float32 e3 = e1;
+ float32 e2 = n[H4(i + flip)];
+ float32 e4 = e2;
- d[H4(i)] = float32_muladd(e1, e2, d[H4(i)], 0, fpst);
- d[H4(i + 1)] = float32_muladd(e3, e4, d[H4(i + 1)], 0, fpst);
+ d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
+ d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
@@ -417,13 +417,13 @@ void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm,
neg_imag <<= 63;
for (i = 0; i < opr_sz / 8; i += 2) {
- float64 e1 = n[i + flip];
- float64 e2 = m[i + flip] ^ neg_real;
- float64 e3 = e1;
- float64 e4 = m[i + 1 - flip] ^ neg_imag;
+ float64 e2 = n[i + flip];
+ float64 e1 = m[i + flip] ^ neg_real;
+ float64 e4 = e2;
+ float64 e3 = m[i + 1 - flip] ^ neg_imag;
- d[i] = float64_muladd(e1, e2, d[i], 0, fpst);
- d[i + 1] = float64_muladd(e3, e4, d[i + 1], 0, fpst);
+ d[i] = float64_muladd(e2, e1, d[i], 0, fpst);
+ d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
which is a basically mechanical rename, and put it into target-arm.next.
thanks
-- PMM
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [PATCH v3 13/16] target/arm: Decode aa32 armv8.3 3-same
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (11 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 12/16] target/arm: Decode aa64 armv8.3 fcmla Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-03-01 13:53 ` Peter Maydell
2018-03-01 14:01 ` Peter Maydell
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 14/16] target/arm: Decode aa32 armv8.3 2-reg-index Richard Henderson
` (2 subsequent siblings)
15 siblings, 2 replies; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9169b6b367..45513c9d86 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7680,6 +7680,68 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
return 0;
}
+/* Advanced SIMD three registers of the same length extension.
+ * 31 25 23 22 20 16 12 11 10 9 8 3 0
+ * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
+ * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
+ * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
+ */
+static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
+{
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
+ int rd, rn, rm, rot, size, opr_sz;
+ TCGv_ptr fpst;
+ bool q;
+
+ q = extract32(insn, 6, 1);
+ VFP_DREG_D(rd, insn);
+ VFP_DREG_N(rn, insn);
+ VFP_DREG_M(rm, insn);
+ if ((rd | rn | rm) & q) {
+ return 1;
+ }
+
+ if ((insn & 0xfe200f10) == 0xfc200800) {
+ /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
+ size = extract32(insn, 20, 1);
+ rot = extract32(insn, 23, 2);
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)
+ || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
+ return 1;
+ }
+ fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
+ } else if ((insn & 0xfea00f10) == 0xfc800800) {
+ /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
+ size = extract32(insn, 20, 1);
+ rot = extract32(insn, 24, 1);
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)
+ || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
+ return 1;
+ }
+ fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
+ } else {
+ return 1;
+ }
+
+ if (s->fp_excp_el) {
+ gen_exception_insn(s, 4, EXCP_UDEF,
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
+ return 0;
+ }
+ if (!s->vfp_enabled) {
+ return 1;
+ }
+
+ opr_sz = (1 + q) * 8;
+ fpst = get_fpstatus_ptr(1);
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
+ vfp_reg_offset(1, rn),
+ vfp_reg_offset(1, rm), fpst,
+ opr_sz, opr_sz, rot, fn_gvec_ptr);
+ tcg_temp_free_ptr(fpst);
+ return 0;
+}
+
static int disas_coproc_insn(DisasContext *s, uint32_t insn)
{
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -8424,6 +8486,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
}
}
+ } else if ((insn & 0x0e000a00) == 0x0c000800
+ && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ if (disas_neon_insn_3same_ext(s, insn)) {
+ goto illegal_op;
+ }
+ return;
} else if ((insn & 0x0fe00000) == 0x0c400000) {
/* Coprocessor double register transfer. */
ARCH(5TE);
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [PATCH v3 13/16] target/arm: Decode aa32 armv8.3 3-same
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 13/16] target/arm: Decode aa32 armv8.3 3-same Richard Henderson
@ 2018-03-01 13:53 ` Peter Maydell
2018-03-01 14:01 ` Peter Maydell
1 sibling, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 13:53 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 28 February 2018 at 19:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 9169b6b367..45513c9d86 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7680,6 +7680,68 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
> return 0;
> }
>
> +/* Advanced SIMD three registers of the same length extension.
> + * 31 25 23 22 20 16 12 11 10 9 8 3 0
> + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
> + * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
> + * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
> + */
> +static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
> +{
> + gen_helper_gvec_3_ptr *fn_gvec_ptr;
> + int rd, rn, rm, rot, size, opr_sz;
> + TCGv_ptr fpst;
> + bool q;
> +
> + q = extract32(insn, 6, 1);
> + VFP_DREG_D(rd, insn);
> + VFP_DREG_N(rn, insn);
> + VFP_DREG_M(rm, insn);
> + if ((rd | rn | rm) & q) {
> + return 1;
> + }
> +
> + if ((insn & 0xfe200f10) == 0xfc200800) {
Slightly confusing to be re-checking bits we've already decoded,
rather than just looking at op1/op2/op3/op4/Q/U.
Anyway
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [PATCH v3 13/16] target/arm: Decode aa32 armv8.3 3-same
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 13/16] target/arm: Decode aa32 armv8.3 3-same Richard Henderson
2018-03-01 13:53 ` Peter Maydell
@ 2018-03-01 14:01 ` Peter Maydell
1 sibling, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 14:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 28 February 2018 at 19:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
> @@ -8424,6 +8486,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> }
> }
> }
> + } else if ((insn & 0x0e000a00) == 0x0c000800
> + && arm_dc_feature(s, ARM_FEATURE_V8)) {
> + if (disas_neon_insn_3same_ext(s, insn)) {
> + goto illegal_op;
> + }
> + return;
> } else if ((insn & 0x0fe00000) == 0x0c400000) {
> /* Coprocessor double register transfer. */
> ARCH(5TE);
Oh yes, shouldn't there be a similar fragment in disas_thumb2_insn()
to take care of the Thumb encodings of these insns ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PATCH v3 14/16] target/arm: Decode aa32 armv8.3 2-reg-index
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (12 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 13/16] target/arm: Decode aa32 armv8.3 3-same Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-03-01 14:05 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 15/16] target/arm: Decode t32 simd 3reg and 2reg_scalar extension Richard Henderson
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 16/16] target/arm: Enable ARM_FEATURE_V8_FCMA Richard Henderson
15 siblings, 1 reply; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 45513c9d86..3ad8b4031c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7742,6 +7742,61 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
return 0;
}
+/* Advanced SIMD two registers and a scalar extension.
+ * 31 24 23 22 20 16 12 11 10 9 8 3 0
+ * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
+ * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
+ * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
+ *
+ */
+
+static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
+{
+ int rd, rn, rm, rot, size, opr_sz;
+ TCGv_ptr fpst;
+ bool q;
+
+ q = extract32(insn, 6, 1);
+ VFP_DREG_D(rd, insn);
+ VFP_DREG_N(rn, insn);
+ VFP_DREG_M(rm, insn);
+ if ((rd | rn) & q) {
+ return 1;
+ }
+
+ if ((insn & 0xff000f10) == 0xfe000800) {
+ /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
+ rot = extract32(insn, 20, 2);
+ size = extract32(insn, 23, 1);
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)
+ || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
+ return 1;
+ }
+ } else {
+ return 1;
+ }
+
+ if (s->fp_excp_el) {
+ gen_exception_insn(s, 4, EXCP_UDEF,
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
+ return 0;
+ }
+ if (!s->vfp_enabled) {
+ return 1;
+ }
+
+ opr_sz = (1 + q) * 8;
+ fpst = get_fpstatus_ptr(1);
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
+ vfp_reg_offset(1, rn),
+ vfp_reg_offset(1, rm), fpst,
+ opr_sz, opr_sz, rot,
+ size ? gen_helper_gvec_fcmlas_idx
+ : gen_helper_gvec_fcmlah_idx);
+ tcg_temp_free_ptr(fpst);
+ return 0;
+}
+
static int disas_coproc_insn(DisasContext *s, uint32_t insn)
{
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -8492,6 +8547,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
goto illegal_op;
}
return;
+ } else if ((insn & 0x0f000a00) == 0x0e000800
+ && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
+ goto illegal_op;
+ }
+ return;
} else if ((insn & 0x0fe00000) == 0x0c400000) {
/* Coprocessor double register transfer. */
ARCH(5TE);
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [Qemu-arm] [PATCH v3 14/16] target/arm: Decode aa32 armv8.3 2-reg-index
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 14/16] target/arm: Decode aa32 armv8.3 2-reg-index Richard Henderson
@ 2018-03-01 14:05 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 14:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 28 February 2018 at 19:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> @@ -8492,6 +8547,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> goto illegal_op;
> }
> return;
> + } else if ((insn & 0x0f000a00) == 0x0e000800
> + && arm_dc_feature(s, ARM_FEATURE_V8)) {
> + if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
> + goto illegal_op;
> + }
> + return;
> } else if ((insn & 0x0fe00000) == 0x0c400000) {
> /* Coprocessor double register transfer. */
> ARCH(5TE);
Missing the similar code for disas_thumb2_insn() again.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PATCH v3 15/16] target/arm: Decode t32 simd 3reg and 2reg_scalar extension
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (13 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 14/16] target/arm: Decode aa32 armv8.3 2-reg-index Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-03-01 14:07 ` Peter Maydell
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 16/16] target/arm: Enable ARM_FEATURE_V8_FCMA Richard Henderson
15 siblings, 1 reply; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Happily, the bits are in the same places compared to a32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3ad8b4031c..ba6ab7d287 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10774,7 +10774,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
default_exception_el(s));
break;
}
- if (((insn >> 24) & 3) == 3) {
+ if ((insn & 0xfe000a00) == 0xfc000800
+ && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ /* The Thumb2 and ARM encodings are identical. */
+ if (disas_neon_insn_3same_ext(s, insn)) {
+ goto illegal_op;
+ }
+ } else if ((insn & 0xff000a00) == 0xfe000800
+ && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ /* The Thumb2 and ARM encodings are identical. */
+ if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
+ goto illegal_op;
+ }
+ } else if (((insn >> 24) & 3) == 3) {
/* Translate into the equivalent ARM encoding. */
insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
if (disas_neon_data_insn(s, insn)) {
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [PATCH v3 15/16] target/arm: Decode t32 simd 3reg and 2reg_scalar extension
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 15/16] target/arm: Decode t32 simd 3reg and 2reg_scalar extension Richard Henderson
@ 2018-03-01 14:07 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 14:07 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 28 February 2018 at 19:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Happily, the bits are in the same places compared to a32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 3ad8b4031c..ba6ab7d287 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -10774,7 +10774,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> default_exception_el(s));
> break;
> }
> - if (((insn >> 24) & 3) == 3) {
> + if ((insn & 0xfe000a00) == 0xfc000800
> + && arm_dc_feature(s, ARM_FEATURE_V8)) {
> + /* The Thumb2 and ARM encodings are identical. */
> + if (disas_neon_insn_3same_ext(s, insn)) {
> + goto illegal_op;
> + }
> + } else if ((insn & 0xff000a00) == 0xfe000800
> + && arm_dc_feature(s, ARM_FEATURE_V8)) {
> + /* The Thumb2 and ARM encodings are identical. */
> + if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
> + goto illegal_op;
> + }
> + } else if (((insn >> 24) & 3) == 3) {
> /* Translate into the equivalent ARM encoding. */
> insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
> if (disas_neon_data_insn(s, insn)) {
> --
> 2.14.3
Oh, here they are. If you mention "Thumb decode will be added in
a subsequent commit" in a commit message it helps to avoid confusing
reviewers...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [PATCH v3 16/16] target/arm: Enable ARM_FEATURE_V8_FCMA
2018-02-28 19:31 [Qemu-devel] [PATCH v3 00/16] ARM v8.1 simd + v8.3 complex insns Richard Henderson
` (14 preceding siblings ...)
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 15/16] target/arm: Decode t32 simd 3reg and 2reg_scalar extension Richard Henderson
@ 2018-02-28 19:31 ` Richard Henderson
2018-03-01 13:20 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
15 siblings, 1 reply; 30+ messages in thread
From: Richard Henderson @ 2018-02-28 19:31 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Enable it for the "any" CPU used by *-linux-user.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ca5fb1162a..452bc32f10 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1651,6 +1651,7 @@ static void arm_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
+ set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
cpu->midr = 0xffffffff;
}
#endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 7246866e7d..4228713b19 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -232,6 +232,7 @@ static void aarch64_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_CRC);
set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
+ set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
}
--
2.14.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [Qemu-arm] [PATCH v3 16/16] target/arm: Enable ARM_FEATURE_V8_FCMA
2018-02-28 19:31 ` [Qemu-devel] [PATCH v3 16/16] target/arm: Enable ARM_FEATURE_V8_FCMA Richard Henderson
@ 2018-03-01 13:20 ` Peter Maydell
2018-03-01 14:12 ` Peter Maydell
0 siblings, 1 reply; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 13:20 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 28 February 2018 at 19:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Enable it for the "any" CPU used by *-linux-user.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.c | 1 +
> target/arm/cpu64.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index ca5fb1162a..452bc32f10 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1651,6 +1651,7 @@ static void arm_any_initfn(Object *obj)
> set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> set_feature(&cpu->env, ARM_FEATURE_CRC);
> set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
> + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
> cpu->midr = 0xffffffff;
> }
> #endif
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 7246866e7d..4228713b19 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -232,6 +232,7 @@ static void aarch64_any_initfn(Object *obj)
> set_feature(&cpu->env, ARM_FEATURE_CRC);
> set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
> set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
> + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
> cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
> cpu->dcz_blocksize = 7; /* 512 bytes */
> }
> --
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
We should be setting some hwcap bits in linux-user for these new feature
bits (and RDM), right?
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH v3 16/16] target/arm: Enable ARM_FEATURE_V8_FCMA
2018-03-01 13:20 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
@ 2018-03-01 14:12 ` Peter Maydell
0 siblings, 0 replies; 30+ messages in thread
From: Peter Maydell @ 2018-03-01 14:12 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, qemu-arm
On 1 March 2018 at 13:20, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 February 2018 at 19:31, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>> Enable it for the "any" CPU used by *-linux-user.
> We should be setting some hwcap bits in linux-user for these new feature
> bits (and RDM), right?
Oh, you did that back in the patch where you added the feature bit.
Sorry, I'm clearly skimming these patches a little too quickly.
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread