From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erA1a-0003GP-SJ for qemu-devel@nongnu.org; Wed, 28 Feb 2018 17:16:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erA1W-0003BD-LO for qemu-devel@nongnu.org; Wed, 28 Feb 2018 17:16:34 -0500 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:44316) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1erA1W-00038d-0s for qemu-devel@nongnu.org; Wed, 28 Feb 2018 17:16:30 -0500 Received: by mail-lf0-x243.google.com with SMTP id v9so5848320lfa.11 for ; Wed, 28 Feb 2018 14:16:29 -0800 (PST) From: Max Filippov Date: Wed, 28 Feb 2018 14:16:02 -0800 Message-Id: <20180228221609.11265-5-jcmvbkbc@gmail.com> In-Reply-To: <20180228221609.11265-1-jcmvbkbc@gmail.com> References: <20180228221609.11265-1-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH v2 04/11] target/xtensa: support MTTCG List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov , "Emilio G . Cota" - emit TCG barriers for MEMW, EXTW, S32RI and L32AI; - do atomic_cmpxchg_i32 for S32C1I. Cc: Emilio G. Cota Signed-off-by: Max Filippov --- configure | 1 + target/xtensa/cpu.h | 3 +++ target/xtensa/translate.c | 46 +++++++++++++++++++++++++++++++--------------- 3 files changed, 35 insertions(+), 15 deletions(-) diff --git a/configure b/configure index 39f3a4300163..f83bdeb2a550 100755 --- a/configure +++ b/configure @@ -6813,6 +6813,7 @@ case "$target_name" in ;; xtensa|xtensaeb) TARGET_ARCH=xtensa + mttcg="yes" ;; *) error_exit "Unsupported target CPU" diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 255cc9e08ed9..d9d3b33a7052 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -31,6 +31,9 @@ #define ALIGNED_ONLY #define TARGET_LONG_BITS 32 +/* Xtensa processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #define CPUArchState struct CPUXtensaState #include "qemu-common.h" diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 5969d7c3cd96..c06d30d17960 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1664,9 +1664,15 @@ static void translate_ldst(DisasContext *dc, const uint32_t arg[], gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]); } if (par[2]) { + if (par[1]) { + tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL); + } tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); } else { tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + if (par[1]) { + tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL); + } } tcg_temp_free(addr); } @@ -1823,6 +1829,12 @@ static void translate_mac16(DisasContext *dc, const uint32_t arg[], } } +static void translate_memw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); +} + static void translate_minmax(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { @@ -2193,29 +2205,33 @@ static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[], tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); } +#ifdef CONFIG_USER_ONLY +static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) +{ +} +#else +static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) +{ + TCGv_i32 tpc = tcg_const_i32(dc->pc); + + gen_helper_check_atomctl(cpu_env, tpc, addr); + tcg_temp_free(tpc); +} +#endif + static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { if (gen_window_check2(dc, arg[0], arg[1])) { - TCGLabel *label = gen_new_label(); TCGv_i32 tmp = tcg_temp_local_new_i32(); TCGv_i32 addr = tcg_temp_local_new_i32(); - TCGv_i32 tpc; tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); gen_load_store_alignment(dc, 2, addr, true); - - tpc = tcg_const_i32(dc->pc); - gen_helper_check_atomctl(cpu_env, tpc, addr); - tcg_gen_qemu_ld32u(cpu_R[arg[0]], addr, dc->cring); - tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[arg[0]], - cpu_SR[SCOMPARE1], label); - - tcg_gen_qemu_st32(tmp, addr, dc->cring); - - gen_set_label(label); - tcg_temp_free(tpc); + gen_check_atomctl(dc, addr); + tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1], + tmp, dc->cring, MO_32); tcg_temp_free(addr); tcg_temp_free(tmp); } @@ -2828,7 +2844,7 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_extui, }, { .name = "extw", - .translate = translate_nop, + .translate = translate_memw, }, { .name = "hwwdtlba", .translate = translate_ill, @@ -2945,7 +2961,7 @@ static const XtensaOpcodeOps core_ops[] = { .par = (const uint32_t[]){TCG_COND_GEU}, }, { .name = "memw", - .translate = translate_nop, + .translate = translate_memw, }, { .name = "min", .translate = translate_minmax, -- 2.11.0