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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 07/42] hw/sii9022: Add support for Silicon Image SII9022
Date: Thu,  1 Mar 2018 11:23:28 +0000	[thread overview]
Message-ID: <20180301112403.12487-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org>

From: Linus Walleij <linus.walleij@linaro.org>

This adds support for emulating the Silicon Image SII9022 DVI/HDMI
bridge. It's not very clever right now, it just acknowledges
the switch into DDC I2C mode and back. Combining this with the
existing DDC I2C emulation gives the right behavior on the Versatile
Express emulation passing through the QEMU EDID to the emulated
platform.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Message-id: 20180227104903.21353-5-linus.walleij@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: explictly reset ddc_req/ddc_skip_finish/ddc]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/display/Makefile.objs |   1 +
 hw/display/sii9022.c     | 191 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/display/trace-events  |   5 ++
 3 files changed, 197 insertions(+)
 create mode 100644 hw/display/sii9022.c

diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index d3a4cb396e..3c7c75b94d 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_VGA_CIRRUS) += cirrus_vga.o
 common-obj-$(CONFIG_G364FB) += g364fb.o
 common-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
 common-obj-$(CONFIG_PL110) += pl110.o
+common-obj-$(CONFIG_SII9022) += sii9022.o
 common-obj-$(CONFIG_SSD0303) += ssd0303.o
 common-obj-$(CONFIG_SSD0323) += ssd0323.o
 common-obj-$(CONFIG_XEN) += xenfb.o
diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c
new file mode 100644
index 0000000000..eaf11a6e7b
--- /dev/null
+++ b/hw/display/sii9022.c
@@ -0,0 +1,191 @@
+/*
+ * Silicon Image SiI9022
+ *
+ * This is a pretty hollow emulation: all we do is acknowledge that we
+ * exist (chip ID) and confirm that we get switched over into DDC mode
+ * so the emulated host can proceed to read out EDID data. All subsequent
+ * set-up of connectors etc will be acknowledged and ignored.
+ *
+ * Copyright (C) 2018 Linus Walleij
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/i2c/i2c-ddc.h"
+#include "trace.h"
+
+#define SII9022_SYS_CTRL_DATA 0x1a
+#define SII9022_SYS_CTRL_PWR_DWN 0x10
+#define SII9022_SYS_CTRL_AV_MUTE 0x08
+#define SII9022_SYS_CTRL_DDC_BUS_REQ 0x04
+#define SII9022_SYS_CTRL_DDC_BUS_GRTD 0x02
+#define SII9022_SYS_CTRL_OUTPUT_MODE 0x01
+#define SII9022_SYS_CTRL_OUTPUT_HDMI 1
+#define SII9022_SYS_CTRL_OUTPUT_DVI 0
+#define SII9022_REG_CHIPID 0x1b
+#define SII9022_INT_ENABLE 0x3c
+#define SII9022_INT_STATUS 0x3d
+#define SII9022_INT_STATUS_HOTPLUG 0x01;
+#define SII9022_INT_STATUS_PLUGGED 0x04;
+
+#define TYPE_SII9022 "sii9022"
+#define SII9022(obj) OBJECT_CHECK(sii9022_state, (obj), TYPE_SII9022)
+
+typedef struct sii9022_state {
+    I2CSlave parent_obj;
+    uint8_t ptr;
+    bool addr_byte;
+    bool ddc_req;
+    bool ddc_skip_finish;
+    bool ddc;
+} sii9022_state;
+
+static const VMStateDescription vmstate_sii9022 = {
+    .name = "sii9022",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_I2C_SLAVE(parent_obj, sii9022_state),
+        VMSTATE_UINT8(ptr, sii9022_state),
+        VMSTATE_BOOL(addr_byte, sii9022_state),
+        VMSTATE_BOOL(ddc_req, sii9022_state),
+        VMSTATE_BOOL(ddc_skip_finish, sii9022_state),
+        VMSTATE_BOOL(ddc, sii9022_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
+{
+    sii9022_state *s = SII9022(i2c);
+
+    switch (event) {
+    case I2C_START_SEND:
+        s->addr_byte = true;
+        break;
+    case I2C_START_RECV:
+        break;
+    case I2C_FINISH:
+        break;
+    case I2C_NACK:
+        break;
+    }
+
+    return 0;
+}
+
+static int sii9022_rx(I2CSlave *i2c)
+{
+    sii9022_state *s = SII9022(i2c);
+    uint8_t res = 0x00;
+
+    switch (s->ptr) {
+    case SII9022_SYS_CTRL_DATA:
+        if (s->ddc_req) {
+            /* Acknowledge DDC bus request */
+            res = SII9022_SYS_CTRL_DDC_BUS_GRTD | SII9022_SYS_CTRL_DDC_BUS_REQ;
+        }
+        break;
+    case SII9022_REG_CHIPID:
+        res = 0xb0;
+        break;
+    case SII9022_INT_STATUS:
+        /* Something is cold-plugged in, no interrupts */
+        res = SII9022_INT_STATUS_PLUGGED;
+        break;
+    default:
+        break;
+    }
+
+    trace_sii9022_read_reg(s->ptr, res);
+    s->ptr++;
+
+    return res;
+}
+
+static int sii9022_tx(I2CSlave *i2c, uint8_t data)
+{
+    sii9022_state *s = SII9022(i2c);
+
+    if (s->addr_byte) {
+        s->ptr = data;
+        s->addr_byte = false;
+        return 0;
+    }
+
+    switch (s->ptr) {
+    case SII9022_SYS_CTRL_DATA:
+        if (data & SII9022_SYS_CTRL_DDC_BUS_REQ) {
+            s->ddc_req = true;
+            if (data & SII9022_SYS_CTRL_DDC_BUS_GRTD) {
+                s->ddc = true;
+                /* Skip this finish since we just switched to DDC */
+                s->ddc_skip_finish = true;
+                trace_sii9022_switch_mode("DDC");
+            }
+        } else {
+            s->ddc_req = false;
+            s->ddc = false;
+            trace_sii9022_switch_mode("normal");
+        }
+        break;
+    default:
+        break;
+    }
+
+    trace_sii9022_write_reg(s->ptr, data);
+    s->ptr++;
+
+    return 0;
+}
+
+static void sii9022_reset(DeviceState *dev)
+{
+    sii9022_state *s = SII9022(dev);
+
+    s->ptr = 0;
+    s->addr_byte = false;
+    s->ddc_req = false;
+    s->ddc_skip_finish = false;
+    s->ddc = false;
+}
+
+static void sii9022_realize(DeviceState *dev, Error **errp)
+{
+    I2CBus *bus;
+
+    bus = I2C_BUS(qdev_get_parent_bus(dev));
+    i2c_create_slave(bus, TYPE_I2CDDC, 0x50);
+}
+
+static void sii9022_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+
+    k->event = sii9022_event;
+    k->recv = sii9022_rx;
+    k->send = sii9022_tx;
+    dc->reset = sii9022_reset;
+    dc->realize = sii9022_realize;
+    dc->vmsd = &vmstate_sii9022;
+}
+
+static const TypeInfo sii9022_info = {
+    .name          = TYPE_SII9022,
+    .parent        = TYPE_I2C_SLAVE,
+    .instance_size = sizeof(sii9022_state),
+    .class_init    = sii9022_class_init,
+};
+
+static void sii9022_register_types(void)
+{
+    type_register_static(&sii9022_info);
+}
+
+type_init(sii9022_register_types)
diff --git a/hw/display/trace-events b/hw/display/trace-events
index da498c1def..5a48c6cb6a 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -132,3 +132,8 @@ vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
 vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
 vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
 vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
+
+# hw/display/sii9022.c
+sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
+sii9022_write_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
+sii9022_switch_mode(const char *mode) "mode: %s"
-- 
2.16.2

  parent reply	other threads:[~2018-03-01 11:24 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-01 11:23 [Qemu-devel] [PULL 00/42] target-arm queue Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 01/42] hw: register: Run post_write hook on reset Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 02/42] xilinx_spips: Enable only two slaves when reading/writing with stripe Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 04/42] i2c: Fix some brace style issues Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 05/42] i2c: Move the bus class to i2c.h Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 06/42] hw/i2c-ddc: Do not fail writes Peter Maydell
2018-03-01 11:23 ` Peter Maydell [this message]
2018-03-01 11:23 ` [Qemu-devel] [PULL 08/42] arm/vexpress: Add proper display connector emulation Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 09/42] include/exec/helper-head.h: support f16 in helper calls Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 10/42] target/arm/cpu64: introduce ARM_V8_FP16 feature bit Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 11/42] target/arm/cpu.h: update comment for half-precision values Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 12/42] target/arm/cpu.h: add additional float_status flags Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 13/42] target/arm/helper: pass explicit fpst to set_rmode Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 14/42] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 15/42] arm/translate-a64: handle_3same_64 comment fix Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 16/42] arm/translate-a64: initial decode for simd_three_reg_same_fp16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 17/42] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 18/42] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] " Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 19/42] arm/translate-a64: add FP16 FMULA/X/S " Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 20/42] arm/translate-a64: add FP16 FR[ECP/SQRT]S " Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 21/42] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 22/42] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 23/42] arm/translate-a64: add FP16 x2 ops for simd_indexed Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 24/42] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 25/42] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx " Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 27/42] arm/translate-a64: add FP16 FCMxx (zero) " Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 28/42] arm/translate-a64: add FP16 SCVTF/UCVFT " Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS " Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 30/42] arm/helper.c: re-factor recpe and add recepe_f16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 32/42] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 33/42] arm/translate-a64: add FP16 FSQRT " Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 34/42] arm/helper.c: re-factor rsqrte and add rsqrte_f16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 35/42] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 36/42] arm/translate-a64: add FP16 FMOV to simd_mod_imm Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 37/42] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise Peter Maydell
2018-03-01 11:23 ` [Qemu-devel] [PULL 38/42] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 Peter Maydell
2018-03-01 11:24 ` [Qemu-devel] [PULL 39/42] arm/translate-a64: add all single op FP16 to handle_fp_1src_half Peter Maydell
2018-03-01 11:24 ` [Qemu-devel] [PULL 40/42] target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU Peter Maydell
2018-03-01 11:24 ` [Qemu-devel] [PULL 41/42] linux-user: Report AArch64 FP16 support via hwcap bits Peter Maydell
2018-03-01 11:24 ` [Qemu-devel] [PULL 42/42] MAINTAINERS: Update my email address Peter Maydell
2018-03-01 13:00 ` [Qemu-devel] [PULL 00/42] target-arm queue no-reply
2018-03-01 14:45   ` Peter Maydell
2018-03-02  0:52     ` Fam Zheng
2018-03-01 13:01 ` no-reply
2018-03-01 17:08 ` Peter Maydell

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